• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 223 matches

• 2024
• 
  Jakub Husa, Lukás Sekanina:
  Semantic mutation operator for a fast and efficient design of bent Boolean functions. Genet. Program. Evolvable Mach. 25(1): 3 (2024)
• 
  Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina:
  Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. DATE 2024: 1-6
• 
  Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
  Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. DDECS 2024: 1-6
• 
  Michal Pinos, Lukás Sekanina, Vojtech Mrazek:
  ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. IJCNN 2024: 1-8
• 
  Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
  Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. CoRR abs/2404.05368 (2024)
• 
  Michal Pinos, Lukás Sekanina, Vojtech Mrazek:
  ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. CoRR abs/2404.08002 (2024)
• 2023
• 
  Michal Pinos, Vojtech Mrazek, Filip Vaverka, Zdenek Vasícek, Lukás Sekanina:
  Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 212-224 (2023)
• 
  Martin Hurta, Jana Schwarzerova, Thomas Nägele, Wolfram Weckwerth, Valentine Provazník, Lukás Sekanina:
  Utilizing Genetic Programming to Enhance Polygenic Risk Score Calculation. BIBM 2023: 3782-3787
• 
  Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukás Sekanina:
  ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. DATE 2023: 1-2
• 
  Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukás Sekanina:
  MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. DDECS 2023: 155-160
• 
  Michal Pinos, Vojtech Mrazek, Lukás Sekanina:
  Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. DDECS 2023: 45-50
• 
  Tadeas Juza, Lukás Sekanina:
  GPAM: Genetic Programming with Associative Memory. EuroGP 2023: 68-83
• 
  Marek Sedlacek, Lukás Sekanina:
  Evolution of Editing Scripts From Examples. GECCO Companion 2023: 803-806
• 
  Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
  Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. ICCAD 2023: 1-9
• 
  Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
  autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. CoRR abs/2303.04734 (2023)
• 2022
• 
  Michal Pinos, Vojtech Mrazek, Lukás Sekanina:
  Evolutionary approximation and neural architecture search. Genet. Program. Evolvable Mach. 23(3): 351-374 (2022)
• 
  Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar:
  SagTree: Towards efficient mutation in evolutionary circuit approximation. Swarm Evol. Comput. 69: 100986 (2022)
• 
  Martin Hurta, Michaela Drahosova, Lukás Sekanina, Stephen L. Smith, Jane E. Alty:
  Evolutionary Design of Reduced Precision Levodopa-Induced Dyskinesia Classifiers. EuroGP 2022: 85-101
• 
  Matej Valek, Lukás Sekanina:
  Evolutionary Approximation in Non-Local Means Image Filters. SMC 2022: 2762-2769
• 2021
• 
  Lukás Sekanina:
  Neural Architecture Search and Hardware Accelerator Co-Search: A Survey. IEEE Access 9: 151337-151362 (2021)
• 
  Mario Barbareschi, Alberto Bosio, Lukás Sekanina, Claus Braun:
  Editorial: Special issue on Advancing on Approximate Computing: Methodologies, Architectures and Algorithms. Future Gener. Comput. Syst. 124: 54-55 (2021)
• 
  Michal Pinos, Vojtech Mrazek, Lukás Sekanina:
  Evolutionary Neural Architecture Search Supporting Approximate Multipliers. EuroGP 2021: 82-97
• 
  Muhammad Shafique, Andreas Steininger, Lukás Sekanina, Milos Krstic, Goran Stojanovic, Vojtech Mrazek:
  24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021. IEEE 2021, ISBN 978-1-6654-3595-6 [contents]
• 
  Michal Pinos, Vojtech Mrazek, Lukás Sekanina:
  Evolutionary Neural Architecture Search Supporting Approximate Multipliers. CoRR abs/2101.11883 (2021)
• 
  Lukás Sekanina:
  Evolutionary Algorithms in Approximate Computing: A Survey. CoRR abs/2108.07000 (2021)
• 2020
• 
  Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar:
  Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. Appl. Soft Comput. 95: 106466 (2020)
• 
  Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek:
  Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(4): 406-418 (2020)
• 
  Ting Hu, Miguel Nicolau, Lukás Sekanina:
  Special issue on highlights of genetic programming 2019 events. Genet. Program. Evolvable Mach. 21(3): 283-285 (2020)
• 
  Mohammad Saeed Ansari, Vojtech Mrazek, Bruce F. Cockburn, Lukás Sekanina, Zdenek Vasícek, Jie Han:
  Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 317-328 (2020)
• 
  Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek:
  Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. AICAS 2020: 243-247

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