- David L. Landis:
A Self-Test System Architecture for Reconfigurable WSI. ITC 1989: 275-282 - Frank J. Langley, Ronald R. Boatright, Laurence Crosby:
Composite Electro-Optical Testing of Surface-Mount Device Boards-One Manufacturer's Experience. ITC 1989: 686-691 - Kenneth Lanier:
Methods of Test Waveform Synthesis for High-Speed Data Communication Devices. ITC 1989: 222-230 - Massimo Lanzoni, Piero Olivo, Bruno Riccò:
A Testing Technique to Characterize E2PROM's Aging and Endurance. ITC 1989: 391-396 - Tracy Larrabee:
Efficient Generation of Test Patterns Using Boolean Difference. ITC 1989: 795-802 - Jens Leenstra, Lambert Spaanenburg:
On the Design and Test of Asynchronous Macros Embedded in Synchronous Systems. ITC 1989: 838-845 - Gary J. Lesmeister:
The Linear Array Systolic Tester (LAST). ITC 1989: 543-549 - Régis Leveugle, Gabriele Saucier:
Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities. ITC 1989: 355-363 - Marc E. Levitt, Jacob A. Abraham:
The Economics of Scan Design. ITC 1989: 869-874 - Robert F. Lusch, Endre F. Sarkany:
Techniques for Improved Testability in the IBM ES/9370 System. ITC 1989: 290-294 - Miroslaw Malek, Antoine N. Mourad, Mihir Pandya:
Topological Testing. ITC 1989: 103-110 - Wojciech Maly, Samir B. Naik:
Process Monitoring Oriented IC Testing. ITC 1989: 527-532 - W. Malzfeldt, W. Mohr, H.-D. Oberle, K. Kodalle:
Fast Automatic Failbit Analysis for DRAMs. ITC 1989: 431-438 - William R. Mann:
R96MFX Test Strategy. ITC 1989: 611-614 - Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima:
A New Array Architecture for Parallel Testing in VLSI Memories. ITC 1989: 322-326 - Solomon Max:
Fast Accurate and Complete ADC Testing. ITC 1989: 111-117 - Alice McKeon, Antony Wakeling:
Fault Diagnosis in Analogue Circuits Using AI Techniques. ITC 1989: 118-123 - Scott F. Midkiff, Wern-Yan Koe:
Test Effectiveness Metrics and CMOS Faults. ITC 1989: 653-659 - Hyoung B. Min, William A. Rogers:
Search Strategy Switching: An Alternative to Increased Backtracking. ITC 1989: 803-811 - Thomas H. Morrin:
Mixed-Mode Simulation for Time-Domain Fault Analysis. ITC 1989: 231-241 - Norman Nadeau, Sylvie Perreault:
An Analysis of Tungsten Probes' Effect on Yield in a Production Wafer Probe Environment. ITC 1989: 208-215 - Yasuyuki Nozuyama, Akira Nishimura, Jun Iwamura:
Implementation and Evaluation of Microinstruction-Controlled Self Test Using a Masked Microinstruction Scheme. ITC 1989: 624-632 - Sheila O'Keefe:
Reconfigurable Resource Architecture Improves VLSI Tester Utilization. ITC 1989: 597-604 - David K. Oka:
Transmission Line Simulation for Testing ISDN Devices. ITC 1989: 87-93 - Piero Olivo, Maurizio Damiani, Bruno Riccò:
On the Design of Multiple-Input Shift-Registers for Signature Analysis Testing. ITC 1989: 936 - J. Stephen Pabst:
Cost Impacts of Automatic Test Equipment Purchase Decisions. ITC 1989: 605-610 - Eric Paradis, David Stannard:
SASPL: A Test Program Productivity Analysis Tool. ITC 1989: 577-584 - Srinivas Patil, Prithviraj Banerjee:
Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment. ITC 1989: 718-726 - J. Patterson:
Improved System Design Through Proper Nesting of Test Levels. ITC 1989: 533-542 - Michel Crastes de Paulet, Margot Karam, Gabriele Saucier:
Testability Expertise and Test Planning from High-Level Specifications. ITC 1989: 692-699