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@inproceedings{DBLP:conf/ispass/EyermanHH22,
  author       = {Stijn Eyerman and
                  Wim Heirman and
                  Ibrahim Hur},
  title        = {{DRAM} Bandwidth and Latency Stacks: Visualizing {DRAM} Bottlenecks},
  booktitle    = {International {IEEE} Symposium on Performance Analysis of Systems
                  and Software, {ISPASS} 2022, Singapore, May 22-24, 2022},
  pages        = {322--331},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/ISPASS55109.2022.00045},
  doi          = {10.1109/ISPASS55109.2022.00045},
  timestamp    = {Mon, 04 Jul 2022 17:06:18 +0200},
  biburl       = {https://dblp.org/rec/conf/ispass/EyermanHH22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijcta/RadhaSN19,
  author       = {Subramanyam Radha and
                  David Sundararaj Shylu and
                  Perattur Nagabushanam},
  title        = {Power efficient low latency architecture for decoder: Breaking the
                  {ACS} bottleneck},
  journal      = {Int. J. Circuit Theory Appl.},
  volume       = {47},
  number       = {9},
  pages        = {1513--1528},
  year         = {2019},
  url          = {https://doi.org/10.1002/cta.2663},
  doi          = {10.1002/CTA.2663},
  timestamp    = {Mon, 11 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijcta/RadhaSN19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isit/SpeidelPB17,
  author       = {Ulrich Speidel and
                  Sven Puchinger and
                  Martin Bossert},
  title        = {Constraints for coded tunnels across long latency bottlenecks with
                  ARQ-based congestion control},
  booktitle    = {2017 {IEEE} International Symposium on Information Theory, {ISIT}
                  2017, Aachen, Germany, June 25-30, 2017},
  pages        = {271--275},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ISIT.2017.8006532},
  doi          = {10.1109/ISIT.2017.8006532},
  timestamp    = {Wed, 16 Oct 2019 14:14:48 +0200},
  biburl       = {https://dblp.org/rec/conf/isit/SpeidelPB17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@phdthesis{DBLP:phd/basesearch/Wang15l,
  author       = {Qingyang Wang},
  title        = {A study of transient bottlenecks: understanding and reducing latency
                  long-tail problem in n-tier web applications},
  school       = {Georgia Institute of Technology, Atlanta, GA, {USA}},
  year         = {2015},
  url          = {https://hdl.handle.net/1853/54002},
  timestamp    = {Wed, 29 Mar 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/phd/basesearch/Wang15l.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/DasygenisBDCST06,
  author       = {Minas Dasygenis and
                  Erik Brockmeyer and
                  Bart Durinck and
                  Francky Catthoor and
                  Dimitrios Soudris and
                  Adonios Thanailakis},
  title        = {A combined {DMA} and application-specific prefetching approach for
                  tackling the memory latency bottleneck},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {14},
  number       = {3},
  pages        = {279--291},
  year         = {2006},
  url          = {https://doi.org/10.1109/TVLSI.2006.871759},
  doi          = {10.1109/TVLSI.2006.871759},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/DasygenisBDCST06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}