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@article{DBLP:journals/access/MahmoudSLHS24,
author = {Dina G. Mahmoud and
Beatrice Shokry and
Vincent Lenders and
Wei Hu and
Mirjana Stojilovic},
title = {X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don't-Care
Hardware Trojans to Shared Cloud FPGAs},
journal = {{IEEE} Access},
volume = {12},
pages = {8983--9011},
year = {2024},
url = {https://doi.org/10.1109/ACCESS.2024.3353134},
doi = {10.1109/ACCESS.2024.3353134},
timestamp = {Sat, 10 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/MahmoudSLHS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijpp/OttavianoBBVCRBB24,
author = {Alessandro Ottaviano and
Robert Balas and
Giovanni Bambini and
Antonio del Vecchio and
Maicol Ciani and
Davide Rossi and
Luca Benini and
Andrea Bartolini},
title = {ControlPULP: {A} {RISC-V} On-Chip Parallel Power Controller for Many-Core
{HPC} Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal
Emulation},
journal = {Int. J. Parallel Program.},
volume = {52},
number = {1},
pages = {93--123},
year = {2024},
url = {https://doi.org/10.1007/s10766-024-00761-4},
doi = {10.1007/S10766-024-00761-4},
timestamp = {Thu, 04 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijpp/OttavianoBBVCRBB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrtip/HoshinoSRD24,
author = {Yukinobu Hoshino and
Masahiro Shimasaki and
Namal Rathnayake and
Tuan Linh Dang},
title = {Performance verification and latency time evaluation of hardware image
processing module for appearance inspection systems using {FPGA}},
journal = {J. Real Time Image Process.},
volume = {21},
number = {1},
pages = {20},
year = {2024},
url = {https://doi.org/10.1007/s11554-023-01392-7},
doi = {10.1007/S11554-023-01392-7},
timestamp = {Fri, 19 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jrtip/HoshinoSRD24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/MartinsVSBZ24,
author = {Lucas Amilton Martins and
Felipe Viel and
Laio Oriel Seman and
Eduardo Augusto Bezerra and
C{\'{e}}sar Albenes Zeferino},
title = {A real-time SVM-based hardware accelerator for hyperspectral images
classification in {FPGA}},
journal = {Microprocess. Microsystems},
volume = {104},
pages = {104998},
year = {2024},
url = {https://doi.org/10.1016/j.micpro.2023.104998},
doi = {10.1016/J.MICPRO.2023.104998},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/MartinsVSBZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KaurCKA24,
author = {Jasmin Kaur and
Alvaro Cintas Canto and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {Hardware Constructions for Error Detection in {WG-29} Stream Cipher
Benchmarked on {FPGA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {43},
number = {4},
pages = {1307--1311},
year = {2024},
url = {https://doi.org/10.1109/TCAD.2023.3338108},
doi = {10.1109/TCAD.2023.3338108},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KaurCKA24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tim/FalahatiSA24,
author = {Ali Falahati and
Mahdieh Shamirzaee and
Bijan Alizadeh},
title = {An FPGA-Based Hardware Architecture for {P} + {M} Class {PMU} Using
Accuracy-Aware O-Spline Filter Selection and Modulation Detection},
journal = {{IEEE} Trans. Instrum. Meas.},
volume = {73},
pages = {1--8},
year = {2024},
url = {https://doi.org/10.1109/TIM.2024.3351242},
doi = {10.1109/TIM.2024.3351242},
timestamp = {Sat, 10 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tim/FalahatiSA24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AnupreethamIHBKMNBCS24,
author = {Anupreetham Anupreetham and
Mohamed Ibrahim and
Mathew Hall and
Andrew Boutros and
Ajay Kuzhively and
Abinash Mohanty and
Eriko Nurvitadhi and
Vaughn Betz and
Yu Cao and
Jae{-}Sun Seo},
title = {High Throughput FPGA-Based Object Detection via Algorithm-Hardware
Co-Design},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {1:1--1:20},
year = {2024},
url = {https://doi.org/10.1145/3634919},
doi = {10.1145/3634919},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AnupreethamIHBKMNBCS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KalomirosVV24,
author = {John A. Kalomiros and
John V. Vourvoulakis and
Stavros Vologiannidis},
title = {A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm:
An Efficient Implementation for the Stratix {V} and Zynq UltraScale+
{FPGA} Technology},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {5:1--5:25},
year = {2024},
url = {https://doi.org/10.1145/3615869},
doi = {10.1145/3615869},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KalomirosVV24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiuLYC24,
author = {Zhengyan Liu and
Qiang Liu and
Shun Yan and
Ray C. C. Cheung},
title = {An Efficient FPGA-based Depthwise Separable Convolutional Neural Network
Accelerator with Hardware Pruning},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {15:1--15:20},
year = {2024},
url = {https://doi.org/10.1145/3615661},
doi = {10.1145/3615661},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LiuLYC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/YuanVO24,
author = {Yu Yuan and
Kushal Virupakshappa and
Erdal Oruklu},
title = {Accelerating a Meta Learning Model for Ultrasonic Non-Destructive
Testing Applications Using Model Compression and {FPGA} Hardware},
journal = {J. Signal Process. Syst.},
volume = {96},
number = {1},
pages = {15--29},
year = {2024},
url = {https://doi.org/10.1007/s11265-023-01901-8},
doi = {10.1007/S11265-023-01901-8},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/YuanVO24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/MpakosTAMMTGPK24,
author = {Panagiotis Mpakos and
Ioanna Tasou and
Chloe Alverti and
Panagiotis Miliadis and
Pavlos Malakonakis and
Dimitris Theodoropoulos and
Georgios I. Goumas and
Dionisios N. Pnevmatikatos and
Nectarios Koziris},
editor = {Iouliia Skliarova and
Piedad Brox Jim{\'{e}}nez and
M{\'{a}}rio P. V{\'{e}}stias and
Pedro C. Diniz},
title = {Open-Source SpMV Multiplication Hardware Accelerator for FPGA-Based
{HPC} Systems},
booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications
- 20th International Symposium, {ARC} 2024, Aveiro, Portugal, March
20-22, 2024, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {14553},
pages = {19--32},
publisher = {Springer},
year = {2024},
url = {https://doi.org/10.1007/978-3-031-55673-9\_2},
doi = {10.1007/978-3-031-55673-9\_2},
timestamp = {Mon, 25 Mar 2024 20:43:52 +0100},
biburl = {https://dblp.org/rec/conf/arc/MpakosTAMMTGPK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/AhmedB24,
author = {Muhammed Kawser Ahmed and
Christophe Bobda},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {{ISO-TENANT:} Rethinking {FPGA} Power Distribution Network {(PDN):}
{A} Hardware Based Solution for Remote Power Side Channel Attacks
in {FPGA}},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {42},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637591},
doi = {10.1145/3626202.3637591},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/AhmedB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/PougetPC24,
author = {St{\'{e}}phane Pouget and
Louis{-}No{\"{e}}l Pouchet and
Jason Cong},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Automatic Hardware Pragma Insertion in High-Level Synthesis: {A} Non-Linear
Programming Approach},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {184},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637593},
doi = {10.1145/3626202.3637593},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/PougetPC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/RayDQY24a,
author = {Andy Ray and
Benjamin Devlin and
Fu Yong Quah and
Rahul Yesantharao},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Hardcaml: An OCaml Hardware Domain-Specific Language for Efficient
and Robust Design},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {41},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637586},
doi = {10.1145/3626202.3637586},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/RayDQY24a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/XiaoLZ024,
author = {Youwei Xiao and
Zizhang Luo and
Kexing Zhou and
Yun Liang},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Cement: Streamlining {FPGA} Hardware Design with Cycle-Deterministic
eHDL and Synthesis},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {211--222},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637561},
doi = {10.1145/3626202.3637561},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/XiaoLZ024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icissp/RibesMGP24,
author = {Stefano Ribes and
Fabio Malatesta and
Grazia Garzo and
Alessandro Palumbo},
editor = {Gabriele Lenzini and
Paolo Mori and
Steven Furnell},
title = {Machine Learning-Based Classification of Hardware Trojans in FPGAs
Implementing {RISC-V} Cores},
booktitle = {Proceedings of the 10th International Conference on Information Systems
Security and Privacy, {ICISSP} 2024, Rome, Italy, February 26-28,
2024},
pages = {717--724},
publisher = {{SCITEPRESS}},
year = {2024},
url = {https://doi.org/10.5220/0012324200003648},
doi = {10.5220/0012324200003648},
timestamp = {Tue, 02 Apr 2024 14:37:52 +0200},
biburl = {https://dblp.org/rec/conf/icissp/RibesMGP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/MandalR24,
author = {Suraj Mandal and
Debapriya Basu Roy},
title = {KiD: {A} Hardware Design Framework Targeting Unified {NTT} Multiplication
for CRYSTALS-Kyber and CRYSTALS-Dilithium on {FPGA}},
booktitle = {37th International Conference on {VLSI} Design and 23rd International
Conference on Embedded Systems, {VLSID} 2024, Kolkata, India, January
6-10, 2024},
pages = {455--460},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/VLSID60093.2024.00082},
doi = {10.1109/VLSID60093.2024.00082},
timestamp = {Mon, 08 Apr 2024 20:48:39 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/MandalR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/sp/Snider23,
author = {Ross Snider},
title = {Advanced Digital System Design using SoC FPGAs - An Integrated Hardware/Software
Approach},
publisher = {Springer},
year = {2023},
url = {https://doi.org/10.1007/978-3-031-15416-4},
doi = {10.1007/978-3-031-15416-4},
isbn = {978-3-031-15415-7},
timestamp = {Mon, 16 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/books/sp/Snider23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/LiG23b,
author = {Tengfei Li and
Shenshen Gu},
title = {{FPGA} Hardware Implementation of Efficient Long Short-Term Memory
Network Based on Construction Vector Method},
journal = {{IEEE} Access},
volume = {11},
pages = {122357--122367},
year = {2023},
url = {https://doi.org/10.1109/ACCESS.2023.3329048},
doi = {10.1109/ACCESS.2023.3329048},
timestamp = {Tue, 28 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/LiG23b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/MadsenP23,
author = {Anne K. Madsen and
Darshika G. Perera},
title = {Toward Composing Efficient FPGA-Based Hardware Accelerators for Physics-Based
Model Predictive Control Smart Sensor for {HEV} Battery Cell Management},
journal = {{IEEE} Access},
volume = {11},
pages = {106141--106171},
year = {2023},
url = {https://doi.org/10.1109/ACCESS.2023.3319288},
doi = {10.1109/ACCESS.2023.3319288},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/MadsenP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/MatteoGS23,
author = {Stefano Di Matteo and
Matteo Lo Gerfo and
Sergio Saponara},
title = {{VLSI} Design and {FPGA} Implementation of an {NTT} Hardware Accelerator
for Homomorphic SEAL-Embedded Library},
journal = {{IEEE} Access},
volume = {11},
pages = {72498--72508},
year = {2023},
url = {https://doi.org/10.1109/ACCESS.2023.3295245},
doi = {10.1109/ACCESS.2023.3295245},
timestamp = {Sat, 21 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/MatteoGS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/TsaiHC23,
author = {Tsung{-}Han Tsai and
Yuan{-}Chen Ho and
Po{-}Ting Chi},
title = {Hardware Architecture Design for Hand Gesture Recognition System on
{FPGA}},
journal = {{IEEE} Access},
volume = {11},
pages = {51767--51776},
year = {2023},
url = {https://doi.org/10.1109/ACCESS.2023.3277857},
doi = {10.1109/ACCESS.2023.3277857},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/TsaiHC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/ZhaoDDZZQ23,
author = {Fuhai Zhao and
Jiang Du and
Yunkai Deng and
Jialin Zheng and
Yangbin Zeng and
Chunhui Qu},
title = {An Adaptive Word-Length Selection Method to Optimize Hardware Resources
for FPGA-Based Real-Time Simulation of Power Converters},
journal = {{IEEE} Access},
volume = {11},
pages = {122980--122990},
year = {2023},
url = {https://doi.org/10.1109/ACCESS.2023.3328919},
doi = {10.1109/ACCESS.2023.3328919},
timestamp = {Tue, 28 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/ZhaoDDZZQ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cea/GuptaK23,
author = {Namit Gupta and
Adesh Kumar},
title = {Study on the wireless sensor networks routing for Low-Power {FPGA}
hardware in field applications},
journal = {Comput. Electron. Agric.},
volume = {212},
pages = {108145},
year = {2023},
url = {https://doi.org/10.1016/j.compag.2023.108145},
doi = {10.1016/J.COMPAG.2023.108145},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cea/GuptaK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computation/SiderisD23,
author = {Argyrios Sideris and
Minas Dasygenis},
title = {Enhancing the Hardware Pipelining Optimization Technique of the {SHA-3}
via {FPGA}},
journal = {Comput.},
volume = {11},
number = {8},
pages = {152},
year = {2023},
url = {https://doi.org/10.3390/computation11080152},
doi = {10.3390/COMPUTATION11080152},
timestamp = {Fri, 18 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computation/SiderisD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/LaraNinoDM23,
author = {Carlos Andres Lara{-}Nino and
Arturo Diaz{-}Perez and
Miguel Morales{-}Sandoval},
title = {Hardware Acceleration of {SIKE} on Low-End FPGAs},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {15},
number = {2},
pages = {73--76},
year = {2023},
url = {https://doi.org/10.1109/LES.2022.3175016},
doi = {10.1109/LES.2022.3175016},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/LaraNinoDM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ewc/AsghariH0R023,
author = {Mohsen Asghari and
Amir Hosein Hadian{-}Rasanan and
Saeid Gorgin and
Dara Rahmati and
K. Parand},
title = {FPGA-orthopoly: a hardware implementation of orthogonal polynomials},
journal = {Eng. Comput.},
volume = {39},
number = {3},
pages = {2257--2276},
year = {2023},
url = {https://doi.org/10.1007/s00366-022-01612-x},
doi = {10.1007/S00366-022-01612-X},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ewc/AsghariH0R023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/fgcs/SotoHF23,
author = {Javier E. Soto and
Cecilia Hern{\'{a}}ndez and
Miguel E. Figueroa},
title = {{JACC-FPGA:} {A} hardware accelerator for Jaccard similarity estimation
using FPGAs in the cloud},
journal = {Future Gener. Comput. Syst.},
volume = {138},
pages = {26--42},
year = {2023},
url = {https://doi.org/10.1016/j.future.2022.08.005},
doi = {10.1016/J.FUTURE.2022.08.005},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/fgcs/SotoHF23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/icl/AlmeidaPDOC23,
author = {Lu{\'{\i}}s Filipe Almeida and
Samuel Santos Pereira and
Jos{\'{e}} D. Domingues and
Arnaldo S. R. Oliveira and
Nuno Borges Carvalho},
title = {Moving {NFV} Toward the Antenna Through FPGA-Based Hardware Reconfiguration},
journal = {{IEEE} Commun. Lett.},
volume = {27},
number = {1},
pages = {342--346},
year = {2023},
url = {https://doi.org/10.1109/LCOMM.2022.3216506},
doi = {10.1109/LCOMM.2022.3216506},
timestamp = {Thu, 03 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/icl/AlmeidaPDOC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/TiempoJ23a,
author = {Ann Jelyn Tiempo and
Yong{-}Jin Jeong},
title = {Implementing Region-Based Segmentation for Hardware Trojan Detection
in FPGAs Cell-Level Netlist},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {106},
number = {11},
pages = {1926--1929},
year = {2023},
url = {https://doi.org/10.1587/transinf.2023edl8036},
doi = {10.1587/TRANSINF.2023EDL8036},
timestamp = {Wed, 29 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicetd/TiempoJ23a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijcat/VaidyanathanSCMKMSS23,
author = {Sundarapandian Vaidyanathan and
Aceng Sambas and
Daniel Clemente{-}L{\'{o}}pez and
Jes{\'{u}}s M. Mu{\~{n}}oz{-}Pacheco and
Alain Soup Tewa Kammogne and
Vannick Fopa Mawamba and
Martin Siewe Siewe and
Samy Abdelwahab Safaan},
title = {Electronic circuit design and FPGA-based hardware implementation of
a new multistable 4-D hyperchaotic four-leaf system},
journal = {Int. J. Comput. Appl. Technol.},
volume = {72},
number = {1},
pages = {13--28},
year = {2023},
url = {https://doi.org/10.1504/IJCAT.2023.132548},
doi = {10.1504/IJCAT.2023.132548},
timestamp = {Mon, 27 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijcat/VaidyanathanSCMKMSS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijon/RanZDCZ23,
author = {Shaolin Ran and
Beizhen Zhao and
Xing Dai and
Cheng Cheng and
Yong Zhang},
title = {Software-hardware co-design for accelerating large-scale graph convolutional
network inference on {FPGA}},
journal = {Neurocomputing},
volume = {532},
pages = {129--140},
year = {2023},
url = {https://doi.org/10.1016/j.neucom.2023.02.032},
doi = {10.1016/J.NEUCOM.2023.02.032},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijon/RanZDCZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/information/SiderisSD23,
author = {Argyrios Sideris and
Theodora Sanida and
Minas Dasygenis},
title = {A Novel Hardware Architecture for Enhancing the Keccak Hash Function
in {FPGA} Devices},
journal = {Inf.},
volume = {14},
number = {9},
pages = {475},
year = {2023},
url = {https://doi.org/10.3390/info14090475},
doi = {10.3390/INFO14090475},
timestamp = {Wed, 24 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/information/SiderisSD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jaihc/GafsiHMM23,
author = {Mohamed Gafsi and
Mohamed Ali Hajjaji and
Jihene Malek and
Abdellatif Mtibaa},
title = {{FPGA} hardware acceleration of an improved chaos-based cryptosystem
for real-time image encryption and decryption},
journal = {J. Ambient Intell. Humaniz. Comput.},
volume = {14},
number = {6},
pages = {7001--7022},
year = {2023},
url = {https://doi.org/10.1007/s12652-021-03555-5},
doi = {10.1007/S12652-021-03555-5},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jaihc/GafsiHMM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/MarchisioTRS23,
author = {Alberto Marchisio and
Federico Teodonio and
Antonello Rizzi and
Muhammad Shafique},
title = {ISMatch: {A} real-time hardware accelerator for inexact string matching
of {DNA} sequences on {FPGA}},
journal = {Microprocess. Microsystems},
volume = {97},
pages = {104763},
year = {2023},
url = {https://doi.org/10.1016/j.micpro.2023.104763},
doi = {10.1016/J.MICPRO.2023.104763},
timestamp = {Fri, 08 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/MarchisioTRS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mta/ZhangSZ23,
author = {Jun Zhang and
Wenchen Shi and
Hao Zhang},
title = {Study on versatile video coding multiple transform selection of hardware
architecture based on {FPGA}},
journal = {Multim. Tools Appl.},
volume = {82},
number = {10},
pages = {14929--14944},
year = {2023},
url = {https://doi.org/10.1007/s11042-022-14069-3},
doi = {10.1007/S11042-022-14069-3},
timestamp = {Tue, 18 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mta/ZhangSZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sap/RenugadeviJVBT23,
author = {N. Renugadevi and
Stheya Julakanti and
Sai Charan Vemula and
Somya Bhatnagar and
Shirisha Thangallapally},
title = {Low area and high throughput implementation of advanced encryption
standard hardware accelerator on {FPGA} using Mux-Demux pair},
journal = {Secur. Priv.},
volume = {6},
number = {4},
year = {2023},
url = {https://doi.org/10.1002/spy2.292},
doi = {10.1002/SPY2.292},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sap/RenugadeviJVBT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/BashaKCLSJKD23,
author = {Mudasar Basha and
Munuswamy Siva Kumar and
Mangali Chinna Chinnaiah and
Siew{-}Kei Lam and
Thambipillai Srikanthan and
Narambhatla Janardhan and
Dodde Hari Krishna and
Sanjay Dubey},
title = {A Versatile Approach to Polygonal Object Avoidance in Indoor Environments
with Hardware Schemes Using an FPGA-Based Multi-Robot},
journal = {Sensors},
volume = {23},
number = {23},
pages = {9480},
year = {2023},
url = {https://doi.org/10.3390/s23239480},
doi = {10.3390/S23239480},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sensors/BashaKCLSJKD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/SuSAS23,
author = {Yuanxin Su and
Kah Phooi Seng and
Li{-}Minn Ang and
Jeremy Smith},
title = {Binary Neural Networks in FPGAs: Architectures, Tool Flows and Hardware
Comparisons},
journal = {Sensors},
volume = {23},
number = {22},
pages = {9254},
year = {2023},
url = {https://doi.org/10.3390/s23229254},
doi = {10.3390/S23229254},
timestamp = {Fri, 09 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sensors/SuSAS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/SuiLZZYZT23,
author = {Xuefu Sui and
Qunbo Lv and
Liangjie Zhi and
Baoyu Zhu and
Yuanbo Yang and
Yu Zhang and
Zheng Tan},
title = {A Hardware-Friendly High-Precision {CNN} Pruning Method and Its {FPGA}
Implementation},
journal = {Sensors},
volume = {23},
number = {2},
pages = {824},
year = {2023},
url = {https://doi.org/10.3390/s23020824},
doi = {10.3390/S23020824},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sensors/SuiLZZYZT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sncs/KokkiligaddaNPSP23,
author = {Venkata Siva Kumar Kokkiligadda and
Vijitha Naikoti and
Gaurao Sunil Patkotwar and
Samrat L. Sabat and
Rangababu Peesapati},
title = {FPGA-Based Hardware Accelerator for Matrix Inversion},
journal = {{SN} Comput. Sci.},
volume = {4},
number = {2},
pages = {147},
year = {2023},
url = {https://doi.org/10.1007/s42979-022-01542-x},
doi = {10.1007/S42979-022-01542-X},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sncs/KokkiligaddaNPSP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/DangMG23,
author = {Viet Ba Dang and
Kamyar Mohajerani and
Kris Gaj},
title = {High-Speed Hardware Architectures and {FPGA} Benchmarking of CRYSTALS-Kyber,
NTRU, and Saber},
journal = {{IEEE} Trans. Computers},
volume = {72},
number = {2},
pages = {306--320},
year = {2023},
url = {https://doi.org/10.1109/TC.2022.3222954},
doi = {10.1109/TC.2022.3222954},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/DangMG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PaulYSKT23,
author = {Bikram Paul and
Tarun Kumar Yadav and
Balbir Singh and
Srinivasan Krishnaswamy and
Gaurav Trivedi},
title = {A Resource Efficient Software-Hardware Co-Design of Lattice-Based
Homomorphic Encryption Scheme on the {FPGA}},
journal = {{IEEE} Trans. Computers},
volume = {72},
number = {5},
pages = {1247--1260},
year = {2023},
url = {https://doi.org/10.1109/TC.2022.3198628},
doi = {10.1109/TC.2022.3198628},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PaulYSKT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/SongHTW23,
author = {Yifeng Song and
Xiao Hu and
Jing Tian and
Zhongfeng Wang},
title = {A High-Speed FPGA-Based Hardware Implementation for Leighton-Micali
Signature},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {70},
number = {1},
pages = {241--252},
year = {2023},
url = {https://doi.org/10.1109/TCSI.2022.3210016},
doi = {10.1109/TCSI.2022.3210016},
timestamp = {Tue, 05 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcasI/SongHTW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tie/WangXCL23,
author = {Yu Wang and
Wujun Xie and
Haochang Chen and
David Day{-}Uei Li},
title = {Low-Hardware Consumption, Resolution-Configurable Gray Code Oscillator
Time-to-Digital Converters Implemented in 16 nm, 20 nm, and 28 nm
FPGAs},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {70},
number = {4},
pages = {4256--4266},
year = {2023},
url = {https://doi.org/10.1109/TIE.2022.3174299},
doi = {10.1109/TIE.2022.3174299},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tie/WangXCL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tjs/ZaganG23,
author = {Ionel Zagan and
Vasile Gheorghita Gaitan},
title = {{FPGA} implementation of hardware accelerated {RTOS} based on real-time
event handling},
journal = {J. Supercomput.},
volume = {79},
number = {11},
pages = {12441--12471},
year = {2023},
url = {https://doi.org/10.1007/s11227-023-05151-0},
doi = {10.1007/S11227-023-05151-0},
timestamp = {Fri, 16 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tjs/ZaganG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tjs/ZaganG23a,
author = {Ionel Zagan and
Vasile Gheorghita Gaitan},
title = {Correction to: {FPGA} implementation of hardware accelerated {RTOS}
based on real-time event handling},
journal = {J. Supercomput.},
volume = {79},
number = {13},
pages = {15213},
year = {2023},
url = {https://doi.org/10.1007/s11227-023-05229-9},
doi = {10.1007/S11227-023-05229-9},
timestamp = {Fri, 30 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tjs/ZaganG23a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HeBXA23,
author = {Pengzhou He and
Tianyou Bao and
Jiafeng Xie and
Moeness G. Amin},
title = {{FPGA} Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based
Post-quantum Cryptography},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {45:1--45:23},
year = {2023},
url = {https://doi.org/10.1145/3569457},
doi = {10.1145/3569457},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HeBXA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SuhMNKCS23,
author = {Han{-}Sok Suh and
Jian Meng and
Ty Nguyen and
Vijay Kumar and
Yu Cao and
Jae{-}Sun Seo},
title = {Algorithm-hardware Co-optimization for Energy-efficient Drone Detection
on Resource-constrained {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {33:1--33:25},
year = {2023},
url = {https://doi.org/10.1145/3583074},
doi = {10.1145/3583074},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SuhMNKCS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LingLCQLZW23,
author = {Ming Ling and
Qingde Lin and
Ruiqi Chen and
Haimeng Qi and
Mengru Lin and
Yanxiang Zhu and
Jiansheng Wu},
title = {Vina-FPGA: {A} Hardware-Accelerated Molecular Docking Tool With Fixed-Point
Quantization and Low-Level Parallelism},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {484--497},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3217275},
doi = {10.1109/TVLSI.2022.3217275},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LingLCQLZW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aisd/PandeySRAKTMS23,
author = {Sandeep Kumar Pandey and
Geetika Srivastava and
Mamun Bin Ibne Reaz and
Sawal Hamid Md. Ali and
Edi Kurniawan and
Rabindra Gandhi Thangarajoo and
Ganga Ram Mishra and
Sacchidanand Shukla},
editor = {Namrata Rastogi Nagpal and
Meenakshi Srivastava and
Sanju Tiwari and
Fernando Ortiz{-}Rodr{\'{\i}}guez},
title = {FPGA-based Hardware Classifier for Diabetic Sensorimotor Polyneuropathy
Severity Assessment},
booktitle = {Proceedings of the First International Workshop on Artificial Intelligence:
Empowering Sustainable Development co-located with First International
Conference on Artificial Intelligence: Towards Sustainable Intelligence
(AI4S-2023), Pune, India, September 4-5, 2023},
series = {{CEUR} Workshop Proceedings},
volume = {3619},
pages = {33--41},
publisher = {CEUR-WS.org},
year = {2023},
url = {https://ceur-ws.org/Vol-3619/AISD\_Paper\_4.pdf},
timestamp = {Mon, 29 Jan 2024 17:09:11 +0100},
biburl = {https://dblp.org/rec/conf/aisd/PandeySRAKTMS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/applepies/JamiliMCBMAO23,
author = {Saeid Jamili and
Antonio Mastrandrea and
Abdallah Cheikh and
Marcello Barbirotta and
Francesco Menichelli and
Marco Angioli and
Mauro Olivieri},
editor = {Francesco Bellotti and
Miltos D. Grammatikakis and
Ali Mansour and
Massimo Ruo Roch and
Ralf Seepold and
Agusti Solanas and
Riccardo Berta},
title = {A Universal Hardware Emulator for Verification IPs on {FPGA:} {A}
Novel and Low-Cost Approach},
booktitle = {Applications in Electronics Pervading Industry, Environment and Society
- {APPLEPIES} 2023, Genoa, Italy, 28-29 September 2023},
series = {Lecture Notes in Electrical Engineering},
volume = {1110},
pages = {36--41},
publisher = {Springer},
year = {2023},
url = {https://doi.org/10.1007/978-3-031-48121-5\_5},
doi = {10.1007/978-3-031-48121-5\_5},
timestamp = {Thu, 18 Jan 2024 16:23:38 +0100},
biburl = {https://dblp.org/rec/conf/applepies/JamiliMCBMAO23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/ShiZZY23,
author = {Rui Shi and
Yunfan Zuo and
Kelong Zhang and
Hao Yan},
title = {Hardware Acceleration Linear Matrix Solvor Based on {FPGA}},
booktitle = {15th {IEEE} International Conference on ASIC, {ASICON} 2023, Nanjing,
China, October 24-27, 2023},
pages = {1--4},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ASICON58565.2023.10396603},
doi = {10.1109/ASICON58565.2023.10396603},
timestamp = {Fri, 16 Feb 2024 14:02:58 +0100},
biburl = {https://dblp.org/rec/conf/asicon/ShiZZY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/ChenHXSXGZ23,
author = {Xin Chen and
Liangzhou Huo and
Yudong Xie and
Zhihao Shen and
Zhiqiang Xiang and
Changhao Gao and
Ying Zhang},
title = {FPGA-Based Cross-Hardware {MBU} Emulation Platform for Layout-Level
Digital {VLSI}},
booktitle = {32nd {IEEE} Asian Test Symposium, {ATS} 2023, Beijing, China, October
14-17, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ATS59501.2023.10317974},
doi = {10.1109/ATS59501.2023.10317974},
timestamp = {Fri, 08 Dec 2023 20:28:22 +0100},
biburl = {https://dblp.org/rec/conf/ats/ChenHXSXGZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cbms/StanchieriMFPFGP23,
author = {Guido Di Patrizio Stanchieri and
Andrea De Marcellis and
Marco Faccio and
Elia Palange and
Mario Di Ferdinando and
Stefano Di Gennaro and
Pierdomenico Pepe},
editor = {Jo{\~{a}}o Rafael Almeida and
Myra Spiliopoulou and
Jos{\'{e}} Alberto Ben{\'{\i}}tez{-}Andrades and
Giuseppe Placidi and
Alejandro Rodr{\'{\i}}guez Gonz{\'{a}}lez and
Rosa Sicilia and
Bridget Kane},
title = {On the FPGA-Based Hardware Implementation of Digital Glucose Regulators
for Type 2 Diabetic Patients},
booktitle = {36th {IEEE} International Symposium on Computer-Based Medical Systems,
{CBMS} 2023, L'Aquila, Italy, June 22-24, 2023},
pages = {802--805},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/CBMS58004.2023.00323},
doi = {10.1109/CBMS58004.2023.00323},
timestamp = {Mon, 24 Jul 2023 15:56:16 +0200},
biburl = {https://dblp.org/rec/conf/cbms/StanchieriMFPFGP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cipae/LinCW23,
author = {Yuxuan Lin and
Huangxu Chen and
Zhaohui Wu},
title = {A hardware architecture design for interference rejection of ultrasound
signals based on {FPGA}},
booktitle = {International Conference on Computers, Information Processing and
Advanced Education, {CIPAE} 2023, Ottawa, ON, Canada, August 26-28,
2023},
pages = {492--496},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/CIPAE60493.2023.00099},
doi = {10.1109/CIPAE60493.2023.00099},
timestamp = {Tue, 30 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cipae/LinCW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cscwd/LiuGTZS23,
author = {Jihong Liu and
Neng Gao and
Chenyang Tu and
Yifei Zhang and
Yongjuan Sun},
editor = {Weiming Shen and
Jean{-}Paul A. Barth{\`{e}}s and
Junzhou Luo and
Adriana S. Vivacqua and
Daniel Schneider and
Cheng Xie and
Jinghui Zhang and
Haibin Zhu and
Kunkun Peng and
Cl{\'{a}}udia Lage Rebello da Motta},
title = {A Pure Hardware Design and Implementation on {FPGA} of WireGuard-based
{VPN} Gateway},
booktitle = {26th International Conference on Computer Supported Cooperative Work
in Design, {CSCWD} 2023, Rio de Janeiro, Brazil, May 24-26, 2023},
pages = {1220--1225},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/CSCWD57460.2023.10152666},
doi = {10.1109/CSCWD57460.2023.10152666},
timestamp = {Tue, 06 Feb 2024 14:19:46 +0100},
biburl = {https://dblp.org/rec/conf/cscwd/LiuGTZS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cvpr/PlochaetG23,
author = {Jef Plochaet and
Toon Goedem{\'{e}}},
title = {Hardware-Aware Pruning for {FPGA} Deep Learning Accelerators},
booktitle = {{IEEE/CVF} Conference on Computer Vision and Pattern Recognition,
{CVPR} 2023 - Workshops, Vancouver, BC, Canada, June 17-24, 2023},
pages = {4482--4490},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/CVPRW59228.2023.00471},
doi = {10.1109/CVPRW59228.2023.00471},
timestamp = {Wed, 23 Aug 2023 16:23:26 +0200},
biburl = {https://dblp.org/rec/conf/cvpr/PlochaetG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/CuiLCZZYLC23,
author = {Hongwei Cui and
Shuhao Liang and
Yujie Cui and
Weiqi Zhang and
Honglan Zhan and
Chun Yang and
Xianhua Liu and
Xu Cheng},
title = {A Hardware-Software Cooperative Interval-Replaying for FPGA-based
Architecture Evaluation},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10137049},
doi = {10.23919/DATE56975.2023.10137049},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/CuiLCZZYLC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eit/JohnsonZS23,
author = {Hans Johnson and
Silvia Zorzetti and
Jafar Saniie},
title = {Exploration of Optimizing FPGA-based Qubit Controller for Experiments
on Superconducting Quantum Computing Hardware},
booktitle = {{IEEE} International Conference on Electro Information Technology,
eIT 2023, Romeoville, IL, USA, May 18-20, 2023},
pages = {406--411},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/eIT57321.2023.10187252},
doi = {10.1109/EIT57321.2023.10187252},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/eit/JohnsonZS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ewdts/MelikyanGAK23,
author = {Vazgen Melikyan and
Mushegh T. Grigoryan and
Ashot Avetisyan and
Tigran Khachatryan},
title = {Accelerating {CNN} Models for Visual Odometry: Design and {FPGA} Implementation
for Efficient Hardware Acceleration},
booktitle = {{IEEE} East-West Design {\&} Test Symposium, {EWDTS} 2023, Batumi,
Georgia, September 22-25, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/EWDTS59469.2023.10297049},
doi = {10.1109/EWDTS59469.2023.10297049},
timestamp = {Thu, 16 Nov 2023 09:03:44 +0100},
biburl = {https://dblp.org/rec/conf/ewdts/MelikyanGAK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/0007ZGDWS23,
author = {Jiajun Wu and
Jiajun Zhou and
Yizhao Gao and
Yuhao Ding and
Ngai Wong and
Hayden Kwok{-}Hay So},
title = {{MSD:} Mixing Signed Digit Representations for Hardware-efficient
{DNN} Acceleration on {FPGA} with Heterogeneous Resources},
booktitle = {31st {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2023, Marina Del Rey, CA, USA, May 8-11,
2023},
pages = {94--104},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/FCCM57271.2023.00019},
doi = {10.1109/FCCM57271.2023.00019},
timestamp = {Tue, 18 Jul 2023 14:07:31 +0200},
biburl = {https://dblp.org/rec/conf/fccm/0007ZGDWS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/AizazKT23,
author = {Zainab Aizaz and
Kavita Khare and
Aizaz Tirmizi},
title = {{FASBM:} FPGA-specific Approximate Sum-based Booth multipliers for
energy efficient Hardware Acceleration of Image Processing and Machine
Learning Applications},
booktitle = {31st {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2023, Marina Del Rey, CA, USA, May 8-11,
2023},
pages = {210},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/FCCM57271.2023.00038},
doi = {10.1109/FCCM57271.2023.00038},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/AizazKT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/WangLZYW23,
author = {Yuanfang Wang and
Yu Li and
Haoyang Zhang and
Jun Yu and
Kun Wang},
title = {Moth: {A} Hardware Accelerator for Neural Radiance Field Inference
on {FPGA}},
booktitle = {31st {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2023, Marina Del Rey, CA, USA, May 8-11,
2023},
pages = {227},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/FCCM57271.2023.00055},
doi = {10.1109/FCCM57271.2023.00055},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fccm/WangLZYW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ficloud/AllamASE23,
author = {Oussama El Allam and
Abdelhakim Alali and
Mohamed Sadik and
Hasna Elmaaradi},
editor = {Irfan Awan and
Muhammad Younas and
Markus Aleksy},
title = {Open-source Hardware {FPGA} Platforms for IoT: Paradigms, opportunities
and open issues},
booktitle = {10th International Conference on Future Internet of Things and Cloud,
FiCloud 2023, Marrakesh, Morocco, August 14-16, 2023},
pages = {292--297},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/FiCloud58648.2023.00050},
doi = {10.1109/FICLOUD58648.2023.00050},
timestamp = {Thu, 04 Apr 2024 15:39:38 +0200},
biburl = {https://dblp.org/rec/conf/ficloud/AllamASE23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fie/LiLJLHYL23,
author = {Ying Li and
Jingzhuo Liang and
Gui Shi Jie and
Yangdong Liu and
Wei Huang and
Yue Yan and
Xianglong Liu},
title = {An innovative experimental teaching method of hardware-software co-design-Taking
a hardware accelerator of neural network using {FPGA}},
booktitle = {{IEEE} Frontiers in Education Conference, {FIE} 2023, College Station,
TX, USA, October 18-21, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/FIE58773.2023.10343303},
doi = {10.1109/FIE58773.2023.10343303},
timestamp = {Fri, 26 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fie/LiLJLHYL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HowABLSG23,
author = {Dana How and
Tim Ansell and
Vaughn Betz and
Chris Lavin and
Ted Speers and
Pierre{-}Emmanuel Gaillardon},
editor = {Paolo Ienne and
Zhiru Zhang},
title = {Open-source and FPGAs: Hardware, Software, Both or None?},
booktitle = {Proceedings of the 2023 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2023, Monterey, CA, USA, February
12-14, 2023},
pages = {149},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3543622.3579026},
doi = {10.1145/3543622.3579026},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/HowABLSG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ShadabZGL23,
author = {Rakin Muhammad Shadab and
Yu Zou and
Sanjay Gandham and
Mingjie Lin},
editor = {Paolo Ienne and
Zhiru Zhang},
title = {{OMT:} {A} Demand-Adaptive, Hardware-Targeted Bonsai Merkle Tree Framework
for Embedded Heterogeneous Memory Platform},
booktitle = {Proceedings of the 2023 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2023, Monterey, CA, USA, February
12-14, 2023},
pages = {47},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3543622.3573165},
doi = {10.1145/3543622.3573165},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ShadabZGL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/Jentzsch23,
author = {Felix Jentzsch},
editor = {Nele Mentens and
Leonel Sousa and
Pedro Trancoso and
Nikela Papadopoulou and
Ioannis Sourdis},
title = {Hardware-Aware AutoML for Exploration of Custom {FPGA} Accelerators
for RadioML},
booktitle = {33rd International Conference on Field-Programmable Logic and Applications,
{FPL} 2023, Gothenburg, Sweden, September 4-8, 2023},
pages = {359--360},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/FPL60245.2023.00066},
doi = {10.1109/FPL60245.2023.00066},
timestamp = {Fri, 17 Nov 2023 08:57:25 +0100},
biburl = {https://dblp.org/rec/conf/fpl/Jentzsch23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ZhaoHH23,
author = {Baoze Zhao and
Wenjin Huang and
Yihua Huang},
editor = {Nele Mentens and
Leonel Sousa and
Pedro Trancoso and
Nikela Papadopoulou and
Ioannis Sourdis},
title = {A Novel Hardware Accelerator of NeRF Based on Xilinx UltraScale and
UltraScale+ {FPGA}},
booktitle = {33rd International Conference on Field-Programmable Logic and Applications,
{FPL} 2023, Gothenburg, Sweden, September 4-8, 2023},
pages = {197--203},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/FPL60245.2023.00035},
doi = {10.1109/FPL60245.2023.00035},
timestamp = {Mon, 20 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/ZhaoHH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/ZhaoHLH23,
author = {Baoze Zhao and
Wenjin Huang and
Tianrui Li and
Yihua Huang},
title = {{BSTMSM:} {A} High-Performance FPGA-based Multi-Scalar Multiplication
Hardware Accelerator},
booktitle = {International Conference on Field Programmable Technology, {ICFPT}
2023, Yokohama, Japan, December 12-14, 2023},
pages = {35--43},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICFPT59805.2023.00009},
doi = {10.1109/ICFPT59805.2023.00009},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/ZhaoHLH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iait/SahaGPR23,
author = {Piyali Saha and
Sudip Ghosh and
Debajyoti Pal and
Hafizur Rahaman},
title = {Hardware Performance Analysis of N-bit {CLA} on {FPGA} and Programmable
SoC},
booktitle = {Proceedings of the 13th International Conference on Advances in Information
Technology, {IAIT} 2023, Bangkok, Thailand, December 6-9, 2023},
pages = {1:1--1:7},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3628454.3628455},
doi = {10.1145/3628454.3628455},
timestamp = {Wed, 13 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iait/SahaGPR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic3i/ShrivastavaK23,
author = {Shishir Shrivastava and
Amanpreet Kaur},
title = {Comparative Energy {\&} Hardware Analysis on Implementation of
8-Bit {ALU} Using Different FPGAs Families},
booktitle = {6th International Conference on Contemporary Computing and Informatics,
{IC3I} 2023, Gautam Buddha Nagar, India, September 14-16, 2023},
pages = {193--197},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/IC3I59117.2023.10397728},
doi = {10.1109/IC3I59117.2023.10397728},
timestamp = {Tue, 13 Feb 2024 08:24:21 +0100},
biburl = {https://dblp.org/rec/conf/ic3i/ShrivastavaK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic3i/ShrivastavaK23a,
author = {Shishir Shrivastava and
Amanpreet Kaur},
title = {Comparative Energy {\&} Hardware Analysis on Implementation of
Full Subtractor Using Different FPGAs Families},
booktitle = {6th International Conference on Contemporary Computing and Informatics,
{IC3I} 2023, Gautam Buddha Nagar, India, September 14-16, 2023},
pages = {198--202},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/IC3I59117.2023.10397853},
doi = {10.1109/IC3I59117.2023.10397853},
timestamp = {Tue, 13 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic3i/ShrivastavaK23a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icc/BaiZCZCZCYW23,
author = {Yueyin Bai and
Hao Zhou and
Ruiqi Chen and
Kuangjie Zou and
Jialin Cao and
Haoyang Zhang and
Jianli Chen and
Jun Yu and
Kun Wang},
title = {g-BERT: Enabling Green {BERT} Deployment on {FPGA} via Hardware-Aware
Hybrid Pruning},
booktitle = {{IEEE} International Conference on Communications, {ICC} 2023, Rome,
Italy, May 28 - June 1, 2023},
pages = {1706--1711},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICC45041.2023.10278567},
doi = {10.1109/ICC45041.2023.10278567},
timestamp = {Tue, 02 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icc/BaiZCZCZCYW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PuSHYSZ23,
author = {Ruiyao Pu and
Yiwei Sun and
Pei{-}Hsin Ho and
Fan Yang and
Li Shang and
Xuan Zeng},
title = {Sphinx: {A} Hybrid Boolean Processor-FPGA Hardware Emulation System},
booktitle = {{IEEE/ACM} International Conference on Computer Aided Design, {ICCAD}
2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023},
pages = {1--9},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICCAD57390.2023.10323694},
doi = {10.1109/ICCAD57390.2023.10323694},
timestamp = {Wed, 03 Jan 2024 08:34:26 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PuSHYSZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccel/CruzGMAJSD23,
author = {Thiago S. Cruz and
Jo{\~{a}}o P. M. Gomes and
Lucas F. Martins and
Danyllo W. Albuquerque and
Gutemberg G. dos Santos J{\'{u}}nior and
Danilo F. S. Santos and
Jemerson Dam{\'{a}}sio},
title = {Extensible Hardware Inference Accelerator for {FPGA} using Models
from TensorFlow Lite},
booktitle = {{IEEE} International Conference on Consumer Electronics, {ICCE} 2023,
Las Vegas, NV, USA, January 6-8, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICCE56470.2023.10043475},
doi = {10.1109/ICCE56470.2023.10043475},
timestamp = {Tue, 21 Feb 2023 18:13:47 +0100},
biburl = {https://dblp.org/rec/conf/iccel/CruzGMAJSD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccsa/PhamQuoc23,
author = {Cuong Pham{-}Quoc},
editor = {Osvaldo Gervasi and
Beniamino Murgante and
Ana Maria A. C. Rocha and
Chiara Garau and
Francesco Scorza and
Yeliz Karaca and
Carmelo M. Torre},
title = {FPGA-Based Hardware/Software Codesign for Video Encoder on IoT Edge
Platforms},
booktitle = {Computational Science and Its Applications - {ICCSA} 2023 Workshops
- Athens, Greece, July 3-6, 2023, Proceedings, Part {V}},
series = {Lecture Notes in Computer Science},
volume = {14108},
pages = {82--96},
publisher = {Springer},
year = {2023},
url = {https://doi.org/10.1007/978-3-031-37117-2\_7},
doi = {10.1007/978-3-031-37117-2\_7},
timestamp = {Fri, 21 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccsa/PhamQuoc23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/MurtazaPMQB23,
author = {Ali Murtaza and
Muhammad Adeel Pasha and
Shahid Masud and
M. Yasir Qadri and
Abdul Basit},
title = {{FPGA} Based Intelligent Hardware Trojan Design and its SoC Implementation},
booktitle = {30th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2023, Istanbul, Turkey, December 4-7, 2023},
pages = {1--4},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICECS58634.2023.10382763},
doi = {10.1109/ICECS58634.2023.10382763},
timestamp = {Thu, 18 Jan 2024 08:27:11 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/MurtazaPMQB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/OztasODA23,
author = {Ali Emre Oztas and
Ege Ozteke and
Mahir Demir and
Tankut Akgul},
title = {Implementation of a Hardware Accelerated {VVC} Decoder on {ARM} and
{FPGA}},
booktitle = {30th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2023, Istanbul, Turkey, December 4-7, 2023},
pages = {1--4},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICECS58634.2023.10382778},
doi = {10.1109/ICECS58634.2023.10382778},
timestamp = {Thu, 18 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/OztasODA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icspcc/LuoHWC23,
author = {Wenqin Luo and
Patrick Hung and
Shiqi Wang and
Ray C. C. Cheung},
title = {Image Super-Resolution and {FPGA} Hardware Design},
booktitle = {{IEEE} International Conference on Signal Processing, Communications
and Computing, {ICSPCC} 2023, Zhengzhou, China, November 14-17, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICSPCC59353.2023.10400225},
doi = {10.1109/ICSPCC59353.2023.10400225},
timestamp = {Wed, 20 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icspcc/LuoHWC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ijcnn/YemmeG23,
author = {Anil Yemme and
Shayan Srinivasa Garani},
title = {A Scalable {GPT-2} Inference Hardware Architecture on {FPGA}},
booktitle = {International Joint Conference on Neural Networks, {IJCNN} 2023, Gold
Coast, Australia, June 18-23, 2023},
pages = {1--8},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/IJCNN54540.2023.10191067},
doi = {10.1109/IJCNN54540.2023.10191067},
timestamp = {Wed, 09 Aug 2023 16:25:09 +0200},
biburl = {https://dblp.org/rec/conf/ijcnn/YemmeG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isaims/Kang23,
author = {Zhengdong Kang},
title = {Hardware acceleration of the {SED} algorithm for Biomolecular activity
predictionBiomolecular activity algorithm {(SED)} uses {FPGA} parallel
programmability to achieve hardware acceleration},
booktitle = {Proceedings of the 2023 4th International Symposium on Artificial
Intelligence for Medicine Science, {ISAIMS} 2023, Chengdu, China,
October 20-22, 2023},
pages = {1136--1140},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3644116.3644309},
doi = {10.1145/3644116.3644309},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isaims/Kang23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChenZMCY023,
author = {Ruiqi Chen and
Haoyang Zhang and
Yuhanxiao Ma and
Jianli Chen and
Jun Yu and
Kun Wang},
title = {eSSpMV: An Embedded-FPGA-based Hardware Accelerator for Symmetric
Sparse Matrix-Vector Multiplication},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2023,
Monterey, CA, USA, May 21-25, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISCAS46773.2023.10181734},
doi = {10.1109/ISCAS46773.2023.10181734},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChenZMCY023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GrafP23,
author = {Jeremy R. Graf and
Darshika G. Perera},
title = {Optimizing Density-Based Ant Colony Stream Clustering Using FPGA-Based
Hardware Accelerator},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2023,
Monterey, CA, USA, May 21-25, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISCAS46773.2023.10181665},
doi = {10.1109/ISCAS46773.2023.10181665},
timestamp = {Mon, 31 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/GrafP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/KishimotoT23,
author = {Yui Kishimoto and
Hiroyuki Torikai},
title = {A hardware-efficient {FPGA} cochlear model for next generation nonlinear
cochlear implant},
booktitle = {20th International SoC Design Conference, {ISOCC} 2023, Jeju, Republic
of Korea, October 25-28, 2023},
pages = {253--255},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISOCC59558.2023.10395971},
doi = {10.1109/ISOCC59558.2023.10395971},
timestamp = {Thu, 22 Feb 2024 20:44:54 +0100},
biburl = {https://dblp.org/rec/conf/isocc/KishimotoT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/GuerrieriM0U23,
author = {Andrea Guerrieri and
Gabriel Da Silva Marques and
Francesco Regazzoni and
Andres Upegui},
title = {H-Saber: An FPGA-Optimized Version for Designing Fast and Efficient
Post-Quantum Cryptography Hardware Accelerators},
booktitle = {24th International Symposium on Quality Electronic Design, {ISQED}
2023, San Francisco, CA, USA, April 5-7, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISQED57927.2023.10129356},
doi = {10.1109/ISQED57927.2023.10129356},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/GuerrieriM0U23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/RajputDD23,
author = {Shailesh Rajput and
Jaya Dofe and
Wafi Danesh},
title = {Automating Hardware Trojan Detection Using Unsupervised Learning:
{A} Case Study of {FPGA}},
booktitle = {24th International Symposium on Quality Electronic Design, {ISQED}
2023, San Francisco, CA, USA, April 5-7, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISQED57927.2023.10129335},
doi = {10.1109/ISQED57927.2023.10129335},
timestamp = {Thu, 01 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/RajputDD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/meco/TanDJM23,
author = {Yiming Tan and
Aditya Diwakar and
Jason Jagielo and
Vincent John Mooney},
title = {Software Compilation Using {FPGA} Hardware: Register Allocation},
booktitle = {12th Mediterranean Conference on Embedded Computing, {MECO} 2023,
Budva, Montenegro, June 6-10, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/MECO58584.2023.10155001},
doi = {10.1109/MECO58584.2023.10155001},
timestamp = {Sun, 24 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/meco/TanDJM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/KordiBFM23,
author = {Farshideh Kordi and
Christian Barnard and
Paul Fortier and
Amine Miled},
title = {FPGA-Based Hardware-in-the-Loop Real-Time Simulation Implementation},
booktitle = {66th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2023, Tempe, AZ, USA, August 6-9, 2023},
pages = {232--235},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/MWSCAS57524.2023.10405949},
doi = {10.1109/MWSCAS57524.2023.10405949},
timestamp = {Sat, 24 Feb 2024 20:42:53 +0100},
biburl = {https://dblp.org/rec/conf/mwscas/KordiBFM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/NguyenZVP23,
author = {Dyk Chung Nguyen and
Yuan{-}Hang Zhang and
Massimiliano Di Ventra and
Yuriy V. Pershin},
title = {Hardware Implementation of Digital Memcomputing on Small-Size FPGAs},
booktitle = {66th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2023, Tempe, AZ, USA, August 6-9, 2023},
pages = {346--350},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/MWSCAS57524.2023.10405845},
doi = {10.1109/MWSCAS57524.2023.10405845},
timestamp = {Sat, 24 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mwscas/NguyenZVP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/WangCYWL23,
author = {Haonan Wang and
Ke Chen and
Chenggang Yan and
Bi Wu and
Weiqiang Liu},
title = {Hardware-Efficient Accurate and Approximate {FPGA} Multipliers for
Error-Tolerant Applications},
booktitle = {66th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2023, Tempe, AZ, USA, August 6-9, 2023},
pages = {977--981},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/MWSCAS57524.2023.10406016},
doi = {10.1109/MWSCAS57524.2023.10406016},
timestamp = {Sat, 24 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mwscas/WangCYWL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/niles/ElgoharyN23,
author = {Ahmed Elgohary and
Omar A. Nasr},
title = {An Efficient Hardware Implementation of {CNN} Generic Processor for
{FPGA}},
booktitle = {5th Novel Intelligent and Leading Emerging Sciences Conference, {NILES}
2023, Giza, Egypt, October 21-23, 2023},
pages = {217--221},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/NILES59815.2023.10296773},
doi = {10.1109/NILES59815.2023.10296773},
timestamp = {Tue, 14 Nov 2023 16:09:49 +0100},
biburl = {https://dblp.org/rec/conf/niles/ElgoharyN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/tencon/RaoP23,
author = {Prajwal S. Rao and
Aparna Pulikala},
title = {Hardware-Optimized Deep Learning Model for FPGA-Based Character Recognition},
booktitle = {{IEEE} Region 10 Conference, {TENCON} 2023, Chiang Mai, Thailand,
October 31 - Nov. 3, 2023},
pages = {238--242},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/TENCON58879.2023.10322427},
doi = {10.1109/TENCON58879.2023.10322427},
timestamp = {Sat, 02 Dec 2023 14:05:41 +0100},
biburl = {https://dblp.org/rec/conf/tencon/RaoP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/uemcom/RexW23,
author = {Eric Rex and
Xiaofang Wang},
editor = {Satyajit Chakrabarti and
Rajashree Paul},
title = {Efficient Quantization and Hardware Implementation of AlexNet on Resource-limited
FPGAs},
booktitle = {14th {IEEE} Annual Ubiquitous Computing, Electronics {\&} Mobile
Communication Conference, {UEMCON} 2023, New York, NY, USA, October
12-14, 2023},
pages = {399--406},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/UEMCON59035.2023.10316010},
doi = {10.1109/UEMCON59035.2023.10316010},
timestamp = {Fri, 24 Nov 2023 20:33:22 +0100},
biburl = {https://dblp.org/rec/conf/uemcom/RexW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PathakS23,
author = {Meghvern Pathak and
Rahul Shrestha},
title = {Hardware Architecture and {FPGA} Implementation of Low Latency Turbo
Encoder for Deep-Space Communication Systems},
booktitle = {36th International Conference on {VLSI} Design and 2023 22nd International
Conference on Embedded Systems, {VLSID} 2023, Hyderabad, India, January
8-12, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSID57277.2023.00016},
doi = {10.1109/VLSID57277.2023.00016},
timestamp = {Sat, 22 Apr 2023 17:02:07 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/PathakS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2302-02959,
author = {Stefan Bosse},
title = {Rule-based High-level Hardware-RTL Synthesis of Algorithms, Virtualizing
Machines, and Communication Protocols with FPGAs based on Concurrent
Communicating Sequential Processes and the ConPro Synthesis Framework},
journal = {CoRR},
volume = {abs/2302.02959},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2302.02959},
doi = {10.48550/ARXIV.2302.02959},
eprinttype = {arXiv},
eprint = {2302.02959},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2302-02959.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2305-01061,
author = {Dyk Chung Nguyen and
Yuan{-}Hang Zhang and
Massimiliano Di Ventra and
Yuriy V. Pershin},
title = {Hardware implementation of digital memcomputing on small-size FPGAs},
journal = {CoRR},
volume = {abs/2305.01061},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2305.01061},
doi = {10.48550/ARXIV.2305.01061},
eprinttype = {arXiv},
eprint = {2305.01061},
timestamp = {Fri, 05 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2305-01061.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2306-09501,
author = {Alessandro Ottaviano and
Robert Balas and
Giovanni Bambini and
Antonio del Vecchio and
Maicol Ciani and
Davide Rossi and
Luca Benini and
Andrea Bartolini},
title = {ControlPULP: {A} {RISC-V} On-Chip Parallel Power Controller for Many-Core
{HPC} Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal
Emulation},
journal = {CoRR},
volume = {abs/2306.09501},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2306.09501},
doi = {10.48550/ARXIV.2306.09501},
eprinttype = {arXiv},
eprint = {2306.09501},
timestamp = {Thu, 22 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2306-09501.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2307-09371,
author = {Manolis Ploumidis and
Fabien Chaix and
Nikolaos Chrysos and
Marios Asiminakis and
Vassilis Flouris and
Nikolaos D. Kallimanis and
Nikolaos Kossifidis and
Michael Nikoloudakis and
Polydoros Petrakis and
Nikolaos Dimou and
Michalis Gianioudis and
Georgios Ieronymakis and
Aggelos Ioannou and
George Kalokerinos and
Pantelis Xirouchakis and
Georgios Ailamakis and
Astrinos Damianakis and
Michael Ligerakis and
Ioannis Makris and
Theocharis Vavouris and
Manolis Katevenis and
Vassilis Papaefstathiou and
Manolis Marazakis and
Iakovos Mavroidis},
title = {The ExaNeSt Prototype: Evaluation of Efficient {HPC} Communication
Hardware in an ARM-based Multi-FPGA Rack},
journal = {CoRR},
volume = {abs/2307.09371},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2307.09371},
doi = {10.48550/ARXIV.2307.09371},
eprinttype = {arXiv},
eprint = {2307.09371},
timestamp = {Tue, 25 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2307-09371.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2309-13321,
author = {Federico Manca and
Francesco Ratto},
title = {ONNX-to-Hardware Design Flow for the Generation of Adaptive Neural-Network
Accelerators on FPGAs},
journal = {CoRR},
volume = {abs/2309.13321},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2309.13321},
doi = {10.48550/ARXIV.2309.13321},
eprinttype = {arXiv},
eprint = {2309.13321},
timestamp = {Wed, 27 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2309-13321.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2309-16158,
author = {Jindong Li and
Guobin Shen and
Dongcheng Zhao and
Qian Zhang and
Yi Zeng},
title = {FireFly v2: Advancing Hardware Support for High-Performance Spiking
Neural Network with a Spatiotemporal {FPGA} Accelerator},
journal = {CoRR},
volume = {abs/2309.16158},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2309.16158},
doi = {10.48550/ARXIV.2309.16158},
eprinttype = {arXiv},
eprint = {2309.16158},
timestamp = {Tue, 20 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2309-16158.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2311-04581,
author = {Suraj Mandal and
Debapriya Basu Roy},
title = {KiD: {A} Hardware Design Framework Targeting Unified {NTT} Multiplication
for CRYSTALS-Kyber and CRYSTALS-Dilithium on {FPGA}},
journal = {CoRR},
volume = {abs/2311.04581},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2311.04581},
doi = {10.48550/ARXIV.2311.04581},
eprinttype = {arXiv},
eprint = {2311.04581},
timestamp = {Tue, 14 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2311-04581.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/BeheraR22,
author = {Sagarika Behera and
Prathuri Jhansi Rani},
title = {Design of Novel Hardware Architecture for Fully Homomorphic Encryption
Algorithms in {FPGA} for Real-Time Data in Cloud Computing},
journal = {{IEEE} Access},
volume = {10},
pages = {131406--131418},
year = {2022},
url = {https://doi.org/10.1109/ACCESS.2022.3229892},
doi = {10.1109/ACCESS.2022.3229892},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/BeheraR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/MolinaGCR22,
author = {Romina Soledad Molina and
Veronica Gil{-}Costa and
Maria Liz Crespo and
Giovanni Ramponi},
title = {High-Level Synthesis Hardware Design for FPGA-Based Accelerators:
Models, Methodologies, and Frameworks},
journal = {{IEEE} Access},
volume = {10},
pages = {90429--90455},
year = {2022},
url = {https://doi.org/10.1109/ACCESS.2022.3201107},
doi = {10.1109/ACCESS.2022.3201107},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/MolinaGCR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/WangCGDCZH22,
author = {Zixiao Wang and
Biyao Che and
Liang Guo and
Yang Du and
Ying Chen and
Jizhuang Zhao and
Wei He},
title = {PipeFL: Hardware/Software co-Design of an {FPGA} Accelerator for Federated
Learning},
journal = {{IEEE} Access},
volume = {10},
pages = {98649--98661},
year = {2022},
url = {https://doi.org/10.1109/ACCESS.2022.3206785},
doi = {10.1109/ACCESS.2022.3206785},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/WangCGDCZH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/YuZWY22,
author = {Le Yu and
Shiwei Zhang and
Nansong Wu and
Chongchong Yu},
title = {FPGA-Based Hardware-in-the-Loop Simulation of User Selection Algorithms
for Cooperative Transmission Technology Over {LOS} Channel on Geosynchronous
Satellites},
journal = {{IEEE} Access},
volume = {10},
pages = {6071--6083},
year = {2022},
url = {https://doi.org/10.1109/ACCESS.2022.3141098},
doi = {10.1109/ACCESS.2022.3141098},
timestamp = {Tue, 08 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/YuZWY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cacm/Mattioli22,
author = {Michael Mattioli},
title = {FPGAs in client compute hardware},
journal = {Commun. {ACM}},
volume = {65},
number = {8},
pages = {36--42},
year = {2022},
url = {https://doi.org/10.1145/3546035},
doi = {10.1145/3546035},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cacm/Mattioli22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cem/ZhangLWLWJ22,
author = {Zhendong Zhang and
Peng Liu and
Weidong Wang and
Shunbin Li and
Peng Wang and
Yingtao Jiang},
title = {High-Performance Password Recovery Hardware Going From {GPU} to Hybrid
{CPU-FPGA} Platform},
journal = {{IEEE} Consumer Electron. Mag.},
volume = {11},
number = {1},
pages = {80--87},
year = {2022},
url = {https://doi.org/10.1109/MCE.2020.3042166},
doi = {10.1109/MCE.2020.3042166},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cem/ZhangLWLWJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computers/Adam22,
author = {George K. Adam},
title = {Co-Design of Multicore Hardware and Multithreaded Software for Thread
Performance Assessment on an {FPGA}},
journal = {Comput.},
volume = {11},
number = {5},
pages = {76},
year = {2022},
url = {https://doi.org/10.3390/computers11050076},
doi = {10.3390/COMPUTERS11050076},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computers/Adam22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/csse/GuptaVJKK22,
author = {Namit Gupta and
Kunwar Singh Vaisla and
Arpit Jain and
Adesh Kumar and
Rajeev Kumar},
title = {Performance Analysis of {AODV} Routing for Wireless Sensor Network
in {FPGA} Hardware},
journal = {Comput. Syst. Sci. Eng.},
volume = {40},
number = {3},
pages = {1073--1084},
year = {2022},
url = {https://doi.org/10.32604/csse.2022.019911},
doi = {10.32604/CSSE.2022.019911},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/csse/GuptaVJKK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/MukherjeeC22,
author = {Rijoy Mukherjee and
Rajat Subhra Chakraborty},
title = {Novel Hardware Trojan Attack on Activation Parameters of FPGA-Based
{DNN} Accelerators},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {14},
number = {3},
pages = {131--134},
year = {2022},
url = {https://doi.org/10.1109/LES.2022.3159541},
doi = {10.1109/LES.2022.3159541},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/MukherjeeC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/RSAP22,
author = {Naveenkumar R and
N. M. Sivamangai and
Napolean A and
S. Sridevi Sathya Priya},
title = {Design and Evaluation of {XOR} Arbiter Physical Unclonable Function
and its Implementation on {FPGA} in Hardware Security Applications},
journal = {J. Electron. Test.},
volume = {38},
number = {6},
pages = {653--666},
year = {2022},
url = {https://doi.org/10.1007/s10836-022-06034-7},
doi = {10.1007/S10836-022-06034-7},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/et/RSAP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceee/ZhangGHZCY22,
author = {Fei Zhang and
Ziyang Gao and
Jiaming Huang and
Peining Zhen and
Hai{-}Bao Chen and
Jie Yan},
title = {{HFOD:} {A} hardware-friendly quantization method for object detection
on embedded FPGAs},
journal = {{IEICE} Electron. Express},
volume = {19},
number = {8},
pages = {20220067},
year = {2022},
url = {https://doi.org/10.1587/elex.19.20220067},
doi = {10.1587/ELEX.19.20220067},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceee/ZhangGHZCY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceee/ZufengG22,
author = {Luo Zufeng and
Yuan Guo{-}shun},
title = {{LDCPUF:} {A} novel FPGA-based physical unclonable function with ultra-low
hardware cost},
journal = {{IEICE} Electron. Express},
volume = {19},
number = {16},
pages = {20220246},
year = {2022},
url = {https://doi.org/10.1587/elex.19.20220246},
doi = {10.1587/ELEX.19.20220246},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceee/ZufengG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/ManabeKS22,
author = {Taito Manabe and
Taichi Katayama and
Yuichiro Shibata},
title = {{FPGA} Implementation of a Stream-Based Real-Time Hardware Line Segment
Detector},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {105-A},
number = {3},
pages = {468--477},
year = {2022},
url = {https://doi.org/10.1587/transfun.2021vlp0009},
doi = {10.1587/TRANSFUN.2021VLP0009},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/ManabeKS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/MoriMS22,
author = {Tatsuma Mori and
Taito Manabe and
Yuichiro Shibata},
title = {A Hardware Oriented Approximate Convex Hull Algorithm and its {FPGA}
Implementation},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {105-A},
number = {3},
pages = {459--467},
year = {2022},
url = {https://doi.org/10.1587/transfun.2021vlp0016},
doi = {10.1587/TRANSFUN.2021VLP0016},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/MoriMS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijcomsys/VenkataramananL22,
author = {V. Venkataramanan and
S. Lakshmi},
title = {Performance analysis of {LTE} physical layer using hardware cosimulation
techniques and implementation on {FPGA} for communication systems},
journal = {Int. J. Commun. Syst.},
volume = {35},
number = {2},
year = {2022},
url = {https://doi.org/10.1002/dac.4125},
doi = {10.1002/DAC.4125},
timestamp = {Fri, 21 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijcomsys/VenkataramananL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijnm/HuangGS22,
author = {Xiaoying Huang and
Zhichuan Guo and
Mangu Song},
title = {{FGLB:} {A} fine-grained hardware intra-server load balancer based
on 100 {G} {FPGA} SmartNIC},
journal = {Int. J. Netw. Manag.},
volume = {32},
number = {6},
year = {2022},
url = {https://doi.org/10.1002/nem.2211},
doi = {10.1002/NEM.2211},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijnm/HuangGS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jce/GrossJZS22,
author = {Mathieu Gross and
Nisha Jacob and
Andreas Zankl and
Georg Sigl},
title = {Breaking TrustZone memory isolation and secure boot through malicious
hardware on a modern FPGA-SoC},
journal = {J. Cryptogr. Eng.},
volume = {12},
number = {2},
pages = {181--196},
year = {2022},
url = {https://doi.org/10.1007/s13389-021-00273-8},
doi = {10.1007/S13389-021-00273-8},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jce/GrossJZS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/GuptaC22,
author = {Mangal Deep Gupta and
Rajeev K. Chauhan},
title = {Hardware Efficient Pseudo-Random Number Generator Using Chen Chaotic
System on {FPGA}},
journal = {J. Circuits Syst. Comput.},
volume = {31},
number = {3},
pages = {2250043:1--2250043:14},
year = {2022},
url = {https://doi.org/10.1142/S0218126622500438},
doi = {10.1142/S0218126622500438},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/GuptaC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/AnandakumarHS22,
author = {N. Nalla Anandakumar and
Mohammad S. Hashmi and
Somitra Kumar Sanadhya},
title = {Design and Analysis of FPGA-based PUFs with Enhanced Performance for
Hardware-oriented Security},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {18},
number = {4},
pages = {72:1--72:26},
year = {2022},
url = {https://doi.org/10.1145/3517813},
doi = {10.1145/3517813},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/AnandakumarHS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/PalumboCLHRBO22,
author = {Alessandro Palumbo and
Luca Cassano and
Bruno Luzzi and
Jos{\'{e}} Alberto Hern{\'{a}}ndez and
Pedro Reviriego and
Giuseppe Bianchi and
Marco Ottavi},
title = {Is your {FPGA} bitstream Hardware Trojan-free? Machine learning can
provide an answer},
journal = {J. Syst. Archit.},
volume = {128},
pages = {102543},
year = {2022},
url = {https://doi.org/10.1016/j.sysarc.2022.102543},
doi = {10.1016/J.SYSARC.2022.102543},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/PalumboCLHRBO22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/lgrs/MaciasBBG22,
author = {Rub{\'{e}}n Macias and
Sergio Bernab{\'{e}} and
Daniel B{\'{a}}scones and
Carlos Gonz{\'{a}}lez},
title = {{FPGA} Implementation of a Hardware Optimized Automatic Target Detection
and Classification Algorithm for Hyperspectral Image Analysis},
journal = {{IEEE} Geosci. Remote. Sens. Lett.},
volume = {19},
pages = {1--5},
year = {2022},
url = {https://doi.org/10.1109/LGRS.2022.3189109},
doi = {10.1109/LGRS.2022.3189109},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/lgrs/MaciasBBG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/FariasNC22,
author = {Marcos Santana Farias and
Nadia Nedjah and
Paulo Victor R. de Carvalho},
title = {Active redundant hardware architecture for increased reliability in
FPGA-based nuclear reactors critical systems},
journal = {Microprocess. Microsystems},
volume = {90},
pages = {104495},
year = {2022},
url = {https://doi.org/10.1016/j.micpro.2022.104495},
doi = {10.1016/J.MICPRO.2022.104495},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/FariasNC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/HamdaouiBM22,
author = {Fay{\c{c}}al Hamdaoui and
Sana Bougharriou and
Abdellatif Mtibaa},
title = {Optimized Hardware Vision System for Vehicle Detection based on {FPGA}
and Combining Machine Learning and {PSO}},
journal = {Microprocess. Microsystems},
volume = {90},
pages = {104469},
year = {2022},
url = {https://doi.org/10.1016/j.micpro.2022.104469},
doi = {10.1016/J.MICPRO.2022.104469},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/HamdaouiBM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/WulfWG22,
author = {Cornelia Wulf and
Michael Willig and
Diana Goehringer},
title = {RTOS-supported low power scheduling of periodic hardware tasks in
flash-based FPGAs},
journal = {Microprocess. Microsystems},
volume = {92},
pages = {104566},
year = {2022},
url = {https://doi.org/10.1016/j.micpro.2022.104566},
doi = {10.1016/J.MICPRO.2022.104566},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/WulfWG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/LiHCGHX22,
author = {Xueming Li and
Hongmin Huang and
Taosheng Chen and
Huaien Gao and
Xianghong Hu and
Xiaoming Xiong},
title = {A hardware-efficient computing engine for FPGA-based deep convolutional
neural network accelerator},
journal = {Microelectron. J.},
volume = {128},
pages = {105547},
year = {2022},
url = {https://doi.org/10.1016/j.mejo.2022.105547},
doi = {10.1016/J.MEJO.2022.105547},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/LiHCGHX22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/monet/Pham-QuocNT22,
author = {Cuong Pham{-}Quoc and
Xuan Quang Nguyen and
Tran Ngoc Thinh},
title = {Towards An FPGA-targeted Hardware/Software Co-design Framework for
CNN-based Edge Computing},
journal = {Mob. Networks Appl.},
volume = {27},
number = {5},
pages = {2024--2035},
year = {2022},
url = {https://doi.org/10.1007/s11036-022-01985-9},
doi = {10.1007/S11036-022-01985-9},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/monet/Pham-QuocNT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ojcands/GoldsmithCS22,
author = {Josh Goldsmith and
Louise H. Crockett and
Robert W. Stewart},
title = {A Natively Fixed-Point Run-Time Reconfigurable {FIR} Filter Design
Method for {FPGA} Hardware},
journal = {{IEEE} Open J. Circuits Syst.},
volume = {3},
pages = {25--37},
year = {2022},
url = {https://doi.org/10.1109/OJCAS.2022.3152399},
doi = {10.1109/OJCAS.2022.3152399},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ojcands/GoldsmithCS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/remotesensing/PitonakMDJM22,
author = {Radoslav Pitonak and
Jan Mucha and
Lukas Dobis and
Martin Javorka and
Marek Marusin},
title = {CloudSatNet-1: FPGA-Based Hardware-Accelerated Quantized {CNN} for
Satellite On-Board Cloud Coverage Classification},
journal = {Remote. Sens.},
volume = {14},
number = {13},
pages = {3180},
year = {2022},
url = {https://doi.org/10.3390/rs14133180},
doi = {10.3390/RS14133180},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/remotesensing/PitonakMDJM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/SilvaPMNMF22,
author = {Jo{\~{a}}o Silva and
Pedro Pereira and
Rui Machado and
Rafael N{\'{e}}voa and
Pedro Melo{-}Pinto and
Duarte Fernandes},
title = {Customizable FPGA-Based Hardware Accelerator for Standard Convolution
Processes Empowered with Quantization Applied to LiDAR Data},
journal = {Sensors},
volume = {22},
number = {6},
pages = {2184},
year = {2022},
url = {https://doi.org/10.3390/s22062184},
doi = {10.3390/S22062184},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sensors/SilvaPMNMF22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/SuiLBZZYT22,
author = {Xuefu Sui and
Qunbo Lv and
Yang Bai and
Baoyu Zhu and
Liangjie Zhi and
Yuanbo Yang and
Zheng Tan},
title = {A Hardware-Friendly Low-Bit Power-of-Two Quantization Method for CNNs
and Its {FPGA} Implementation},
journal = {Sensors},
volume = {22},
number = {17},
pages = {6618},
year = {2022},
url = {https://doi.org/10.3390/s22176618},
doi = {10.3390/S22176618},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sensors/SuiLBZZYT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sncs/OdetolaGYKH22,
author = {Tolulope A. Odetola and
Katie M. Groves and
Muhammed Yousufuddin and
Faiq Khalid and
Syed Rafay Hasan},
title = {2L-3W: 2-Level 3-Way Hardware-Software Co-verification for the Mapping
of Convolutional Neural Network {(CNN)} onto {FPGA} Boards},
journal = {{SN} Comput. Sci.},
volume = {3},
number = {1},
pages = {60},
year = {2022},
url = {https://doi.org/10.1007/s42979-021-00954-5},
doi = {10.1007/S42979-021-00954-5},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sncs/OdetolaGYKH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/symmetry/SongHLXXHR22,
author = {Qi Song and
Yourui Huang and
Wenhao Lai and
Jiachang Xu and
Shanyong Xu and
Tao Han and
Xue Rong},
title = {{FPGA} Hardware Realization of Membrane Calculation Optimization Algorithm
with Great Parallelism},
journal = {Symmetry},
volume = {14},
number = {10},
pages = {2199},
year = {2022},
url = {https://doi.org/10.3390/sym14102199},
doi = {10.3390/SYM14102199},
timestamp = {Mon, 05 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/symmetry/SongHLXXHR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/RodriguezOPT22,
author = {Alfonso Rodr{\'{\i}}guez and
Andr{\'{e}}s Otero and
Marco Platzner and
Eduardo de la Torre},
title = {Exploiting Hardware-Based Data-Parallel and Multithreading Models
for Smart Edge Computing in Reconfigurable FPGAs},
journal = {{IEEE} Trans. Computers},
volume = {71},
number = {11},
pages = {2903--2914},
year = {2022},
url = {https://doi.org/10.1109/TC.2021.3107196},
doi = {10.1109/TC.2021.3107196},
timestamp = {Mon, 05 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/RodriguezOPT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/UllahRSK22,
author = {Salim Ullah and
Semeen Rehman and
Muhammad Shafique and
Akash Kumar},
title = {High-Performance Accurate and Approximate Multipliers for FPGA-Based
Hardware Accelerators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {2},
pages = {211--224},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3056337},
doi = {10.1109/TCAD.2021.3056337},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/UllahRSK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/LiuCYG22,
author = {Yijun Liu and
Yuehai Chen and
Wujian Ye and
Yu Gui},
title = {{FPGA-NHAP:} {A} General FPGA-Based Neuromorphic Hardware Acceleration
Platform With High Speed and Low Power},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {69},
number = {6},
pages = {2553--2566},
year = {2022},
url = {https://doi.org/10.1109/TCSI.2022.3160693},
doi = {10.1109/TCSI.2022.3160693},
timestamp = {Mon, 13 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasI/LiuCYG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/LiuLHLQCLZ22,
author = {Ye Liu and
Jingyuan Li and
Kun Huang and
Xiangting Li and
Xiuyuan Qi and
Liang Chang and
Yu Long and
Jun Zhou},
title = {MobileSP: An FPGA-Based Real-Time Keypoint Extraction Hardware Accelerator
for Mobile {VSLAM}},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {69},
number = {12},
pages = {4919--4929},
year = {2022},
url = {https://doi.org/10.1109/TCSI.2022.3190300},
doi = {10.1109/TCSI.2022.3190300},
timestamp = {Fri, 06 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasI/LiuLHLQCLZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasII/KaurKA22,
author = {Jasmin Kaur and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {Hardware Constructions for Error Detection in Lightweight Authenticated
Cipher {ASCON} Benchmarked on {FPGA}},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {69},
number = {4},
pages = {2276--2280},
year = {2022},
url = {https://doi.org/10.1109/TCSII.2021.3136463},
doi = {10.1109/TCSII.2021.3136463},
timestamp = {Sat, 21 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasII/KaurKA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tetc/KaurSKA22,
author = {Jasmin Kaur and
Ausmita Sarker and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {Hardware Constructions for Error Detection in Lightweight Welch-Gong
(WG)-Oriented Streamcipher {WAGE} Benchmarked on {FPGA}},
journal = {{IEEE} Trans. Emerg. Top. Comput.},
volume = {10},
number = {2},
pages = {1208--1215},
year = {2022},
url = {https://doi.org/10.1109/TETC.2021.3073163},
doi = {10.1109/TETC.2021.3073163},
timestamp = {Tue, 28 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tetc/KaurSKA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tie/XuGCJQ22,
author = {Fang Xu and
Zhongyi Guo and
Hong Chen and
Dongdong Ji and
Ting Qu},
title = {A Custom Parallel Hardware Architecture of Nonlinear Model-Predictive
Control on {FPGA}},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {69},
number = {11},
pages = {11569--11579},
year = {2022},
url = {https://doi.org/10.1109/TIE.2021.3118427},
doi = {10.1109/TIE.2021.3118427},
timestamp = {Tue, 28 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tie/XuGCJQ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tnn/HuangWCLZLH22,
author = {Wenjin Huang and
Huangtao Wu and
Qingkun Chen and
Conghui Luo and
Shihao Zeng and
Tianrui Li and
Yihua Huang},
title = {FPGA-Based High-Throughput {CNN} Hardware Accelerator With High Computing
Resource Utilization Ratio},
journal = {{IEEE} Trans. Neural Networks Learn. Syst.},
volume = {33},
number = {8},
pages = {4069--4083},
year = {2022},
url = {https://doi.org/10.1109/TNNLS.2021.3055814},
doi = {10.1109/TNNLS.2021.3055814},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tnn/HuangWCLZLH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DamianiFBBS22,
author = {Andrea Damiani and
Giorgia Fiscaletti and
Marco Bacis and
Rolando Brondolin and
Marco D. Santambrogio},
title = {BlastFunction: {A} Full-stack Framework Bringing {FPGA} Hardware Acceleration
to Cloud-native Applications},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {2},
pages = {17:1--17:27},
year = {2022},
url = {https://doi.org/10.1145/3472958},
doi = {10.1145/3472958},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DamianiFBBS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GhaffariCL22,
author = {Sina Ghaffari and
David W. Capson and
Kin Fun Li},
title = {A Fully Pipelined {FPGA} Architecture for Multiscale {BRISK} Descriptors
With a Novel Hardware-Aware Sampling Pattern},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {826--839},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3151896},
doi = {10.1109/TVLSI.2022.3151896},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GhaffariCL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEssd/AouissaouiBS22,
author = {Ichraf Aouissaoui and
Toufik Bakir and
Anis Sakly},
title = {{FPGA} Hardware Co-Simulation of a Stream Cipher Image Cryptosystem
based on Fixed-Point Chaotic Map},
booktitle = {19th International Multi-Conference on Systems, Signals {\&} Devices,
{SSD} 2022, S{\'{e}}tif, Algeria, May 6-10, 2022},
pages = {1764--1769},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/SSD54932.2022.9955847},
doi = {10.1109/SSD54932.2022.9955847},
timestamp = {Tue, 06 Dec 2022 09:27:55 +0100},
biburl = {https://dblp.org/rec/conf/IEEEssd/AouissaouiBS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/acssc/MohamedC22,
author = {Nadya A. Mohamed and
Joseph R. Cavallaro},
title = {FPGA-based {DNN} Hardware Accelerator for Sensor Network Aggregation
Node},
booktitle = {56th Asilomar Conference on Signals, Systems, and Computers, {ACSSC}
2022, Pacific Grove, CA, USA, October 31 - Nov. 2, 2022},
pages = {322--327},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/IEEECONF56349.2022.10051920},
doi = {10.1109/IEEECONF56349.2022.10051920},
timestamp = {Fri, 10 Mar 2023 11:53:17 +0100},
biburl = {https://dblp.org/rec/conf/acssc/MohamedC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aii2/BorelliSGF22,
author = {Antonio Borelli and
Fanny Spagnolo and
Raffaele Gravina and
Fabio Frustaci},
title = {An FPGA-Based Hardware Accelerator for the k-Nearest Neighbor Algorithm
Implementation in Wearable Embedded Systems},
booktitle = {{AII}},
pages = {44--56},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-24801-6\_4},
doi = {10.1007/978-3-031-24801-6\_4},
timestamp = {Sat, 25 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aii2/BorelliSGF22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aii2/HuzyukSF22,
author = {Roman Huzyuk and
Fanny Spagnolo and
Fabio Frustaci},
title = {Designing Low-Power and High-Speed FPGA-Based Binary Decision Tree
Hardware Accelerators},
booktitle = {{AII}},
pages = {57--72},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-24801-6\_5},
doi = {10.1007/978-3-031-24801-6\_5},
timestamp = {Sat, 25 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aii2/HuzyukSF22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aiml2/VR22,
author = {Sanjaya M. V and
Madhav Rao},
title = {An hardware accelerator design of Mobile-Net model on {FPGA}},
booktitle = {Proceedings of the Second International Conference on {AI-ML} Systems,
AIMLSystems 2022, Bangalore, India, October 12-15, 2022},
pages = {2:1--2:9},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3564121.3564124},
doi = {10.1145/3564121.3564124},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aiml2/VR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/applepies/CaneseCNFRS22,
author = {Lorenzo Canese and
Gian Carlo Cardarilli and
Luca Di Nunzio and
Rocco Fazzolari and
Marco Re and
Sergio Span{\`{o}}},
editor = {Riccardo Berta and
Alessandro De Gloria},
title = {Automatic {IP} Core Generator for FPGA-Based Q-Learning Hardware Accelerators},
booktitle = {Applications in Electronics Pervading Industry, Environment and Society
- {APPLEPIES} 2022, Genoa, Italy, 26-27 September 2022},
series = {Lecture Notes in Electrical Engineering},
volume = {1036},
pages = {242--247},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-30333-3\_32},
doi = {10.1007/978-3-031-30333-3\_32},
timestamp = {Mon, 08 May 2023 15:55:39 +0200},
biburl = {https://dblp.org/rec/conf/applepies/CaneseCNFRS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/applepies/DonisiBLLR22,
author = {Andrea Donisi and
Luigi Di Benedetto and
Rosalba Liguori and
Gian Domenico Licciardo and
Alfredo Rubino},
editor = {Riccardo Berta and
Alessandro De Gloria},
title = {A {FPGA} HardWare Architecture for {AZSPWM} Based on a Taylor Series
Decomposition},
booktitle = {Applications in Electronics Pervading Industry, Environment and Society
- {APPLEPIES} 2022, Genoa, Italy, 26-27 September 2022},
series = {Lecture Notes in Electrical Engineering},
volume = {1036},
pages = {73--81},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-30333-3\_10},
doi = {10.1007/978-3-031-30333-3\_10},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/applepies/DonisiBLLR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/applepies/MansooriC22,
author = {Mohammad Amir Mansoori and
Mario R. Casu},
editor = {Riccardo Berta and
Alessandro De Gloria},
title = {Multi-objective Framework for Training and Hardware Co-optimization
in FPGAs},
booktitle = {Applications in Electronics Pervading Industry, Environment and Society
- {APPLEPIES} 2022, Genoa, Italy, 26-27 September 2022},
series = {Lecture Notes in Electrical Engineering},
volume = {1036},
pages = {273--278},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-30333-3\_36},
doi = {10.1007/978-3-031-30333-3\_36},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/applepies/MansooriC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arcs/PassarettiBWP22,
author = {Daniele Passaretti and
Felix Boehm and
Martin Wilhelm and
Thilo Pionteck},
editor = {Martin Schulz and
Carsten Trinitis and
Nikela Papadopoulou and
Thilo Pionteck},
title = {Hardware Isolation Support for Low-Cost SoC-FPGAs},
booktitle = {Architecture of Computing Systems - 35th International Conference,
{ARCS} 2022, Heilbronn, Germany, September 13-15, 2022, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {13642},
pages = {148--163},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-21867-5\_10},
doi = {10.1007/978-3-031-21867-5\_10},
timestamp = {Tue, 20 Dec 2022 09:38:33 +0100},
biburl = {https://dblp.org/rec/conf/arcs/PassarettiBWP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/EjjehMCNSANNR22,
author = {Adel Ejjeh and
Leon Medvinsky and
Aaron Councilman and
Hemang Nehra and
Suraj Sharma and
Vikram S. Adve and
Luigi Nardi and
Eriko Nurvitadhi and
Rob A. Rutenbar},
title = {{HPVM2FPGA:} Enabling True Hardware-Agnostic {FPGA} Programming},
booktitle = {33rd {IEEE} International Conference on Application-specific Systems,
Architectures and Processors, {ASAP} 2022, Gothenburg, Sweden, July
12-14, 2022},
pages = {1--10},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ASAP54787.2022.00012},
doi = {10.1109/ASAP54787.2022.00012},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/EjjehMCNSANNR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asiasim/ZhaoZL22,
author = {Yu Zhao and
Chun Zhao and
Yue Liu},
editor = {Wenhui Fan and
Lin Zhang and
Ni Li and
Xiao Song},
title = {FPGA-Based Hardware Modeling on Pigeon-Inspired Optimization Algorithm},
booktitle = {Methods and Applications for Modeling and Simulation of Complex Systems
- 21st Asia Simulation Conference, AsiaSim 2022, Changsha, China,
December 9-11, 2022, Proceedings, Part {I}},
series = {Communications in Computer and Information Science},
volume = {1712},
pages = {407--423},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-981-19-9198-1\_31},
doi = {10.1007/978-981-19-9198-1\_31},
timestamp = {Wed, 08 Mar 2023 10:20:10 +0100},
biburl = {https://dblp.org/rec/conf/asiasim/ZhaoZL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asse/HuangRY22,
author = {Hui Huang and
Hai{-}Jun Rong and
Zhao{-}Xu Yang},
title = {A Task-Parallel and Reconfigurable FPGA-Based Hardware Implementation
of Extreme Learning Machine},
booktitle = {{ASSE} 2022: 3rd Asia Service Sciences and Software Engineering Conference,
Macao, February 24 - 26, 2022},
pages = {194--202},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3523181.3523209},
doi = {10.1145/3523181.3523209},
timestamp = {Wed, 20 Apr 2022 19:32:12 +0200},
biburl = {https://dblp.org/rec/conf/asse/HuangRY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cec/FritzschHB22,
author = {Clemens Fritzsch and
J{\"{o}}rn Hoffmann and
Martin Bogdan},
title = {Evolving Hardware by Direct Bitstream Manipulation of a Modern {FPGA}},
booktitle = {{IEEE} Congress on Evolutionary Computation, {CEC} 2022, Padua, Italy,
July 18-23, 2022},
pages = {1--8},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/CEC55065.2022.9870297},
doi = {10.1109/CEC55065.2022.9870297},
timestamp = {Mon, 12 Sep 2022 17:48:09 +0200},
biburl = {https://dblp.org/rec/conf/cec/FritzschHB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codit/ElloumiSR22,
author = {Hejer Elloumi and
Dorra Sellami and
Hassan Rabah},
title = {A Flexible Hardware Accelerator for Morphological Filters on {FPGA}},
booktitle = {8th International Conference on Control, Decision and Information
Technologies, CoDIT 2022, Istanbul, Turkey, May 17-20, 2022},
pages = {550--555},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/CoDIT55151.2022.9804025},
doi = {10.1109/CODIT55151.2022.9804025},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/codit/ElloumiSR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PengHCLGLJWBLD22,
author = {Hongwu Peng and
Shaoyi Huang and
Shiyang Chen and
Bingbing Li and
Tong Geng and
Ang Li and
Weiwen Jiang and
Wujie Wen and
Jinbo Bi and
Hang Liu and
Caiwen Ding},
editor = {Rob Oshana},
title = {A length adaptive algorithm-hardware co-design of transformer on {FPGA}
through sparse attention and dynamic pipelining},
booktitle = {{DAC} '22: 59th {ACM/IEEE} Design Automation Conference, San Francisco,
California, USA, July 10 - 14, 2022},
pages = {1135--1140},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3489517.3530585},
doi = {10.1145/3489517.3530585},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/PengHCLGLJWBLD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HanZLZGJ22,
author = {Mingqin Han and
Yilan Zhu and
Qian Lou and
Zimeng Zhou and
Shanqing Guo and
Lei Ju},
editor = {Cristiana Bolchini and
Ingrid Verbauwhede and
Ioana Vatajelu},
title = {coxHE: {A} software-hardware co-design framework for {FPGA} acceleration
of homomorphic computation},
booktitle = {2022 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2022, Antwerp, Belgium, March 14-23, 2022},
pages = {1353--1358},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.23919/DATE54114.2022.9774559},
doi = {10.23919/DATE54114.2022.9774559},
timestamp = {Tue, 07 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/HanZLZGJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/Awan22,
author = {Ahsan Javed Awan},
title = {Towards Hardware Support for {FPGA} Resource Elasticity},
booktitle = {25th Euromicro Conference on Digital System Design, {DSD} 2022, Maspalomas,
Spain, August 31 - Sept. 2, 2022},
pages = {9--15},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/DSD57027.2022.00011},
doi = {10.1109/DSD57027.2022.00011},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/Awan22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/HerrmannKSS22,
author = {Viktor Herrmann and
Justin Knapheide and
Fritjof Steinert and
Benno Stabernack},
title = {A {YOLO} v3-tiny {FPGA} Architecture using a Reconfigurable Hardware
Accelerator for Real-time Region of Interest Detection},
booktitle = {25th Euromicro Conference on Digital System Design, {DSD} 2022, Maspalomas,
Spain, August 31 - Sept. 2, 2022},
pages = {84--92},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/DSD57027.2022.00021},
doi = {10.1109/DSD57027.2022.00021},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/HerrmannKSS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/SciangulaRBB22,
author = {Gerlando Sciangula and
Francesco Restuccia and
Alessandro Biondi and
Giorgio C. Buttazzo},
title = {Hardware Acceleration of Deep Neural Networks for Autonomous Driving
on FPGA-based SoC},
booktitle = {25th Euromicro Conference on Digital System Design, {DSD} 2022, Maspalomas,
Spain, August 31 - Sept. 2, 2022},
pages = {406--414},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/DSD57027.2022.00061},
doi = {10.1109/DSD57027.2022.00061},
timestamp = {Thu, 22 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/SciangulaRBB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/embc/GudurMBAS22,
author = {Venkateshwarlu Yellaswamy Gudur and
Sidharth Maheshwari and
Swati Bhardwaj and
Amit Acharyya and
Rishad A. Shafik},
title = {Hardware-Algorithm Codesign for Fast and Energy Efficient Approximate
String Matching on {FPGA} for Computational Biology},
booktitle = {44th Annual International Conference of the {IEEE} Engineering in
Medicine {\&} Biology Society, {EMBC} 2022, Glasgow, Scotland,
United Kingdom, July 11-15, 2022},
pages = {87--90},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/EMBC48229.2022.9870924},
doi = {10.1109/EMBC48229.2022.9870924},
timestamp = {Thu, 22 Sep 2022 19:31:35 +0200},
biburl = {https://dblp.org/rec/conf/embc/GudurMBAS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/epia/PereiraSMSDMNMM22,
author = {Pedro Pereira and
Ant{\'{o}}nio Silva and
Rui Machado and
Jo{\~{a}}o Silva and
Dalila Dur{\~{a}}es and
Jos{\'{e}} Machado and
Paulo Novais and
Jo{\~{a}}o Monteiro and
Pedro Melo{-}Pinto and
Duarte Fernandes},
editor = {Goreti Marreiros and
Bruno Martins and
Ana Paiva and
Bernardete Ribeiro and
Alberto Sardinha},
title = {Comparison of Different Deployment Approaches of FPGA-Based Hardware
Accelerator for 3D Object Detection Models},
booktitle = {Progress in Artificial Intelligence - 21st {EPIA} Conference on Artificial
Intelligence, {EPIA} 2022, Lisbon, Portugal, August 31 - September
2, 2022, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {13566},
pages = {285--296},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-16474-3\_24},
doi = {10.1007/978-3-031-16474-3\_24},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/epia/PereiraSMSDMNMM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GaoWS22,
author = {Yizhao Gao and
Song Wang and
Hayden Kwok{-}Hay So},
editor = {Michael Adler and
Paolo Ienne},
title = {{REMOT:} {A} Hardware-Software Architecture for Attention-Guided Multi-Object
Tracking with Dynamic Vision Sensors on FPGAs},
booktitle = {{FPGA} '22: The 2022 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022},
pages = {158--168},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3490422.3502365},
doi = {10.1145/3490422.3502365},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/GaoWS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LiuOGB22,
author = {Yanqi Liu and
Anthony Opipari and
Th{\'{e}}o Gu{\'{e}}rin and
Ruth Iris Bahar},
editor = {Michael Adler and
Paolo Ienne},
title = {Hardware Acceleration of Nonparametric Belief Propagation for Efficient
Robot Manipulation},
booktitle = {{FPGA} '22: The 2022 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022},
pages = {51},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3490422.3502329},
doi = {10.1145/3490422.3502329},
timestamp = {Mon, 14 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LiuOGB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ShadabZGAL22,
author = {Rakin Muhammad Shadab and
Yu Zou and
Sanjay Gandham and
Amro Awad and
Mingjie Lin},
editor = {Michael Adler and
Paolo Ienne},
title = {{HMT:} {A} Hardware-Centric Hybrid Bonsai Merkle Tree Algorithm for
High-Performance Authentication},
booktitle = {{FPGA} '22: The 2022 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022},
pages = {52},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3490422.3502345},
doi = {10.1145/3490422.3502345},
timestamp = {Mon, 14 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ShadabZGAL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ArthantoO022,
author = {Yashael Faith Arthanto and
David Ojika and
Joo{-}Young Kim},
title = {{FSHMEM:} Supporting Partitioned Global Address Space on FPGAs for
Large-Scale Hardware Acceleration Infrastructure},
booktitle = {32nd International Conference on Field-Programmable Logic and Applications,
{FPL} 2022, Belfast, United Kingdom, August 29 - Sept. 2, 2022},
pages = {218--224},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/FPL57034.2022.00042},
doi = {10.1109/FPL57034.2022.00042},
timestamp = {Mon, 20 Feb 2023 17:38:16 +0100},
biburl = {https://dblp.org/rec/conf/fpl/ArthantoO022.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/WangZCYCZWCB22,
author = {Zelin Wang and
Ke Zhang and
Yisong Chang and
Yanlong Yin and
Yuxiao Chen and
Ran Zhao and
Songyue Wang and
Mingyu Chen and
Yungang Bao},
title = {{FPL} Demo: {SERVE:} Agile Hardware Development Platform with Cloud
{IDE} and Cloud FPGAs},
booktitle = {32nd International Conference on Field-Programmable Logic and Applications,
{FPL} 2022, Belfast, United Kingdom, August 29 - Sept. 2, 2022},
pages = {471},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/FPL57034.2022.00087},
doi = {10.1109/FPL57034.2022.00087},
timestamp = {Sat, 19 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/WangZCYCZWCB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/SouvatzoglouAAV22,
author = {Ioanna Souvatzoglou and
Dimitris Agiakatsikas and
George Antonopoulos and
Vasileios Vlagkoulis and
Aitzan Sari and
Athanasios Papadimitriou and
Mihalis Psarakis},
title = {The Impact of Hardware Folding on Dependability in Spaceborne FPGA-based
Neural Networks},
booktitle = {International Conference on Field-Programmable Technology, {(IC)FPT}
2022, Hong Kong, December 5-9, 2022},
pages = {1},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ICFPT56656.2022.9974551},
doi = {10.1109/ICFPT56656.2022.9974551},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/SouvatzoglouAAV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/YaoZ22,
author = {Shangshang Yao and
Liang Zhang},
title = {Hardware-Efficient FPGA-Based Approximate Multipliers for Error-Tolerant
Computing},
booktitle = {International Conference on Field-Programmable Technology, {(IC)FPT}
2022, Hong Kong, December 5-9, 2022},
pages = {1--8},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ICFPT56656.2022.9974399},
doi = {10.1109/ICFPT56656.2022.9974399},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/YaoZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gecco/0001FB22,
author = {J{\"{o}}rn Hoffmann and
Clemens Fritzsch and
Martin Bogdan},
editor = {Jonathan E. Fieldsend and
Markus Wagner},
title = {CoBEA: framework for evolving hardware by direct manipulation of {FPGA}
bitstreams},
booktitle = {{GECCO} '22: Genetic and Evolutionary Computation Conference, Companion
Volume, Boston, Massachusetts, USA, July 9 - 13, 2022},
pages = {112--115},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3520304.3528821},
doi = {10.1145/3520304.3528821},
timestamp = {Mon, 25 Jul 2022 17:04:27 +0200},
biburl = {https://dblp.org/rec/conf/gecco/0001FB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/KarleKP022,
author = {Christian Maximilian Karle and
Marius Kreutzer and
Johannes Pfau and
J{\"{u}}rgen Becker},
title = {A hardware/software co-design approach to prototype 6G mobile applications
inside the {GNU} Radio {SDR} Ecosystem using {FPGA} hardware accelerators},
booktitle = {{HEART} 2022: International Symposium on Highly-Efficient Accelerators
and Reconfigurable Technologies, Tsukuba, Japan, June 9 - 10, 2022},
pages = {33--41},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3535044.3535049},
doi = {10.1145/3535044.3535049},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/heart/KarleKP022.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hotchips/ShumarayevCHK22,
author = {Sergey Y. Shumarayev and
Allen Chan and
Tim Hoang and
Robert Keller},
title = {Heterogenous Integration Enables {FPGA} Based Hardware Acceleration
for {RF} Applications},
booktitle = {2022 {IEEE} Hot Chips 34 Symposium, {HCS} 2022, Cupertino, CA, USA,
August 21-23, 2022},
pages = {1--20},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/HCS55958.2022.9895615},
doi = {10.1109/HCS55958.2022.9895615},
timestamp = {Wed, 05 Oct 2022 17:46:21 +0200},
biburl = {https://dblp.org/rec/conf/hotchips/ShumarayevCHK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpec/ChenLHH22,
author = {Shaofen Chen and
Haiyan Lin and
Wenjin Huang and
Yihua Huang},
title = {Hardware Design and Implementation of Classic McEliece Post-Quantum
Cryptosystem Based on {FPGA}},
booktitle = {{IEEE} High Performance Extreme Computing Conference, {HPEC} 2022,
Waltham, MA, USA, September 19-23, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/HPEC55821.2022.9926295},
doi = {10.1109/HPEC55821.2022.9926295},
timestamp = {Wed, 23 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hpec/ChenLHH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic3i/KumarSMBTK22,
author = {Keshav Kumar and
Vijay Singh and
Gaurav Mishra and
Bellam Ravindra Babu and
Nandita Tripathi and
Pramod Kumar},
title = {Power-Efficient Secured Hardware Design of {AES} Algorithm on High
Performance {FPGA}},
booktitle = {5th International Conference on Contemporary Computing and Informatics,
{IC3I} 2022, Uttar Pradesh, India, December 14-16, 2022},
pages = {1634--1637},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/IC3I56241.2022.10073148},
doi = {10.1109/IC3I56241.2022.10073148},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ic3i/KumarSMBTK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icce-tw/JiangWWHF22,
author = {Ko{-}Yi Jiang and
Hsing{-}Yao Wang and
Chung{-}Bin Wu and
Yin{-}Tsung Hwang and
Chih{-}Peng Fan},
title = {Quantized Lite Convolutional Neural Network Hardware Accelerator Design
with {FPGA} for Face Direction Recognition},
booktitle = {{IEEE} International Conference on Consumer Electronics - Taiwan,
{ICCE-TW} 2022, Taipei, Taiwan, July 6-8, 2022},
pages = {61--62},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ICCE-Taiwan55306.2022.9869249},
doi = {10.1109/ICCE-TAIWAN55306.2022.9869249},
timestamp = {Fri, 09 Sep 2022 16:55:40 +0200},
biburl = {https://dblp.org/rec/conf/icce-tw/JiangWWHF22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccel/WuWL22,
author = {Chung{-}Bin Wu and
Yu{-}Hu Wu and
Yi{-}Yen Lai},
title = {{AI} Crowd Control Detection System Implemented on {FPGA} Hardware
Development Platform},
booktitle = {{IEEE} International Conference on Consumer Electronics, {ICCE} 2022,
Las Vegas, NV, USA, January 7-9, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ICCE53296.2022.9730294},
doi = {10.1109/ICCE53296.2022.9730294},
timestamp = {Wed, 23 Mar 2022 17:30:12 +0100},
biburl = {https://dblp.org/rec/conf/iccel/WuWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icic/YuMZ22,
author = {Naizhao Yu and
Xiao Min and
Liang Zhao},
editor = {De{-}Shuang Huang and
Kang{-}Hyun Jo and
Junfeng Jing and
Prashan Premaratne and
Vitoantonio Bevilacqua and
Abir Hussain},
title = {A Hardware Implementation Method of Radar Video Scanning Transformation
Based on Dual {FPGA}},
booktitle = {Intelligent Computing Theories and Application - 18th International
Conference, {ICIC} 2022, Xi'an, China, August 7-11, 2022, Proceedings,
Part {I}},
series = {Lecture Notes in Computer Science},
volume = {13393},
pages = {363--375},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-13870-6\_30},
doi = {10.1007/978-3-031-13870-6\_30},
timestamp = {Tue, 16 Aug 2022 16:15:39 +0200},
biburl = {https://dblp.org/rec/conf/icic/YuMZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icm2/MassoudASE22,
author = {Essraa Massoud and
Mohamed Abdelsalam and
Mona Safar and
M. Watheq El{-}Kharashi},
title = {A Reusable UVM-SystemC Verification Environment for Simulation, Hardware
Emulation, and {FPGA} Prototyping: Case Studies},
booktitle = {International Conference on Microelectronics, {ICM} 2022, Casablanca,
Morocco, December 4-7, 2022},
pages = {38--41},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ICM56065.2022.10005445},
doi = {10.1109/ICM56065.2022.10005445},
timestamp = {Sat, 28 Jan 2023 23:52:11 +0100},
biburl = {https://dblp.org/rec/conf/icm2/MassoudASE22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icm2/YacoubISMR22,
author = {Mohammed H. Yacoub and
Samar M. Ismail and
Lobna A. Said and
Ahmed H. Madian and
Ahmed G. Radwan},
title = {Generic Hardware Realization of {K} Nearest Neighbors on {FPGA}},
booktitle = {International Conference on Microelectronics, {ICM} 2022, Casablanca,
Morocco, December 4-7, 2022},
pages = {169--172},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ICM56065.2022.10005537},
doi = {10.1109/ICM56065.2022.10005537},
timestamp = {Sat, 28 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icm2/YacoubISMR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icppw/ShangZLZQ022,
author = {Jiangwei Shang and
Zhan Zhang and
Chuanyou Li and
Kun Zhang and
Lei Qian and
Hongwei Liu},
title = {A Software/Hardware Co-design Local Irregular Sparsity Method for
Accelerating CNNs on {FPGA}},
booktitle = {Workshop Proceedings of the 51st International Conference on Parallel
Processing, {ICPP} Workshops 2022, Bordeaux, France, 29 August 2022
- 1 September 2022},
pages = {25:1--25:7},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3547276.3548521},
doi = {10.1145/3547276.3548521},
timestamp = {Mon, 16 Jan 2023 12:03:13 +0100},
biburl = {https://dblp.org/rec/conf/icppw/ShangZLZQ022.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iecon/RobertMCG22,
author = {T{\'{e}}o Robert and
Romain Month{\'{e}}ard and
Valentin Combet and
Mathieu Gavelle},
title = {Hardware-In-the-Loop Simulation of a High Frequency Interleaved Converter
based on a Low-Cost {FPGA} Platform},
booktitle = {{IECON} 2022 - 48th Annual Conference of the {IEEE} Industrial Electronics
Society, Brussels, Belgium, October 17-20, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/IECON49645.2022.9968950},
doi = {10.1109/IECON49645.2022.9968950},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iecon/RobertMCG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iftc/YangC22,
author = {Dong Yang and
Li Chen},
editor = {Guangtao Zhai and
Jun Zhou and
Hua Yang and
Xiaokang Yang and
Ping An and
Jia Wang},
title = {FPGA-Based Hardware Implementation of {JPEG} {XS} Encoder},
booktitle = {Digital Multimedia Communications - The 19th International Forum,
{IFTC} 2022, Shanghai, China, December 8-9, 2022, Revised Selected
Papers},
series = {Communications in Computer and Information Science},
volume = {1766},
pages = {191--202},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-981-99-0856-1\_14},
doi = {10.1007/978-981-99-0856-1\_14},
timestamp = {Thu, 30 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iftc/YangC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/ClausingP22,
author = {Lennart Clausing and
Marco Platzner},
title = {ReconOS\({}^{\mbox{64}}\): {A} Hardware Operating System for Modern
Platform FPGAs with 64-Bit Support},
booktitle = {{IEEE} International Parallel and Distributed Processing Symposium,
{IPDPS} Workshops 2022, Lyon, France, May 30 - June 3, 2022},
pages = {120--127},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/IPDPSW55747.2022.00029},
doi = {10.1109/IPDPSW55747.2022.00029},
timestamp = {Mon, 08 Aug 2022 16:44:20 +0200},
biburl = {https://dblp.org/rec/conf/ipps/ClausingP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/DiaconuPBL22,
author = {Dana Diaconu and
Lucian Petrica and
Michaela Blott and
Miriam Leeser},
title = {Machine Learning Aided Hardware Resource Estimation for {FPGA} {DNN}
Implementations},
booktitle = {{IEEE} International Parallel and Distributed Processing Symposium,
{IPDPS} Workshops 2022, Lyon, France, May 30 - June 3, 2022},
pages = {77--83},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/IPDPSW55747.2022.00022},
doi = {10.1109/IPDPSW55747.2022.00022},
timestamp = {Mon, 08 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ipps/DiaconuPBL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MansooriC22,
author = {Mohammad Amir Mansoori and
Mario R. Casu},
title = {HLS-based dataflow hardware architecture for Support Vector Machine
in {FPGA}},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {41--45},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937927},
doi = {10.1109/ISCAS48785.2022.9937927},
timestamp = {Thu, 17 Nov 2022 15:59:17 +0100},
biburl = {https://dblp.org/rec/conf/iscas/MansooriC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SuzukiT22,
author = {Haruto Suzuki and
Hiroyuki Torikai},
title = {A Novel Hardware-Efficient Network of Ergodic Cellular Automaton Neuron
Models and its On-FPGA Learning},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {2266--2270},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937691},
doi = {10.1109/ISCAS48785.2022.9937691},
timestamp = {Thu, 17 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/SuzukiT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/SurajWR22,
author = {Alavala Venkata Suraj and
Shaik Mohammed Waseem and
Subir Kumar Roy},
title = {Resource Constrained Hardware Architecture for Training Deep Neural
Networks at the Edge - {FPGA} Implementation},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2022,
Warangal, India, December 18-22, 2022},
pages = {358--361},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/iSES54909.2022.00079},
doi = {10.1109/ISES54909.2022.00079},
timestamp = {Sat, 02 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ises/SurajWR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/ChenSCCYLLLY22,
author = {Yixiao Chen and
Jinfeng Song and
Shuai Chen and
Yuan Cao and
Jing Ye and
Huawei Li and
Xiaowei Li and
Xin Lou and
Enyi Yao},
title = {Exploring the high-throughput and low-delay hardware design of {SM4}
on {FPGA}},
booktitle = {19th International SoC Design Conference, {ISOCC} 2022, Gangneung-si,
Republic of Korea, October 19-22, 2022},
pages = {211--212},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISOCC56007.2022.10031393},
doi = {10.1109/ISOCC56007.2022.10031393},
timestamp = {Mon, 22 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isocc/ChenSCCYLLLY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/DasJ22,
author = {Monalisa Das and
Babita Jajodia},
title = {Hardware Design of Optimized Large Integer Schoolbook Polynomial Multiplications
on {FPGA}},
booktitle = {19th International SoC Design Conference, {ISOCC} 2022, Gangneung-si,
Republic of Korea, October 19-22, 2022},
pages = {65--66},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISOCC56007.2022.10031366},
doi = {10.1109/ISOCC56007.2022.10031366},
timestamp = {Wed, 15 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isocc/DasJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/DasJ22a,
author = {Monalisa Das and
Babita Jajodia},
title = {{FPGA} Implementation of Hybrid Karatsuba Multiplications for {NIST}
Post-Quantum Cryptographic Hardware Primitives},
booktitle = {19th International SoC Design Conference, {ISOCC} 2022, Gangneung-si,
Republic of Korea, October 19-22, 2022},
pages = {81--82},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISOCC56007.2022.10031517},
doi = {10.1109/ISOCC56007.2022.10031517},
timestamp = {Wed, 15 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isocc/DasJ22a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/ShiomiT22,
author = {Yuta Shiomi and
Hiroyuki Torikai},
title = {A hardware-efficient ergodic sequential logic neuron network for brain
prosthetic {FPGA}},
booktitle = {19th International SoC Design Conference, {ISOCC} 2022, Gangneung-si,
Republic of Korea, October 19-22, 2022},
pages = {276--277},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISOCC56007.2022.10031304},
doi = {10.1109/ISOCC56007.2022.10031304},
timestamp = {Wed, 15 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isocc/ShiomiT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/CarpegnaSC22,
author = {Alessio Carpegna and
Alessandro Savino and
Stefano Di Carlo},
title = {Spiker: an FPGA-optimized Hardware accelerator for Spiking Neural
Networks},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2022, Nicosia,
Cyprus, July 4-6, 2022},
pages = {14--19},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISVLSI54635.2022.00016},
doi = {10.1109/ISVLSI54635.2022.00016},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/CarpegnaSC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LiLXW22,
author = {Binjing Li and
Siyuan Lu and
Keli Xie and
Zhongfeng Wang},
title = {Accelerating {NLP} Tasks on {FPGA} with Compressed {BERT} and a Hardware-Oriented
Early Exit Method},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2022, Nicosia,
Cyprus, July 4-6, 2022},
pages = {410--413},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISVLSI54635.2022.00092},
doi = {10.1109/ISVLSI54635.2022.00092},
timestamp = {Fri, 21 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/LiLXW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LuJJHS22,
author = {Qing Lu and
Weiwen Jiang and
Meng Jiang and
Jingtong Hu and
Yiyu Shi},
title = {Hardware/Software Co-Exploration for Graph Neural Architectures on
FPGAs},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2022, Nicosia,
Cyprus, July 4-6, 2022},
pages = {358--362},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISVLSI54635.2022.00079},
doi = {10.1109/ISVLSI54635.2022.00079},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LuJJHS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/MatrangoloMNO22,
author = {Paul{-}Antoine Matrangolo and
C{\'{e}}dric Marchand and
David Navarro and
Ian O'Connor},
title = {Hardware Emulation of FeFET On {FPGA}},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2022, Nicosia,
Cyprus, July 4-6, 2022},
pages = {380--385},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISVLSI54635.2022.00085},
doi = {10.1109/ISVLSI54635.2022.00085},
timestamp = {Tue, 25 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/MatrangoloMNO22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwssip/IbroM22a,
author = {Marsida Ibro and
Galia Marinova},
title = {Hardware Encryption logic on {FPGA} and Power Consumption},
booktitle = {29th International Conference on Systems, Signals and Image Processing,
{IWSSIP} 2022, Sofia, Bulgaria, June 1-3, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/IWSSIP55020.2022.9854482},
doi = {10.1109/IWSSIP55020.2022.9854482},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwssip/IbroM22a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lascas/YashTJ22,
author = {Palak Yash and
Mansi Thakare and
Babita Jajodia},
title = {Optimized Hardware Implementation of Vedic Binary Multiplier using
Nikhilam Sutra on {FPGA}},
booktitle = {13th {IEEE} Latin America Symposium on Circuits and System, {LASCAS}
2022, Puerto Varas, Chile, March 1-4, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/LASCAS53948.2022.9789063},
doi = {10.1109/LASCAS53948.2022.9789063},
timestamp = {Mon, 13 Jun 2022 16:53:37 +0200},
biburl = {https://dblp.org/rec/conf/lascas/YashTJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/RR22,
author = {Soujanya S. R and
Madhav Rao},
title = {Hardware characterization of Integer-Net based seizure detection models
on {FPGA}},
booktitle = {15th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2022, Penang, Malaysia, December 19-22, 2022},
pages = {224--231},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MCSoC57363.2022.00043},
doi = {10.1109/MCSOC57363.2022.00043},
timestamp = {Thu, 26 Jan 2023 11:35:12 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/RR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/SunFW22,
author = {Wei{-}Che Sun and
Chih{-}Peng Fan and
Chung{-}Bin Wu},
title = {Design and {FPGA} Implementation of Lite Convolutional Neural Network
Based Hardware Accelerator for Ocular Biometrics Recognition Technology},
booktitle = {15th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2022, Penang, Malaysia, December 19-22, 2022},
pages = {278--283},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MCSoC57363.2022.00051},
doi = {10.1109/MCSOC57363.2022.00051},
timestamp = {Thu, 26 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/SunFW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/meco/AftowiczLL22,
author = {Marcin Aftowicz and
Kai Lehniger and
Peter Langendoerfer},
title = {Scalable {FPGA} Hardware Accelerator for {SVM} Inference},
booktitle = {11th Mediterranean Conference on Embedded Computing, {MECO} 2022,
Budva, Montenegro, June 7-10, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MECO55406.2022.9797110},
doi = {10.1109/MECO55406.2022.9797110},
timestamp = {Fri, 01 Jul 2022 09:09:18 +0200},
biburl = {https://dblp.org/rec/conf/meco/AftowiczLL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/prime/SangiovanniSC22,
author = {Mario Andrea Sangiovanni and
Fanny Spagnolo and
Pasquale Corsonello},
title = {Hardware-Oriented Multi-Exposure Fusion Approach for Real-Time Video
Processing on {FPGA}},
booktitle = {17th Conference on Ph.D Research in Microelectronics and Electronics,
{PRIME} 2022, Villasimius, SU, Italy, June 12-15, 2022},
pages = {129--132},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/PRIME55000.2022.9816793},
doi = {10.1109/PRIME55000.2022.9816793},
timestamp = {Wed, 03 Aug 2022 15:12:51 +0200},
biburl = {https://dblp.org/rec/conf/prime/SangiovanniSC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pris2/LiuD022,
author = {Xiaojuan Liu and
Jietao Diao and
Nan Li},
title = {{FPGA} hardware implementation of Q-learning algorithm with low resource
consumption},
booktitle = {{PRIS} 2022: 4th International Conference on Pattern Recognition and
Intelligent Systems, Wuhan, China, July 29 - 31, 2022},
pages = {8--13},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3549179.3549181},
doi = {10.1145/3549179.3549181},
timestamp = {Tue, 23 Aug 2022 16:09:05 +0200},
biburl = {https://dblp.org/rec/conf/pris2/LiuD022.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rev/CristeaB22,
author = {Andreea Cristina Suiu Cristea and
Alexandra Balan},
editor = {Michael E. Auer and
Samir Abou El{-}Seoud and
Omar H. Karam},
title = {{AES} Hardware Implementation Based on {FPGA} with Improved Throughput},
booktitle = {Artificial Intelligence and Online Engineering - Proceedings of the
19th International Conference on Remote Engineering and Virtual Instrumentation,
British University, Cairo, Egypt, 28 February - 2 March 2022},
series = {Lecture Notes in Networks and Systems},
volume = {524},
pages = {41--50},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-17091-1\_5},
doi = {10.1007/978-3-031-17091-1\_5},
timestamp = {Tue, 18 Oct 2022 15:09:37 +0200},
biburl = {https://dblp.org/rec/conf/rev/CristeaB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rivf/NghiT22,
author = {Huynh Phuc Nghi and
Tran Ngoc Thinh},
title = {A CNN-Based Vehicle Identification Solution in Parking System With
Hardware Accelerator on {FPGA}},
booktitle = {{RIVF} International Conference on Computing and Communication Technologies,
{RIVF} 2022, Ho Chi Minh City, Vietnam, December 20-22, 2022},
pages = {518--523},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/RIVF55975.2022.10013847},
doi = {10.1109/RIVF55975.2022.10013847},
timestamp = {Mon, 30 Jan 2023 14:34:17 +0100},
biburl = {https://dblp.org/rec/conf/rivf/NghiT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/spa/SzolcK22,
author = {Hubert Szolc and
Tomasz Kryjak},
title = {Hardware-in-the-loop simulation of a {UAV} autonomous landing algorithm
implemented in SoC {FPGA}},
booktitle = {Signal Processing: Algorithms, Architectures, Arrangements, and Applications
{SPA} 2022, Poznan, Poland, September 21-22, 2022},
pages = {135--140},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.23919/SPA53010.2022.9927847},
doi = {10.23919/SPA53010.2022.9927847},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/spa/SzolcK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2201-06993,
author = {Alessio Carpegna and
Alessandro Savino and
Stefano Di Carlo},
title = {FPGA-optimized Hardware acceleration for Spiking Neural Networks},
journal = {CoRR},
volume = {abs/2201.06993},
year = {2022},
url = {https://arxiv.org/abs/2201.06993},
eprinttype = {arXiv},
eprint = {2201.06993},
timestamp = {Fri, 21 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2201-06993.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2201-09670,
author = {Yu Wang and
Wujun Xie and
Haochang Chen and
David Day{-}Uei Li},
title = {Low hardware consumption, resolution-configurable Gray code oscillator
time-to-digital converters implemented in 16nm, 20nm and 28nm FPGAs},
journal = {CoRR},
volume = {abs/2201.09670},
year = {2022},
url = {https://arxiv.org/abs/2201.09670},
eprinttype = {arXiv},
eprint = {2201.09670},
timestamp = {Tue, 01 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2201-09670.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2207-04625,
author = {Yashael Faith Arthanto and
David Ojika and
Joo{-}Young Kim},
title = {{FSHMEM:} Supporting Partitioned Global Address Space on FPGAs for
Large-Scale Hardware Acceleration Infrastructure},
journal = {CoRR},
volume = {abs/2207.04625},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2207.04625},
doi = {10.48550/ARXIV.2207.04625},
eprinttype = {arXiv},
eprint = {2207.04625},
timestamp = {Wed, 05 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2207-04625.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2207-12198,
author = {Hubert Szolc and
Tomasz Kryjak},
title = {Hardware-in-the-loop simulation of a {UAV} autonomous landing algorithm
implemented in SoC {FPGA}},
journal = {CoRR},
volume = {abs/2207.12198},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2207.12198},
doi = {10.48550/ARXIV.2207.12198},
eprinttype = {arXiv},
eprint = {2207.12198},
timestamp = {Mon, 01 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2207-12198.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2208-03646,
author = {Hongwu Peng and
Shaoyi Huang and
Shiyang Chen and
Bingbing Li and
Tong Geng and
Ang Li and
Weiwen Jiang and
Wujie Wen and
Jinbo Bi and
Hang Liu and
Caiwen Ding},
title = {A Length Adaptive Algorithm-Hardware Co-design of Transformer on {FPGA}
Through Sparse Attention and Dynamic Pipelining},
journal = {CoRR},
volume = {abs/2208.03646},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2208.03646},
doi = {10.48550/ARXIV.2208.03646},
eprinttype = {arXiv},
eprint = {2208.03646},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2208-03646.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2210-09481,
author = {Ramchander Rao Bhaskara and
Manoranjan Majji},
title = {{FPGA} Hardware Acceleration for Feature-Based Relative Navigation
Applications},
journal = {CoRR},
volume = {abs/2210.09481},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2210.09481},
doi = {10.48550/ARXIV.2210.09481},
eprinttype = {arXiv},
eprint = {2210.09481},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2210-09481.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2212-09460,
author = {Mohamed Alshemi and
Sherif M. Saif and
Mohamed Taher},
title = {Hardware Acceleration of Lane Detection Algorithm: {A} {GPU} Versus
{FPGA} Comparison},
journal = {CoRR},
volume = {abs/2212.09460},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2212.09460},
doi = {10.48550/ARXIV.2212.09460},
eprinttype = {arXiv},
eprint = {2212.09460},
timestamp = {Tue, 03 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2212-09460.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/hal/Baumela21,
author = {Thomas Baumela},
title = {Integrating devices in {FPGA} using an end-to-end hardware/software
co-designedmessage-based approach. (Int{\'{e}}gration mat{\'{e}}riel/logiciel
sur {FPGA} {\`{a}} l'aide d'une strat{\'{e}}gie de communication
par messages)},
school = {Grenoble Alpes University, France},
year = {2021},
url = {https://tel.archives-ouvertes.fr/tel-03259401},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/hal/Baumela21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/it/Stornaiuolo21,
author = {Luca Stornaiuolo},
title = {Hardware/software co-design for scientific computing and convolutional
neural networks on FPGA-based embedded architectures},
school = {Polytechnic University of Milan, Italy},
year = {2021},
url = {https://hdl.handle.net/10589/171136},
timestamp = {Thu, 20 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/it/Stornaiuolo21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/us/Huang21a,
author = {Sitao Huang},
title = {High-efficiency and high-usability heterogeneous hardware acceleration
with FPGAs},
school = {University of Illinois Urbana-Champaign, {USA}},
year = {2021},
url = {https://hdl.handle.net/2142/113066},
timestamp = {Thu, 07 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/us/Huang21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/El-MaksoudEKM21,
author = {Ahmed J. Abd El{-}Maksoud and
Mohamed Ebbed and
Ahmed H. Khalil and
Hassan Mostafa},
title = {Power Efficient Design of High-Performance Convolutional Neural Networks
Hardware Accelerator on {FPGA:} {A} Case Study With GoogLeNet},
journal = {{IEEE} Access},
volume = {9},
pages = {151897--151911},
year = {2021},
url = {https://doi.org/10.1109/ACCESS.2021.3126838},
doi = {10.1109/ACCESS.2021.3126838},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/El-MaksoudEKM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/GomezNDG21,
author = {Jorge Torres G{\'{o}}mez and
Yannelys Virginia Jerez Naranjo and
Falko Dressler and
M. Julia Fern{\'{a}}ndez{-}Getino Garc{\'{\i}}a},
title = {Undergraduate Curriculum to Teach and Provide Research Skills on Hardware
Design for {SDR} Applications in {FPGA} Technology},
journal = {{IEEE} Access},
volume = {9},
pages = {93967--93975},
year = {2021},
url = {https://doi.org/10.1109/ACCESS.2021.3093072},
doi = {10.1109/ACCESS.2021.3093072},
timestamp = {Wed, 16 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/GomezNDG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/Huang21a,
author = {Chun{-}Hsian Huang},
title = {An FPGA-Based Hardware/Software Design Using Binarized Neural Networks
for Agricultural Applications: {A} Case Study},
journal = {{IEEE} Access},
volume = {9},
pages = {26523--26531},
year = {2021},
url = {https://doi.org/10.1109/ACCESS.2021.3058110},
doi = {10.1109/ACCESS.2021.3058110},
timestamp = {Wed, 07 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/Huang21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/KhanLH21,
author = {Safiullah Khan and
Wai{-}Kong Lee and
Seong Oun Hwang},
title = {A Flexible Gimli Hardware Implementation in {FPGA} and Its Application
to {RFID} Authentication Protocols},
journal = {{IEEE} Access},
volume = {9},
pages = {105327--105340},
year = {2021},
url = {https://doi.org/10.1109/ACCESS.2021.3100104},
doi = {10.1109/ACCESS.2021.3100104},
timestamp = {Thu, 12 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/KhanLH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/YouW21,
author = {Weijie You and
Chang Wu},
title = {{RSNN:} {A} Software/Hardware Co-Optimized Framework for Sparse Convolutional
Neural Networks on FPGAs},
journal = {{IEEE} Access},
volume = {9},
pages = {949--960},
year = {2021},
url = {https://doi.org/10.1109/ACCESS.2020.3047144},
doi = {10.1109/ACCESS.2020.3047144},
timestamp = {Sat, 09 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/YouW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/algorithms/BhattiG21,
author = {Faraz Bhatti and
Thomas Greiner},
title = {Design of an {FPGA} Hardware Optimizing the Performance and Power
Consumption of a Plenoptic Camera Depth Estimation Algorithm},
journal = {Algorithms},
volume = {14},
number = {7},
pages = {215},
year = {2021},
url = {https://doi.org/10.3390/a14070215},
doi = {10.3390/A14070215},
timestamp = {Wed, 01 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/algorithms/BhattiG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/asc/OrtizMBPMM21,
author = {Alexandro Ortiz and
Efrain Mendez and
David Balderas and
Pedro Ponce and
Israel Macias and
Arturo Molina},
title = {Hardware implementation of metaheuristics through LabVIEW {FPGA}},
journal = {Appl. Soft Comput.},
volume = {113},
number = {Part},
pages = {107908},
year = {2021},
url = {https://doi.org/10.1016/j.asoc.2021.107908},
doi = {10.1016/J.ASOC.2021.107908},
timestamp = {Sat, 29 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/asc/OrtizMBPMM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/elektrik/KashifC21,
author = {Muhammad Kashif and
Ihsan {\c{C}}i{\c{c}}ek},
title = {Field-programmable gate array {(FPGA)} hardware design and implementation
of a new area efficient elliptic curve crypto-processor},
journal = {Turkish J. Electr. Eng. Comput. Sci.},
volume = {29},
number = {4},
pages = {2127--2139},
year = {2021},
url = {https://doi.org/10.3906/elk-2008-8},
doi = {10.3906/ELK-2008-8},
timestamp = {Sat, 10 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/elektrik/KashifC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/UllahNK21,
author = {Salim Ullah and
Tuan Duy Anh Nguyen and
Akash Kumar},
title = {Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware
Accelerators},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {13},
number = {2},
pages = {41--44},
year = {2021},
url = {https://doi.org/10.1109/LES.2020.2995053},
doi = {10.1109/LES.2020.2995053},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/UllahNK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijhpsa/Adam21,
author = {George K. Adam},
title = {Multithreading on reconfigurable hardware: a performance evaluation
approach of a multicore {FPGA} architecture},
journal = {Int. J. High Perform. Syst. Archit.},
volume = {10},
number = {2},
pages = {105--116},
year = {2021},
url = {https://doi.org/10.1504/IJHPSA.2021.119154},
doi = {10.1504/IJHPSA.2021.119154},
timestamp = {Tue, 07 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijhpsa/Adam21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijin/LeelavathiSV21,
author = {G. Leelavathi and
K. Shaila and
K. R. Venugopal},
title = {Hardware performance analysis of {RSA} cryptosystems on {FPGA} for
wireless sensor nodes},
journal = {Int. J. Intell. Networks},
volume = {2},
pages = {184--194},
year = {2021},
url = {https://doi.org/10.1016/j.ijin.2021.09.008},
doi = {10.1016/J.IJIN.2021.09.008},
timestamp = {Mon, 29 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijin/LeelavathiSV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijon/HuangYRD21,
author = {Hui Huang and
Jing Yang and
Hai{-}Jun Rong and
Shaoyi Du},
title = {A generic FPGA-based hardware architecture for recursive least mean
p-power extreme learning machine},
journal = {Neurocomputing},
volume = {456},
pages = {421--435},
year = {2021},
url = {https://doi.org/10.1016/j.neucom.2021.05.069},
doi = {10.1016/J.NEUCOM.2021.05.069},
timestamp = {Fri, 06 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijon/HuangYRD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/VuNN21,
author = {Hoang Gia Vu and
Takashi Nakada and
Yasuhiko Nakashima},
title = {Efficient hardware task migration for heterogeneous {FPGA} computing
using HDL-based checkpointing},
journal = {Integr.},
volume = {77},
pages = {180--192},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.11.011},
doi = {10.1016/J.VLSI.2020.11.011},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/VuNN21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jaiscr/KopczynskiG21,
author = {Maciej Kopczynski and
Tomasz Grzes},
title = {Hardware Rough Set Processor Parallel Architecture in {FPGA} for Finding
Core in Big Datasets},
journal = {J. Artif. Intell. Soft Comput. Res.},
volume = {11},
number = {2},
pages = {99--110},
year = {2021},
url = {https://doi.org/10.2478/jaiscr-2021-0007},
doi = {10.2478/JAISCR-2021-0007},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jaiscr/KopczynskiG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/GafsiAHMM21,
author = {Mohamed Gafsi and
Nessrine Abbassi and
Mohamed Ali Hajjaji and
Jihene Malek and
Abdellatif Mtibaa},
title = {Xilinx Zynq {FPGA} for Hardware Implementation of a Chaos-Based Cryptosystem
for Real-Time Image Protection},
journal = {J. Circuits Syst. Comput.},
volume = {30},
number = {11},
pages = {2150204:1--2150204:26},
year = {2021},
url = {https://doi.org/10.1142/S0218126621502042},
doi = {10.1142/S0218126621502042},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcsc/GafsiAHMM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrtip/BoukhtacheBGB21,
author = {Seyfeddine Boukhtache and
Beno{\^{\i}}t Blaysat and
Michel Gr{\'{e}}diac and
Fran{\c{c}}ois Berry},
title = {FPGA-based architecture for bi-cubic interpolation: the best trade-off
between precision and hardware resource consumption},
journal = {J. Real Time Image Process.},
volume = {18},
number = {3},
pages = {901--911},
year = {2021},
url = {https://doi.org/10.1007/s11554-020-01035-1},
doi = {10.1007/S11554-020-01035-1},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrtip/BoukhtacheBGB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/HanL21a,
author = {Dong Han and
Gang Li},
title = {Development of smart english classroom system based on {FPGA} software
and hardware co-simulation test},
journal = {Microprocess. Microsystems},
volume = {81},
pages = {103774},
year = {2021},
url = {https://doi.org/10.1016/j.micpro.2020.103774},
doi = {10.1016/J.MICPRO.2020.103774},
timestamp = {Fri, 21 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/HanL21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/JinJ21,
author = {Shujiao Jin and
Hu Jin},
title = {Optimization of Motion Estimation Algorithm Based on {FPGA} Hardware
System and Video Tracking},
journal = {Microprocess. Microsystems},
volume = {82},
pages = {103867},
year = {2021},
url = {https://doi.org/10.1016/j.micpro.2021.103867},
doi = {10.1016/J.MICPRO.2021.103867},
timestamp = {Tue, 25 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/JinJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/JingX21,
author = {Hu Jing and
Xing Xiaoqiong},
title = {Sports image detection based on {FPGA} hardware system and particle
swarm algorithm},
journal = {Microprocess. Microsystems},
volume = {80},
pages = {103348},
year = {2021},
url = {https://doi.org/10.1016/j.micpro.2020.103348},
doi = {10.1016/J.MICPRO.2020.103348},
timestamp = {Fri, 19 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/JingX21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mta/GuptaJVKK21,
author = {Namit Gupta and
Arpit Jain and
Kunwar Singh Vaisla and
Adesh Kumar and
Rajeev Kumar},
title = {Performance analysis of {DSDV} and {OLSR} wireless sensor network
routing protocols using {FPGA} hardware and machine learning},
journal = {Multim. Tools Appl.},
volume = {80},
number = {14},
pages = {22301--22319},
year = {2021},
url = {https://doi.org/10.1007/s11042-021-10820-4},
doi = {10.1007/S11042-021-10820-4},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mta/GuptaJVKK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/nca/ShymkovychTK21,
author = {Volodymyr M. Shymkovych and
Sergii Telenyk and
Petro I. Kravets},
title = {Hardware implementation of radial-basis neural networks with Gaussian
activation functions on {FPGA}},
journal = {Neural Comput. Appl.},
volume = {33},
number = {15},
pages = {9467--9479},
year = {2021},
url = {https://doi.org/10.1007/s00521-021-05706-3},
doi = {10.1007/S00521-021-05706-3},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/nca/ShymkovychTK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/npl/SateesanSGV21,
author = {Arish Sateesan and
Sharad Sinha and
Smitha K. G. and
A. P. Vinod},
title = {A Survey of Algorithmic and Hardware Optimization Techniques for Vision
Convolutional Neural Networks on FPGAs},
journal = {Neural Process. Lett.},
volume = {53},
number = {3},
pages = {2331--2377},
year = {2021},
url = {https://doi.org/10.1007/s11063-021-10458-1},
doi = {10.1007/S11063-021-10458-1},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/npl/SateesanSGV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/queue/Mattioli21,
author = {Michael Mattioli},
title = {FPGAs in Client Compute Hardware: Despite certain challenges, FPGAs
provide security and performance benefits over ASICs},
journal = {{ACM} Queue},
volume = {19},
number = {6},
pages = {66--88},
year = {2021},
url = {https://doi.org/10.1145/3512327},
doi = {10.1145/3512327},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/queue/Mattioli21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/remotesensing/RapuanoMPDFGF21,
author = {Emilio Rapuano and
Gabriele Meoni and
Tommaso Pacini and
Gianmarco Dinelli and
Gianluca Furano and
Gianluca Giuffrida and
Luca Fanucci},
title = {An FPGA-Based Hardware Accelerator for CNNs Inference on Board Satellites:
Benchmarking with Myriad 2-Based Solution for the CloudScout Case
Study},
journal = {Remote. Sens.},
volume = {13},
number = {8},
pages = {1518},
year = {2021},
url = {https://doi.org/10.3390/rs13081518},
doi = {10.3390/RS13081518},
timestamp = {Wed, 26 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/remotesensing/RapuanoMPDFGF21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tches/XingL21,
author = {Yufei Xing and
Shuguo Li},
title = {A Compact Hardware Implementation of CCA-Secure Key Exchange Mechanism
{CRYSTALS-KYBER} on {FPGA}},
journal = {{IACR} Trans. Cryptogr. Hardw. Embed. Syst.},
volume = {2021},
number = {2},
pages = {328--356},
year = {2021},
url = {https://doi.org/10.46586/tches.v2021.i2.328-356},
doi = {10.46586/TCHES.V2021.I2.328-356},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tches/XingL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/SahaS21,
author = {Debasri Saha and
Susmita Sur{-}Kolay},
title = {Minimization of {WCRT} with Recovery Assurance from Hardware Trojans
for Tasks on FPGA-based Cloud},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {20},
number = {1},
pages = {1:1--1:25},
year = {2021},
url = {https://doi.org/10.1145/3409479},
doi = {10.1145/3409479},
timestamp = {Tue, 09 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tecs/SahaS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/ZhangWZTH21,
author = {Xinyi Zhang and
Yawen Wu and
Peipei Zhou and
Xulong Tang and
Jingtong Hu},
title = {Algorithm-hardware Co-design of Attention Mechanism on {FPGA} Devices},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {20},
number = {5s},
pages = {71:1--71:24},
year = {2021},
url = {https://doi.org/10.1145/3477002},
doi = {10.1145/3477002},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/ZhangWZTH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tetc/TsigkanosKTP21,
author = {Antonis Tsigkanos and
Nektarios Kranitis and
George Theodorou and
Antonis M. Paschalis},
title = {A 3.3 Gbps {CCSDS} 123.0-B-1 Multispectral {\&} Hyperspectral
Image Compression Hardware Accelerator on a Space-Grade {SRAM} {FPGA}},
journal = {{IEEE} Trans. Emerg. Top. Comput.},
volume = {9},
number = {1},
pages = {90--103},
year = {2021},
url = {https://doi.org/10.1109/TETC.2018.2854412},
doi = {10.1109/TETC.2018.2854412},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tetc/TsigkanosKTP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tie/DaiKQC21,
author = {Xunhua Dai and
Chenxu Ke and
Quan Quan and
Kai{-}Yuan Cai},
title = {Simulation Credibility Assessment Methodology With FPGA-based Hardware-in-the-Loop
Platform},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {68},
number = {4},
pages = {3282--3291},
year = {2021},
url = {https://doi.org/10.1109/TIE.2020.2982122},
doi = {10.1109/TIE.2020.2982122},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tie/DaiKQC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tie/HosseinabadiBS21,
author = {Amir Hossein Hadi Hosseinabadi and
David G. Black and
Septimiu E. Salcudean},
title = {Ultra Low-Noise FPGA-Based Six-Axis Optical Force-Torque Sensor: Hardware
and Software},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {68},
number = {10},
pages = {10207--10217},
year = {2021},
url = {https://doi.org/10.1109/TIE.2020.3021648},
doi = {10.1109/TIE.2020.3021648},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tie/HosseinabadiBS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tsg/DuanHD21,
author = {Tong Duan and
Zhen Huang and
Venkata Dinavahi},
title = {{RTCE:} Real-Time Co-Emulation Framework for EMT-Based Power System
and Communication Network on FPGA-MPSoC Hardware Architecture},
journal = {{IEEE} Trans. Smart Grid},
volume = {12},
number = {3},
pages = {2544--2553},
year = {2021},
url = {https://doi.org/10.1109/TSG.2020.3039259},
doi = {10.1109/TSG.2020.3039259},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tsg/DuanHD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BoukhtacheBGB21,
author = {Seyfeddine Boukhtache and
Beno{\^{\i}}t Blaysat and
Michel Gr{\'{e}}diac and
Fran{\c{c}}ois Berry},
title = {Alternatives to Bicubic Interpolation Considering {FPGA} Hardware
Resource Consumption},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {247--258},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3032888},
doi = {10.1109/TVLSI.2020.3032888},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BoukhtacheBGB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEssd/BouguezziFS21a,
author = {Safa Bouguezzi and
Hassene Faiedh and
Chokri Souani},
title = {Hardware Implementation of Tanh Exponential Activation Function using
{FPGA}},
booktitle = {18th International Multi-Conference on Systems, Signals {\&} Devices,
{SSD} 2021, Monastir, Tunisia, March 22-25, 2021},
pages = {1020--1025},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SSD52085.2021.9429506},
doi = {10.1109/SSD52085.2021.9429506},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/IEEEssd/BouguezziFS21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEssd/MaraouiMBAKM21,
author = {Amna Maraoui and
Seifeddine Messaoud and
Soulef Bouaafia and
Ahmed Chiheb Ammari and
Lazhar Khriji and
Mohsen Machhout},
title = {{PYNQ} {FPGA} Hardware implementation of LeNet-5-Based Traffic Sign
Recognition Application},
booktitle = {18th International Multi-Conference on Systems, Signals {\&} Devices,
{SSD} 2021, Monastir, Tunisia, March 22-25, 2021},
pages = {1004--1009},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SSD52085.2021.9429480},
doi = {10.1109/SSD52085.2021.9429480},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/IEEEssd/MaraouiMBAKM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aicas/WangCX21,
author = {Hao Wang and
Shan Cao and
Shugong Xu},
title = {A Real-Time Face Recognition System by Efficient Hardware-Software
Co-Design on {FPGA} SoCs},
booktitle = {3rd {IEEE} International Conference on Artificial Intelligence Circuits
and Systems, {AICAS} 2021, Washington, DC, USA, June 6-9, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/AICAS51828.2021.9458462},
doi = {10.1109/AICAS51828.2021.9458462},
timestamp = {Fri, 25 Jun 2021 11:56:02 +0200},
biburl = {https://dblp.org/rec/conf/aicas/WangCX21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/applepies/CominoPRF21,
author = {Corrado Comino and
Tommaso Pacini and
Emilio Rapuano and
Luca Fanucci},
editor = {Sergio Saponara and
Alessandro De Gloria},
title = {Design and Implementation of an FPGA-Based {CNN} Hardware Accelerator
Using Partial Reconfigurability: The CloudScout Case Study},
booktitle = {Applications in Electronics Pervading Industry, Environment and Society
- {APPLEPIES} 2021},
series = {Lecture Notes in Electrical Engineering},
volume = {866},
pages = {187--193},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-030-95498-7\_26},
doi = {10.1007/978-3-030-95498-7\_26},
timestamp = {Tue, 12 Apr 2022 11:38:04 +0200},
biburl = {https://dblp.org/rec/conf/applepies/CominoPRF21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/applepies/FlorianVGCMCCC21,
author = {Werner Florian and
Bruno Valinoti and
Luis Guillermo Garc{\'{\i}}a and
Marcos Cervetto and
Edgardo Marchi and
Maria Liz Crespo and
Sergio Carrato and
Andres Cicuttin},
editor = {Sergio Saponara and
Alessandro De Gloria},
title = {An Open-Source Hardware/Software Architecture for Remote Control of
SoC-FPGA Based Systems},
booktitle = {Applications in Electronics Pervading Industry, Environment and Society
- {APPLEPIES} 2021},
series = {Lecture Notes in Electrical Engineering},
volume = {866},
pages = {69--75},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-030-95498-7\_10},
doi = {10.1007/978-3-030-95498-7\_10},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/applepies/FlorianVGCMCCC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/WangL21,
author = {Yu Wang and
Peng Li},
title = {Algorithm and Hardware Co-Design for {FPGA} Acceleration of Hamiltonian
Monte Carlo Based No-U-Turn Sampler},
booktitle = {32nd {IEEE} International Conference on Application-specific Systems,
Architectures and Processors, {ASAP} 2021, Virtual Conference, USA,
July 7-9, 2021},
pages = {9--16},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ASAP52443.2021.00009},
doi = {10.1109/ASAP52443.2021.00009},
timestamp = {Sat, 18 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asap/WangL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/BaiFSKZ21,
author = {Jinyu Bai and
Yunqian Fan and
Sifan Sun and
Wang Kang and
Weisheng Zhao},
title = {Tiny neural network search and implementation for embedded {FPGA:}
a software-hardware co-design approach},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2021, Busan,
Korea, Republic of, November 7-10, 2021},
pages = {1--3},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/A-SSCC53895.2021.9634749},
doi = {10.1109/A-SSCC53895.2021.9634749},
timestamp = {Mon, 02 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asscc/BaiFSKZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ccgrid/WangFLT00D21,
author = {Yuke Wang and
Boyuan Feng and
Gushu Li and
Georgios Tzimpragos and
Lei Deng and
Yuan Xie and
Yufei Ding},
editor = {Laurent Lef{\`{e}}vre and
Stacy Patterson and
Young Choon Lee and
Haiying Shen and
Shashikant Ilager and
Mohammad Goudarzi and
Adel Nadjaran Toosi and
Rajkumar Buyya},
title = {TiAcc: Triangle-inequality based Hardware Accelerator for K-means
on FPGAs},
booktitle = {21st {IEEE/ACM} International Symposium on Cluster, Cloud and Internet
Computing, CCGrid 2021, Melbourne, Australia, May 10-13, 2021},
pages = {133--142},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/CCGrid51090.2021.00023},
doi = {10.1109/CCGRID51090.2021.00023},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ccgrid/WangFLT00D21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/KreddigCMS21,
author = {Arne Kreddig and
Simon Conrady and
Manu Manuel and
Walter Stechele},
editor = {Francesco Leporati and
Salvatore Vitabile and
Amund Skavhaug},
title = {A Framework for Hardware-Accelerated Design Space Exploration for
Approximate Computing on {FPGA}},
booktitle = {24th Euromicro Conference on Digital System Design, {DSD} 2021, Virtual
Event / Palermo, Sicily, Italy, September 1-3, 2021},
pages = {1--8},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DSD53832.2021.00010},
doi = {10.1109/DSD53832.2021.00010},
timestamp = {Mon, 07 Nov 2022 07:58:07 +0100},
biburl = {https://dblp.org/rec/conf/dsd/KreddigCMS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/KhouyganiMBC21,
author = {Verjina Torosian Khouygani and
Shahnam Mirzaei and
Christian Beck and
Debi Prasad Choudhary},
title = {An {FPGA} Based Hardware Accelerated Framework for Solar Spectra Matching
with Parameterized Matched Filter {IP} Core},
booktitle = {29th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2021, Orlando, FL, USA, May 9-12, 2021},
pages = {278},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/FCCM51124.2021.00063},
doi = {10.1109/FCCM51124.2021.00063},
timestamp = {Mon, 07 Jun 2021 17:13:01 +0200},
biburl = {https://dblp.org/rec/conf/fccm/KhouyganiMBC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fie/LiNMQ21,
author = {Ying Li and
Jianwei Niu and
Simbarashe Matutu and
Qianben Qi},
title = {Teaching practice reforms towards software-hardware collaboration
in computer system ability training-Taking {FPGA} Design course as
an example},
booktitle = {{IEEE} Frontiers in Education Conference, {FIE} 2021, Lincoln, NE,
USA, October 13-16, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/FIE49875.2021.9637408},
doi = {10.1109/FIE49875.2021.9637408},
timestamp = {Wed, 29 Dec 2021 09:45:46 +0100},
biburl = {https://dblp.org/rec/conf/fie/LiNMQ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/NgoTMP21,
author = {Duc{-}Minh Ngo and
Andriy Temko and
Colin C. Murphy and
Emanuel M. Popovici},
title = {{FPGA} Hardware Acceleration Framework for Anomaly-based Intrusion
Detection System in IoT},
booktitle = {31st International Conference on Field-Programmable Logic and Applications,
{FPL} 2021, Dresden, Germany, August 30 - Sept. 3, 2021},
pages = {69--75},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/FPL53798.2021.00020},
doi = {10.1109/FPL53798.2021.00020},
timestamp = {Mon, 18 Oct 2021 17:08:51 +0200},
biburl = {https://dblp.org/rec/conf/fpl/NgoTMP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/AttiaB21,
author = {Sameh Attia and
Vaughn Betz},
title = {StateLink: {FPGA} System Debugging via Flexible Simulation/Hardware
Integration},
booktitle = {International Conference on Field-Programmable Technology, {(IC)FPT}
2021, Auckland, New Zealand, December 6-10, 2021},
pages = {1--10},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICFPT52863.2021.9609846},
doi = {10.1109/ICFPT52863.2021.9609846},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/AttiaB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/SuhMNVKCS21,
author = {Han{-}Sok Suh and
Jian Meng and
Ty Nguyen and
Shreyas K. Venkataramanaiah and
Vijay Kumar and
Yu Cao and
Jae{-}sun Seo},
title = {Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection
on Resource-Constrained {FPGA}},
booktitle = {International Conference on Field-Programmable Technology, {(IC)FPT}
2021, Auckland, New Zealand, December 6-10, 2021},
pages = {1--9},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICFPT52863.2021.9609840},
doi = {10.1109/ICFPT52863.2021.9609840},
timestamp = {Fri, 03 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/SuhMNVKCS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/ZhangFO21,
author = {Nathan Zhang and
Matthew Feldman and
Kunle Olukotun},
title = {High performance lattice regression on FPGAs via a high level hardware
description language},
booktitle = {International Conference on Field-Programmable Technology, {(IC)FPT}
2021, Auckland, New Zealand, December 6-10, 2021},
pages = {1--10},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICFPT52863.2021.9609893},
doi = {10.1109/ICFPT52863.2021.9609893},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/ZhangFO21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icaiic/MunKK21a,
author = {Gwonhan Mun and
Hee Wook Kim and
Daeho Kim},
title = {{CNPC} deinterleaver implementation to increase hardware logic utilization
on {FPGA}},
booktitle = {International Conference on Artificial Intelligence in Information
and Communication, {ICAIIC} 2021, Jeju Island, South Korea, April
13-16, 2021},
pages = {385--389},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICAIIC51459.2021.9415239},
doi = {10.1109/ICAIIC51459.2021.9415239},
timestamp = {Sat, 09 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icaiic/MunKK21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icassp/BhattiG21,
author = {Faraz Bhatti and
Thomas Greiner},
title = {{FPGA} Hardware Design for Plenoptic 3D Image Processing Algorithm
Targeting a Mobile Application},
booktitle = {{IEEE} International Conference on Acoustics, Speech and Signal Processing,
{ICASSP} 2021, Toronto, ON, Canada, June 6-11, 2021},
pages = {7863--7867},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICASSP39728.2021.9414690},
doi = {10.1109/ICASSP39728.2021.9414690},
timestamp = {Fri, 09 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icassp/BhattiG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icbip/XuSLWKZZ21,
author = {Xianfu Xu and
Wenjun Su and
Bin Li and
Yini Wei and
Deyu Kong and
Hongjie Zeng and
Xuejun Zhang},
title = {An FPGA-Based Hardware Accelerator for 2D Labeling},
booktitle = {{ICBIP} 2021: 6th International Conference on Biomedical Signal and
Image Processing, Suzhou, China, August 20 - 22, 2021},
pages = {72--78},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3484424.3484436},
doi = {10.1145/3484424.3484436},
timestamp = {Fri, 19 Nov 2021 17:41:45 +0100},
biburl = {https://dblp.org/rec/conf/icbip/XuSLWKZZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icce-tw/ChenLW021,
author = {Tzu{-}Chieh Chen and
Yi{-}Jhen Luo and
Wei{-}Chung Wan and
Tsung{-}Han Tsai},
title = {Knee Lift Detection using Convolutional Neural Network Method with
{FPGA} Hardware Design},
booktitle = {{IEEE} International Conference on Consumer Electronics-Taiwan, {ICCE-TW}
2021, Penghu, Taiwan, September 15-17, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCE-TW52618.2021.9603148},
doi = {10.1109/ICCE-TW52618.2021.9603148},
timestamp = {Tue, 23 Nov 2021 09:27:55 +0100},
biburl = {https://dblp.org/rec/conf/icce-tw/ChenLW021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccel/AhmadH21,
author = {Waqar Ahmad and
Ilker Hamzaoglu},
title = {An Efficient Approximate Sum of Absolute Differences Hardware for
FPGAs},
booktitle = {{IEEE} International Conference on Consumer Electronics, {ICCE} 2021,
Las Vegas, NV, USA, January 10-12, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCE50685.2021.9427756},
doi = {10.1109/ICCE50685.2021.9427756},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccel/AhmadH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccp2/ZaporojanCS21,
author = {Sergiu Zaporojan and
Viorel Carbune and
Radu Razvan Slavescu},
title = {Hardware implementation of Hopfield-like neural networks: Quantitative
analysis of {FPGA} approach},
booktitle = {17th {IEEE} International Conference on Intelligent Computer Communication
and Processing, {ICCP} 2021, Cluj-Napoca, Romania, October 28-30,
2021},
pages = {243--250},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCP53602.2021.9733628},
doi = {10.1109/ICCP53602.2021.9733628},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccp2/ZaporojanCS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iceei/CAS21,
author = {Ardian Dwi C and
Trio Adiono and
Nana Sutisna},
title = {{FPGA} Based Hardware Accelerator Design for Convolution Process in
Convolutional Neural Network},
booktitle = {International Conference on Electrical Engineering and Informatics,
{ICEEI} 2021, Kuala Terengganu, Malaysia, October 12-13, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICEEI52609.2021.9611126},
doi = {10.1109/ICEEI52609.2021.9611126},
timestamp = {Tue, 30 Nov 2021 09:40:21 +0100},
biburl = {https://dblp.org/rec/conf/iceei/CAS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icm2/El-MaksoudGHSAE21,
author = {Ahmed J. Abd El{-}Maksoud and
Amr Gamal and
Aya Hesham and
Gamal Saied and
Mennat{-}Allah Ayman and
Omnia Essam and
Sara M. Mohamed and
Eman El Mandouh and
Ziad Ibrahim and
Sara Mohamed and
Hassan Mostafa},
title = {Hardware-Accelerated {ZYNQ-NET} Convolutional Neural Networks on Virtex-7
{FPGA}},
booktitle = {International Conference on Microelectronics, {ICM} 2021, New Cairo
City, Egypt, December 19-22, 2021},
pages = {70--73},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICM52667.2021.9664956},
doi = {10.1109/ICM52667.2021.9664956},
timestamp = {Mon, 05 Jun 2023 17:41:53 +0200},
biburl = {https://dblp.org/rec/conf/icm2/El-MaksoudGHSAE21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icta3/ChenLZ21,
author = {Xiang Chen and
Jindong Li and
Yong Zhao},
title = {Hardware Resource and Computational Density Efficient {CNN} Accelerator
Design Based on {FPGA}},
booktitle = {2021 {IEEE} International Conference on Integrated Circuits, Technologies
and Applications, {ICTA} 2021, Zhuhai, China, November 24-26, 2021},
pages = {204--205},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICTA53157.2021.9661886},
doi = {10.1109/ICTA53157.2021.9661886},
timestamp = {Mon, 06 Nov 2023 08:19:56 +0100},
biburl = {https://dblp.org/rec/conf/icta3/ChenLZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/igarss/DingZLY21,
author = {Ning Ding and
Zhulin Zong and
Bolun Liu and
Shiwei Yuan},
title = {An {FPGA} Hardware Implementation for Omega-K {SAR} Imaging Algorithm},
booktitle = {{IEEE} International Geoscience and Remote Sensing Symposium, {IGARSS}
2021, Brussels, Belgium, July 11-16, 2021},
pages = {5155--5158},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/IGARSS47720.2021.9553776},
doi = {10.1109/IGARSS47720.2021.9553776},
timestamp = {Tue, 19 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/igarss/DingZLY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isalalife/WhitleyYC21,
author = {Derek Whitley and
Jason Yoder and
Nicklas Carpenter},
editor = {Jitka Cejkov{\'{a}} and
Silvia Holler and
Lisa B. Soros and
Olaf Witkowski},
title = {Resurrecting {FPGA} Intrinsic Analog Evolvable Hardware},
booktitle = {2021 Conference on Artificial Life, {ALIFE} 2021, online, July 19-23,
2021},
pages = {106},
publisher = {{MIT} Press},
year = {2021},
url = {https://doi.org/10.1162/isal\_a\_00448},
doi = {10.1162/ISAL\_A\_00448},
timestamp = {Sun, 02 Oct 2022 16:09:08 +0200},
biburl = {https://dblp.org/rec/conf/isalalife/WhitleyYC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/AmidOASN21,
author = {Alon Amid and
Albert J. Ou and
Krste Asanovic and
Yakun Sophia Shao and
Borivoje Nikolic},
title = {Vertically Integrated Computing Labs Using Open-Source Hardware Generators
and Cloud-Hosted FPGAs},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
Daegu, South Korea, May 22-28, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCAS51556.2021.9401515},
doi = {10.1109/ISCAS51556.2021.9401515},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/AmidOASN21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhangLLZNLJ21,
author = {Cong Zhang and
Dongsheng Liu and
Xingjie Liu and
Xuecheng Zou and
Guangda Niu and
Bo Liu and
Quming Jiang},
title = {Towards Efficient Hardware Implementation of {NTT} for Kyber on FPGAs},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
Daegu, South Korea, May 22-28, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCAS51556.2021.9401170},
doi = {10.1109/ISCAS51556.2021.9401170},
timestamp = {Wed, 22 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ZhangLLZNLJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/LuZSEM21,
author = {Yufan Lu and
Xiaojun Zhai and
Sangeet Saha and
Shoaib Ehsan and
Klaus D. McDonald{-}Maier},
title = {{FPGA} based Adaptive Hardware Acceleration for Multiple Deep Learning
Tasks},
booktitle = {14th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2021, Singapore, Singapore, December 20-23,
2021},
pages = {204--209},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/MCSoC51149.2021.00038},
doi = {10.1109/MCSOC51149.2021.00038},
timestamp = {Fri, 11 Feb 2022 09:29:47 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/LuZSEM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/ThakareYCJ21,
author = {Mansi Thakare and
Palak Yash and
Debaleena Chakraborty and
Babita Jajodia},
title = {Efficient Hardware Implementation of Cube Architecture using Yavadunam
Sutra on {FPGA}},
booktitle = {64th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2021, Lansing, MI, USA, August 9-11, 2021},
pages = {373--376},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/MWSCAS47672.2021.9531843},
doi = {10.1109/MWSCAS47672.2021.9531843},
timestamp = {Wed, 22 Sep 2021 16:10:31 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/ThakareYCJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/niles/El-MaksoudMTAEK21,
author = {Ahmed J. Abd El{-}Maksoud and
Abdallah Mohamed and
Ahmed Tarek and
Amr Adel and
Amr Eid and
Farida Khaled and
Fatma Khaled and
Ziad Ibrahim and
Eman El Mandouh and
Hassan Mostafa},
title = {{FPGA} Design of High-Speed Convolutional Neural Network Hardware
Accelerator},
booktitle = {3rd Novel Intelligent and Leading Emerging Sciences Conference, {NILES}
2021, Giza, Egypt, October 23-25, 2021},
pages = {376--379},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/NILES53778.2021.9600555},
doi = {10.1109/NILES53778.2021.9600555},
timestamp = {Fri, 03 Dec 2021 17:36:32 +0100},
biburl = {https://dblp.org/rec/conf/niles/El-MaksoudMTAEK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pasc/KenterSFA21,
author = {Tobias Kenter and
Adesh Shambhu and
Sara Faghih{-}Naini and
Vadym Aizinger},
editor = {Timothy Robinson},
title = {Algorithm-hardware co-design of a discontinuous Galerkin shallow-water
model for a dataflow architecture on {FPGA}},
booktitle = {{PASC} '21: Platform for Advanced Scientific Computing Conference,
Geneva, Switzerland, July 5-9, 2021},
pages = {13:1--13:11},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3468267.3470617},
doi = {10.1145/3468267.3470617},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/pasc/KenterSFA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sac/SeyoumPBB21,
author = {Biruk B. Seyoum and
Marco Pagani and
Alessandro Biondi and
Giorgio C. Buttazzo},
editor = {Chih{-}Cheng Hung and
Jiman Hong and
Alessio Bechini and
Eunjee Song},
title = {Automating the design flow under dynamic partial reconfiguration for
hardware-software co-design in {FPGA} SoC},
booktitle = {{SAC} '21: The 36th {ACM/SIGAPP} Symposium on Applied Computing, Virtual
Event, Republic of Korea, March 22-26, 2021},
pages = {481--490},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3412841.3441928},
doi = {10.1145/3412841.3441928},
timestamp = {Sat, 18 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sac/SeyoumPBB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbac-pad/HarisGCAK21,
author = {Jude Haris and
Perry Gibson and
Jos{\'{e}} Cano and
Nicolas Bohm Agostini and
David R. Kaeli},
title = {{SECDA:} Efficient Hardware/Software Co-Design of FPGA-based {DNN}
Accelerators for Edge Inference},
booktitle = {33rd {IEEE} International Symposium on Computer Architecture and High
Performance Computing, {SBAC-PAD} 2021, Belo Horizonte, Brazil, October
26-29, 2021},
pages = {33--43},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SBAC-PAD53543.2021.00015},
doi = {10.1109/SBAC-PAD53543.2021.00015},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbac-pad/HarisGCAK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KrishnanSS21,
author = {Abi K. Krishnan and
M. H. Supriya and
Nalesh Sivanandan},
title = {A Hardware-Software Co-design based Approach for Development of a
Distributed {DAQ} System using {FPGA}},
booktitle = {25th International Symposium on {VLSI} Design and Test, {VDAT} 2021,
Surat, India, September 16-18, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VDAT53777.2021.9600989},
doi = {10.1109/VDAT53777.2021.9600989},
timestamp = {Fri, 19 Nov 2021 11:34:23 +0100},
biburl = {https://dblp.org/rec/conf/vdat/KrishnanSS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ShekhawatJP21,
author = {Diksha Shekhawat and
Apoorva Jangir and
Jai Gopal Pandey},
title = {A Hardware Generator for Posit Arithmetic and its {FPGA} Prototyping},
booktitle = {25th International Symposium on {VLSI} Design and Test, {VDAT} 2021,
Surat, India, September 16-18, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VDAT53777.2021.9601025},
doi = {10.1109/VDAT53777.2021.9601025},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vdat/ShekhawatJP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2101-01745,
author = {Tom Hogervorst and
Tong Dong Qiu and
Giacomo Marchiori and
Alf Birger Rustad and
Markus Blatt and
Razvan Nane},
title = {Hardware Acceleration of {HPC} Computational Flow Dynamics using HBM-enabled
FPGAs},
journal = {CoRR},
volume = {abs/2101.01745},
year = {2021},
url = {https://arxiv.org/abs/2101.01745},
eprinttype = {arXiv},
eprint = {2101.01745},
timestamp = {Thu, 21 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2101-01745.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2102-01351,
author = {Olivia Weng and
Alireza Khodamoradi and
Ryan Kastner},
title = {Hardware-efficient Residual Networks for FPGAs},
journal = {CoRR},
volume = {abs/2102.01351},
year = {2021},
url = {https://arxiv.org/abs/2102.01351},
eprinttype = {arXiv},
eprint = {2102.01351},
timestamp = {Tue, 09 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2102-01351.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2105-07131,
author = {Amir{-}Hossein Kiamarzi and
Pezhman Torabi and
Reza Sameni},
title = {Hardware Synthesis of State-Space Equations; Application to {FPGA}
Implementation of Shallow and Deep Neural Networks},
journal = {CoRR},
volume = {abs/2105.07131},
year = {2021},
url = {https://arxiv.org/abs/2105.07131},
eprinttype = {arXiv},
eprint = {2105.07131},
timestamp = {Tue, 18 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2105-07131.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2109-03276,
author = {V{\'{\i}}ctor Mayoral Vilches and
Giulio Corradi},
title = {Adaptive Computing in Robotics, Leveraging {ROS} 2 to Enable Software-Defined
Hardware for FPGAs},
journal = {CoRR},
volume = {abs/2109.03276},
year = {2021},
url = {https://arxiv.org/abs/2109.03276},
eprinttype = {arXiv},
eprint = {2109.03276},
timestamp = {Mon, 20 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2109-03276.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2110-00478,
author = {Jude Haris and
Perry Gibson and
Jos{\'{e}} Cano and
Nicolas Bohm Agostini and
David R. Kaeli},
title = {{SECDA:} Efficient Hardware/Software Co-Design of FPGA-based {DNN}
Accelerators for Edge Inference},
journal = {CoRR},
volume = {abs/2110.00478},
year = {2021},
url = {https://arxiv.org/abs/2110.00478},
eprinttype = {arXiv},
eprint = {2110.00478},
timestamp = {Fri, 08 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2110-00478.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2112-12836,
author = {Ahsan Javed Awan and
Fidan Aliyeva},
title = {Hardware Support for {FPGA} Resource Elasticity},
journal = {CoRR},
volume = {abs/2112.12836},
year = {2021},
url = {https://arxiv.org/abs/2112.12836},
eprinttype = {arXiv},
eprint = {2112.12836},
timestamp = {Tue, 04 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2112-12836.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iacr/DangMG21,
author = {Viet Ba Dang and
Kamyar Mohajerani and
Kris Gaj},
title = {High-Speed Hardware Architectures and {FPGA} Benchmarking of CRYSTALS-Kyber,
NTRU, and Saber},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {1508},
year = {2021},
url = {https://eprint.iacr.org/2021/1508},
timestamp = {Fri, 10 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iacr/DangMG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/QiY21,
title = {Artificial intelligence enterprise human resource management system
based on {FPGA} high performance computer hardware},
journal = {Microprocess. Microsystems},
volume = {82},
pages = {103876},
year = {2021},
note = {Withdrawn.},
url = {https://doi.org/10.1016/j.micpro.2021.103876},
doi = {10.1016/J.MICPRO.2021.103876},
timestamp = {Wed, 26 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/QiY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/basesearch/Gnad20,
author = {Dennis Gnad},
title = {Remote Attacks on {FPGA} Hardware},
school = {Karlsruhe University, Germany},
year = {2020},
url = {https://publikationen.bibliothek.kit.edu/1000123237},
doi = {10.5445/IR/1000123237},
timestamp = {Wed, 28 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/phd/basesearch/Gnad20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/hal/Pagani20,
author = {Marco Pagani},
title = {Enabling Predictable Hardware Acceleration in Heterogeneous SoC-FPGA
Computing Platforms. (Techniques pour l'am{\'{e}}lioration de
la pr{\'{e}}visibilit{\'{e}} de l'acc{\'{e}}l{\'{e}}ration
mat{\'{e}}rielle pour les plateformes informatiques h{\'{e}}t{\'{e}}rog{\`{e}}nes
SoC-FPGA)},
school = {University of Lille, France},
year = {2020},
url = {https://tel.archives-ouvertes.fr/tel-03770711},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/hal/Pagani20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/it/Erdem20,
author = {Ahmet Erdem},
title = {Exploration and mapping of deep neural networks to low-power hardware
accelerators and FPGAs},
school = {Polytechnic University of Milan, Italy},
year = {2020},
url = {https://hdl.handle.net/10589/169430},
timestamp = {Wed, 12 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/it/Erdem20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/it/Tucci20,
author = {Lorenzo Di Tucci},
title = {Hugenomic: exploiting FPGAs as hardware accelerators in the genomic
domain},
school = {Polytechnic University of Milan, Italy},
year = {2020},
url = {https://hdl.handle.net/10589/169429},
timestamp = {Thu, 20 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/it/Tucci20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/Al-ShatariHAWT20,
author = {Mohammed Omar Awadh Al{-}Shatari and
Fawnizu Azmadi Hussin and
Azrina Abd Aziz and
Gunawan Witjaksono and
Xuan{-}Tu Tran},
title = {FPGA-Based Lightweight Hardware Architecture of the {PHOTON} Hash
Function for IoT Edge Devices},
journal = {{IEEE} Access},
volume = {8},
pages = {207610--207618},
year = {2020},
url = {https://doi.org/10.1109/ACCESS.2020.3038219},
doi = {10.1109/ACCESS.2020.3038219},
timestamp = {Thu, 31 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/Al-ShatariHAWT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/AslamJSPF20,
author = {Sohaib Aslam and
Ian K. Jennions and
Mohammad Samie and
Suresh Perinpanayagam and
Yisen Fang},
title = {Ingress of Threshold Voltage-Triggered Hardware Trojan in the Modern
{FPGA} Fabric-Detection Methodology and Mitigation},
journal = {{IEEE} Access},
volume = {8},
pages = {31371--31397},
year = {2020},
url = {https://doi.org/10.1109/ACCESS.2020.2973260},
doi = {10.1109/ACCESS.2020.2973260},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/AslamJSPF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/KawashimaMT20,
author = {Ichiro Kawashima and
Takashi Morie and
Hakaru Tamukoh},
title = {{FPGA} Implementation of Hardware-Oriented Chaotic Boltzmann Machines},
journal = {{IEEE} Access},
volume = {8},
pages = {204360--204377},
year = {2020},
url = {https://doi.org/10.1109/ACCESS.2020.3036882},
doi = {10.1109/ACCESS.2020.3036882},
timestamp = {Tue, 01 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/KawashimaMT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/LedwonCH20,
author = {Morgan Ledwon and
Bruce F. Cockburn and
Jie Han},
title = {High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression
and Decompression Using High-Level Synthesis},
journal = {{IEEE} Access},
volume = {8},
pages = {62207--62217},
year = {2020},
url = {https://doi.org/10.1109/ACCESS.2020.2984191},
doi = {10.1109/ACCESS.2020.2984191},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/LedwonCH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/NguyenAH20,
author = {Anh Hoang Ngoc Nguyen and
Masashi Aono and
Yuko Hara{-}Azumi},
title = {FPGA-Based Hardware/Software Co-Design of a Bio-Inspired {SAT} Solver},
journal = {{IEEE} Access},
volume = {8},
pages = {49053--49065},
year = {2020},
url = {https://doi.org/10.1109/ACCESS.2020.2980008},
doi = {10.1109/ACCESS.2020.2980008},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/NguyenAH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/SuYYT20,
author = {Yang Su and
Bailong Yang and
Chen Yang and
Luogeng Tian},
title = {FPGA-Based Hardware Accelerator for Leveled Ring-LWE Fully Homomorphic
Encryption},
journal = {{IEEE} Access},
volume = {8},
pages = {168008--168025},
year = {2020},
url = {https://doi.org/10.1109/ACCESS.2020.3023255},
doi = {10.1109/ACCESS.2020.3023255},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/SuYYT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/WangXWLLW20,
author = {Zixiao Wang and
Ke Xu and
Shuaixiao Wu and
Li Liu and
Lingzhi Liu and
Dong Wang},
title = {Sparse-YOLO: Hardware/Software Co-Design of an {FPGA} Accelerator
for YOLOv2},
journal = {{IEEE} Access},
volume = {8},
pages = {116569--116585},
year = {2020},
url = {https://doi.org/10.1109/ACCESS.2020.3004198},
doi = {10.1109/ACCESS.2020.3004198},
timestamp = {Thu, 16 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/WangXWLLW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/WangXX20,
author = {Dong Wang and
Jia Xu and
Ke Xu},
title = {An FPGA-Based Hardware Accelerator for Real-Time Block-Matching and
3D Filtering},
journal = {{IEEE} Access},
volume = {8},
pages = {121987--121998},
year = {2020},
url = {https://doi.org/10.1109/ACCESS.2020.3006773},
doi = {10.1109/ACCESS.2020.3006773},
timestamp = {Thu, 16 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/WangXX20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/YanTZ20,
author = {Weian Yan and
Weiqin Tong and
Xiaoli Zhi},
title = {{FPGAN:} An {FPGA} Accelerator for Graph Attention Networks With Software
and Hardware Co-Optimization},
journal = {{IEEE} Access},
volume = {8},
pages = {171608--171620},
year = {2020},
url = {https://doi.org/10.1109/ACCESS.2020.3023946},
doi = {10.1109/ACCESS.2020.3023946},
timestamp = {Sat, 21 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/YanTZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/ZhiCDD20,
author = {Shuaiqing Zhi and
Yani Cui and
Jiaxian Deng and
Wencai Du},
title = {An FPGA-Based Simple {RGB-HSI} Space Conversion Algorithm for Hardware
Image Processing},
journal = {{IEEE} Access},
volume = {8},
pages = {173838--173853},
year = {2020},
url = {https://doi.org/10.1109/ACCESS.2020.3026189},
doi = {10.1109/ACCESS.2020.3026189},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/ZhiCDD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/casa/Pham-Quoc20,
author = {Cuong Pham{-}Quoc},
title = {Automatic FPGA-based Hardware Accelerator Design: {A} Case Study with
Image Processing Applications},
journal = {{EAI} Endorsed Trans. Context aware Syst. Appl.},
volume = {7},
number = {20},
pages = {e5},
year = {2020},
url = {https://doi.org/10.4108/eai.12-5-2020.164497},
doi = {10.4108/EAI.12-5-2020.164497},
timestamp = {Wed, 22 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/casa/Pham-Quoc20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cbm/InamBQO20,
author = {Omair Inam and
Abdul Basit and
Mahmood Qureshi and
Hammad Omer},
title = {FPGA-based hardware accelerator for {SENSE} (a parallel {MR} image
reconstruction method)},
journal = {Comput. Biol. Medicine},
volume = {117},
pages = {103598},
year = {2020},
url = {https://doi.org/10.1016/j.compbiomed.2019.103598},
doi = {10.1016/J.COMPBIOMED.2019.103598},
timestamp = {Wed, 02 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cbm/InamBQO20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/darts/RestucciaPBMB20,
author = {Francesco Restuccia and
Marco Pagani and
Alessandro Biondi and
Mauro Marinoni and
Giorgio C. Buttazzo},
title = {Modeling and Analysis of Bus Contention for Hardware Accelerators
in {FPGA} SoCs (Artifact)},
journal = {Dagstuhl Artifacts Ser.},
volume = {6},
number = {1},
pages = {04:1--04:3},
year = {2020},
url = {https://doi.org/10.4230/DARTS.6.1.4},
doi = {10.4230/DARTS.6.1.4},
timestamp = {Thu, 22 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/darts/RestucciaPBMB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/KumarML20,
author = {Vikas Kumar and
Mithun Mukherjee and
Jaime Lloret},
title = {A Hardware-Efficient and Reconfigurable {UFMC} Transmitter Architecture
With its {FPGA} Prototype},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {12},
number = {4},
pages = {109--112},
year = {2020},
url = {https://doi.org/10.1109/LES.2019.2961850},
doi = {10.1109/LES.2019.2961850},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/KumarML20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrnal/HondaT20,
author = {Kentaro Honda and
Hakaru Tamukoh},
title = {A Hardware-Oriented Echo State Network and its {FPGA} Implementation},
journal = {J. Robotics Netw. Artif. Life},
volume = {7},
number = {1},
pages = {58--62},
year = {2020},
url = {https://doi.org/10.2991/jrnal.k.200512.012},
doi = {10.2991/JRNAL.K.200512.012},
timestamp = {Tue, 02 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jrnal/HondaT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jstsp/JainGAFA20,
author = {Akshay Jain and
Pulkit Goel and
Shivam Aggarwal and
Alexander Fell and
Saket Anand},
title = {Symmetric {\textdollar}k{\textdollar}-Means for Deep Neural Network
Compression and Hardware Acceleration on FPGAs},
journal = {{IEEE} J. Sel. Top. Signal Process.},
volume = {14},
number = {4},
pages = {737--749},
year = {2020},
url = {https://doi.org/10.1109/JSTSP.2020.2968810},
doi = {10.1109/JSTSP.2020.2968810},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jstsp/JainGAFA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/HassaneinEDR20,
author = {Ahmed Hassanein and
Mohammed El{-}Abd and
Issam W. Damaj and
Haseeb Ur Rehman},
title = {Parallel hardware implementation of the brain storm optimization algorithm
using FPGAs},
journal = {Microprocess. Microsystems},
volume = {74},
pages = {103005},
year = {2020},
url = {https://doi.org/10.1016/j.micpro.2020.103005},
doi = {10.1016/J.MICPRO.2020.103005},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/HassaneinEDR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/HusseinDR20,
author = {Fady Hussein and
Luka Daoud and
Nader Rafla},
title = {A reconfigurable HexCell-based systolic array architecture for evolvable
hardware on {FPGA}},
journal = {Microprocess. Microsystems},
volume = {74},
pages = {103014},
year = {2020},
url = {https://doi.org/10.1016/j.micpro.2020.103014},
doi = {10.1016/J.MICPRO.2020.103014},
timestamp = {Wed, 07 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/HusseinDR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/MertOS20,
author = {Ahmet Can Mert and
Erdin{\c{c}} {\"{O}}zt{\"{u}}rk and
Erkay Savas},
title = {{FPGA} implementation of a run-time configurable NTT-based polynomial
multiplication hardware},
journal = {Microprocess. Microsystems},
volume = {78},
pages = {103219},
year = {2020},
url = {https://doi.org/10.1016/j.micpro.2020.103219},
doi = {10.1016/J.MICPRO.2020.103219},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/MertOS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/SwamynathanB20,
author = {S. M. Swamynathan and
Velusamy Bhanumathi},
title = {Efficient hardware trojan diagnosis in {SRAM} based on {FPGA} processors
using inject detect masking algorithm for multimedia signal Processors},
journal = {Microprocess. Microsystems},
volume = {77},
pages = {103168},
year = {2020},
url = {https://doi.org/10.1016/j.micpro.2020.103168},
doi = {10.1016/J.MICPRO.2020.103168},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/SwamynathanB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mssp/PhadikarMC20,
author = {Amit Phadikar and
Himadri S. Mandal and
Tien{-}Lung Chiu},
title = {Parallel hardware implementation of data hiding scheme for quality
access control of grayscale image based on {FPGA}},
journal = {Multidimens. Syst. Signal Process.},
volume = {31},
number = {1},
pages = {73--101},
year = {2020},
url = {https://doi.org/10.1007/s11045-019-00650-x},
doi = {10.1007/S11045-019-00650-X},
timestamp = {Fri, 03 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mssp/PhadikarMC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mta/PhadikarMC20,
author = {Amit Phadikar and
Himadri S. Mandal and
Tien{-}Lung Chiu},
title = {A novel {QIM} data hiding scheme and its hardware implementation using
{FPGA} for quality access control of digital image},
journal = {Multim. Tools Appl.},
volume = {79},
number = {17-18},
pages = {12507--12532},
year = {2020},
url = {https://doi.org/10.1007/s11042-019-08392-5},
doi = {10.1007/S11042-019-08392-5},
timestamp = {Mon, 11 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mta/PhadikarMC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/peerj-cs/KakkaraBYMLM20,
author = {Varsha Kakkara and
Karthi Balasubramanian and
B. Yamuna and
Deepak Mishra and
Karthikeyan Lingasubramanian and
Senthil Murugan},
title = {A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation
study},
journal = {PeerJ Comput. Sci.},
volume = {6},
pages = {e250},
year = {2020},
url = {https://doi.org/10.7717/peerj-cs.250},
doi = {10.7717/PEERJ-CS.250},
timestamp = {Wed, 16 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/peerj-cs/KakkaraBYMLM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/Abdelrahman20,
author = {Tarek S. Abdelrahman},
title = {Cooperative Software-hardware Acceleration of K-means on a Tightly
Coupled {CPU-FPGA} System},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {17},
number = {3},
pages = {20:1--20:24},
year = {2020},
url = {https://doi.org/10.1145/3406114},
doi = {10.1145/3406114},
timestamp = {Sat, 18 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/Abdelrahman20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuoWQLTWG20,
author = {Tao Luo and
Xuan Wang and
Chuping Qu and
Matthew Kay Fei Lee and
Wai Teng Tang and
Weng{-}Fai Wong and
Rick Siow Mong Goh},
title = {An FPGA-Based Hardware Emulator for Neuromorphic Chip With {RRAM}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {2},
pages = {438--450},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2018.2889670},
doi = {10.1109/TCAD.2018.2889670},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuoWQLTWG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangXGG20,
author = {Dong Wang and
Ke Xu and
Jingning Guo and
Soheil Ghiasi},
title = {DSP-Efficient Hardware Acceleration of Convolutional Neural Network
Inference on FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {12},
pages = {4867--4880},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2020.2968023},
doi = {10.1109/TCAD.2020.2968023},
timestamp = {Thu, 16 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WangXGG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/AhmadP20,
author = {Afzal Ahmad and
Muhammad Adeel Pasha},
title = {Optimizing Hardware Accelerated General Matrix-Matrix Multiplication
for CNNs on FPGAs},
journal = {{IEEE} Trans. Circuits Syst.},
volume = {67-II},
number = {11},
pages = {2692--2696},
year = {2020},
url = {https://doi.org/10.1109/TCSII.2020.2965154},
doi = {10.1109/TCSII.2020.2965154},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/AhmadP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tim/QinZWZTRD20,
author = {Xi Qin and
Wenzhe Zhang and
Lin Wang and
Yuxi Zhao and
Yu Tong and
Xing Rong and
Jiangfeng Du},
title = {An FPGA-Based Hardware Platform for the Control of Spin-Based Quantum
Systems},
journal = {{IEEE} Trans. Instrum. Meas.},
volume = {69},
number = {4},
pages = {1127--1139},
year = {2020},
url = {https://doi.org/10.1109/TIM.2019.2910921},
doi = {10.1109/TIM.2019.2910921},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tim/QinZWZTRD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tjs/GuhaMSC20,
author = {Krishnendu Guha and
Atanu Majumder and
Debasri Saha and
Amlan Chakrabarti},
title = {Dynamic power-aware scheduling of real-time tasks for FPGA-based cyber
physical systems against power draining hardware trojan attacks},
journal = {J. Supercomput.},
volume = {76},
number = {11},
pages = {8972--9009},
year = {2020},
url = {https://doi.org/10.1007/s11227-020-03184-3},
doi = {10.1007/S11227-020-03184-3},
timestamp = {Sat, 19 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tjs/GuhaMSC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DelomierGCJ20,
author = {Yann Delomier and
Bertrand Le Gal and
J{\'{e}}r{\'{e}}mie Crenne and
Christophe J{\'{e}}go},
title = {Model-based Design of Hardware {SC} Polar Decoders for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {2},
pages = {10:1--10:27},
year = {2020},
url = {https://doi.org/10.1145/3391431},
doi = {10.1145/3391431},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/DelomierGCJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhuHYZZS20,
author = {Chaoyang Zhu and
Kejie Huang and
Shuyuan Yang and
Ziqi Zhu and
Hejia Zhang and
Haibin Shen},
title = {An Efficient Hardware Accelerator for Structured Sparse Convolutional
Neural Networks on FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {9},
pages = {1953--1965},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3002779},
doi = {10.1109/TVLSI.2020.3002779},
timestamp = {Sat, 19 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhuHYZZS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/wc/ChamolaPKG20,
author = {Vinay Chamola and
Sambit Patra and
Neeraj Kumar and
Mohsen Guizani},
title = {{FPGA} for 5G: Re-configurable Hardware for Next Generation Communication},
journal = {{IEEE} Wirel. Commun.},
volume = {27},
number = {3},
pages = {140--147},
year = {2020},
url = {https://doi.org/10.1109/MWC.001.1900359},
doi = {10.1109/MWC.001.1900359},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/wc/ChamolaPKG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aca/LiangXYS20,
author = {Dongbao Liang and
Jiale Xiao and
Yangbin Yu and
Tao Su},
editor = {Dezun Dong and
Xiaoli Gong and
Cunlu Li and
Dongsheng Li and
Junjie Wu},
title = {A {CNN} Hardware Accelerator in {FPGA} for Stacked Hourglass Network},
booktitle = {Advanced Computer Architecture - 13th Conference, {ACA} 2020, Kunming,
China, August 13-15, 2020, Proceedings},
series = {Communications in Computer and Information Science},
volume = {1256},
pages = {101--116},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-981-15-8135-9\_8},
doi = {10.1007/978-981-15-8135-9\_8},
timestamp = {Wed, 23 Mar 2022 17:30:19 +0100},
biburl = {https://dblp.org/rec/conf/aca/LiangXYS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/acns/LabafniyaBM20,
author = {Mansoureh Labafniya and
Shahram Etemadi Borujeni and
Nele Mentens},
editor = {Jianying Zhou and
Mauro Conti and
Chuadhry Mujeeb Ahmed and
Man Ho Au and
Lejla Batina and
Zhou Li and
Jingqiang Lin and
Eleonora Losiouk and
Bo Luo and
Suryadipta Majumdar and
Weizhi Meng and
Mart{\'{\i}}n Ochoa and
Stjepan Picek and
Georgios Portokalidis and
Cong Wang and
Kehuan Zhang},
title = {Evolvable Hardware Architectures on {FPGA} for Side-Channel Security},
booktitle = {Applied Cryptography and Network Security Workshops - {ACNS} 2020
Satellite Workshops, AIBlock, AIHWS, AIoTS, Cloud S{\&}P, SCI,
SecMT, and SiMLA, Rome, Italy, October 19-22, 2020, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {12418},
pages = {163--180},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-61638-0\_10},
doi = {10.1007/978-3-030-61638-0\_10},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/acns/LabafniyaBM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/BacchusSK20,
author = {Pascal Bacchus and
Robert J. Stewart and
Ekaterina Komendantskaya},
editor = {Fernando Rinc{\'{o}}n and
Jes{\'{u}}s Barba and
Hayden Kwok{-}Hay So and
Pedro C. Diniz and
Juli{\'{a}}n Caba},
title = {Accuracy, Training Time and Hardware Efficiency Trade-Offs for Quantized
Neural Networks on FPGAs},
booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications
- 16th International Symposium, {ARC} 2020, Toledo, Spain, April 1-3,
2020, Proceedings [postponed]},
series = {Lecture Notes in Computer Science},
volume = {12083},
pages = {121--135},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-44534-8\_10},
doi = {10.1007/978-3-030-44534-8\_10},
timestamp = {Mon, 01 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arc/BacchusSK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/IkedaSNMT20,
author = {Taiga Ikeda and
Kento Sakurada and
Atsuyoshi Nakamura and
Masato Motomura and
Shinya Takamaeda{-}Yamazaki},
editor = {Fernando Rinc{\'{o}}n and
Jes{\'{u}}s Barba and
Hayden Kwok{-}Hay So and
Pedro C. Diniz and
Juli{\'{a}}n Caba},
title = {Hardware/Algorithm Co-optimization for Fully-Parallelized Compact
Decision Tree Ensembles on FPGAs},
booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications
- 16th International Symposium, {ARC} 2020, Toledo, Spain, April 1-3,
2020, Proceedings [postponed]},
series = {Lecture Notes in Computer Science},
volume = {12083},
pages = {345--357},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-44534-8\_26},
doi = {10.1007/978-3-030-44534-8\_26},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/arc/IkedaSNMT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asianhost/SahaB20,
author = {Sujan Kumar Saha and
Christophe Bobda},
title = {{FPGA} Accelerated Embedded System Security Through Hardware Isolation},
booktitle = {Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2020,
Kolkata, India, December 15-17, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/AsianHOST51057.2020.9358258},
doi = {10.1109/ASIANHOST51057.2020.9358258},
timestamp = {Wed, 03 Mar 2021 11:46:43 +0100},
biburl = {https://dblp.org/rec/conf/asianhost/SahaB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asplos/KarandikarOAMKN20,
author = {Sagar Karandikar and
Albert J. Ou and
Alon Amid and
Howard Mao and
Randy H. Katz and
Borivoje Nikolic and
Krste Asanovic},
editor = {James R. Larus and
Luis Ceze and
Karin Strauss},
title = {FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance
Profiling and Co-Design},
booktitle = {{ASPLOS} '20: Architectural Support for Programming Languages and
Operating Systems, Lausanne, Switzerland, March 16-20, 2020},
pages = {715--731},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3373376.3378455},
doi = {10.1145/3373376.3378455},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asplos/KarandikarOAMKN20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/atsip/MhaouchEA20,
author = {Ayoub Mhaouch and
Wajdi Elhamzi and
Mohamed Atri},
title = {Lightweight Hardware Architectures for the Piccolo Block Cipher in
{FPGA}},
booktitle = {5th International Conference on Advanced Technologies for Signal and
Image Processing, {ATSIP} 2020, Sousse, Tunisia, September 2-5, 2020},
pages = {1--4},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ATSIP49331.2020.9231586},
doi = {10.1109/ATSIP49331.2020.9231586},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/atsip/MhaouchEA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cosade/BarenghiBFPZ20,
author = {Alessandro Barenghi and
Matteo Brevi and
William Fornaciari and
Gerardo Pelosi and
Davide Zoni},
editor = {Guido Marco Bertoni and
Francesco Regazzoni},
title = {Integrating Side Channel Security in the {FPGA} Hardware Design Flow},
booktitle = {Constructive Side-Channel Analysis and Secure Design - 11th International
Workshop, {COSADE} 2020, Lugano, Switzerland, April 1-3, 2020, Revised
Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {12244},
pages = {275--290},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-68773-1\_13},
doi = {10.1007/978-3-030-68773-1\_13},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cosade/BarenghiBFPZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cscloud/Li0TNC20,
author = {Wanyi Li and
Yongxin Zhu and
Li Tian and
Tianhao Nan and
Xintong Chen},
title = {FPGA-based Hardware Acceleration for Image Copyright Protection Syetem
Based on Blockchain},
booktitle = {7th {IEEE} International Conference on Cyber Security and Cloud Computing,
CSCloud 2020 / 6th {IEEE} International Conference on Edge Computing
and Scalable Cloud, EdgeCom 2020, New York City, NY, USA, August 1-3,
2020},
pages = {234--239},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/CSCloud-EdgeCom49738.2020.00048},
doi = {10.1109/CSCLOUD-EDGECOM49738.2020.00048},
timestamp = {Wed, 26 Aug 2020 17:23:33 +0200},
biburl = {https://dblp.org/rec/conf/cscloud/Li0TNC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csoc/KajurP20,
author = {Renuka Kajur and
K. V. Prasad},
editor = {Radek Silhavy},
title = {Hardware Realization of {GMSK} System Using Pipelined {CORDIC} Module
on {FPGA}},
booktitle = {Applied Informatics and Cybernetics in Intelligent Systems - Proceedings
of the 9th Computer Science On-line Conference 2020, Volume 3},
series = {Advances in Intelligent Systems and Computing},
volume = {1226},
pages = {21--31},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-51974-2\_3},
doi = {10.1007/978-3-030-51974-2\_3},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/csoc/KajurP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KwadjoB20,
author = {Danielle Tchuinkou Kwadjo and
Christophe Bobda},
title = {Late Breaking Results: Automated Hardware Generation of {CNN} Models
on FPGAs},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218692},
doi = {10.1109/DAC18072.2020.9218692},
timestamp = {Wed, 14 Oct 2020 10:56:17 +0200},
biburl = {https://dblp.org/rec/conf/dac/KwadjoB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/RestucciaBMCB20,
author = {Francesco Restuccia and
Alessandro Biondi and
Mauro Marinoni and
Giorgiomaria Cicero and
Giorgio C. Buttazzo},
title = {{AXI} HyperConnect: {A} Predictable, Hypervisor-level Interconnect
for Hardware Accelerators in {FPGA} SoC},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218652},
doi = {10.1109/DAC18072.2020.9218652},
timestamp = {Thu, 22 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/RestucciaBMCB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SunZGPLL20,
author = {Mengshu Sun and
Pu Zhao and
Mehmet G{\"{u}}ng{\"{o}}r and
Massoud Pedram and
Miriam Leeser and
Xue Lin},
title = {3D {CNN} Acceleration on {FPGA} using Hardware-Aware Pruning},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218571},
doi = {10.1109/DAC18072.2020.9218571},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/SunZGPLL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dcis/CarvalhoFT20,
author = {Guilherme Carvalho and
Jo{\~{a}}o Canas Ferreira and
V{\'{\i}}tor Grade Tavares},
title = {Hardware architecture for integrate-and-fire signal reconstruction
on {FPGA}},
booktitle = {{XXXV} Conference on Design of Circuits and Integrated Systems, {DCIS}
2020, Segovia, Spain, November 18-20, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DCIS51330.2020.9268638},
doi = {10.1109/DCIS51330.2020.9268638},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dcis/CarvalhoFT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/FariasNC20,
author = {Marcos Santana Farias and
Nadia Nedjah and
Paulo Victor R. de Carvalho},
title = {Active Redundant Hardware Architecture for Increased Reliability in
FPGA-Based Nuclear Reactors Critical Systems},
booktitle = {23rd Euromicro Conference on Digital System Design, {DSD} 2020, Kranj,
Slovenia, August 26-28, 2020},
pages = {608--615},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DSD51259.2020.00100},
doi = {10.1109/DSD51259.2020.00100},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/FariasNC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/PalaciosCDF20,
author = {Jorge Andr{\'{e}}s Palacios and
Vincenzo Caro and
Miguel Dur{\'{a}}n and
Miguel E. Figueroa},
title = {A hardware architecture for Multiscale Retinex with Chromacity Preservation
on an {FPGA}},
booktitle = {23rd Euromicro Conference on Digital System Design, {DSD} 2020, Kranj,
Slovenia, August 26-28, 2020},
pages = {73--80},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DSD51259.2020.00023},
doi = {10.1109/DSD51259.2020.00023},
timestamp = {Fri, 17 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/PalaciosCDF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ecrts/RestucciaPBMB20,
author = {Francesco Restuccia and
Marco Pagani and
Alessandro Biondi and
Mauro Marinoni and
Giorgio C. Buttazzo},
editor = {Marcus V{\"{o}}lp},
title = {Modeling and Analysis of Bus Contention for Hardware Accelerators
in {FPGA} SoCs},
booktitle = {32nd Euromicro Conference on Real-Time Systems, {ECRTS} 2020, July
7-10, 2020, Virtual Conference},
series = {LIPIcs},
volume = {165},
pages = {12:1--12:23},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2020},
url = {https://doi.org/10.4230/LIPIcs.ECRTS.2020.12},
doi = {10.4230/LIPICS.ECRTS.2020.12},
timestamp = {Thu, 22 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ecrts/RestucciaPBMB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/euc/RiveraW20,
author = {Luis Ramirez Rivera and
Xiaofang Wang},
editor = {Guojun Wang and
Gregorio Mart{\'{\i}}nez P{\'{e}}rez and
Scott Fowler and
Kuan{-}Ching Li},
title = {Run-time Hardware Trojan Detection and Recovery for Third-Party IPs
in SoC FPGAs},
booktitle = {18th {IEEE} International Conference on Embedded and Ubiquitous Computing,
{EUC} 2020, Guangzhou, China, December 31, 2020 - January 1, 2021},
pages = {9--16},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/EUC50751.2020.00009},
doi = {10.1109/EUC50751.2020.00009},
timestamp = {Fri, 30 Apr 2021 12:35:39 +0200},
biburl = {https://dblp.org/rec/conf/euc/RiveraW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ewdts/GorbachovBPK20,
author = {Valeriy Gorbachov and
Abdulrahman Kataeba Batiaa and
Olha Ponomarenko and
Oksana Kotkova},
title = {Hardware Obfuscation Techniques on FPGA-Based Systems},
booktitle = {{IEEE} East-West Design {\&} Test Symposium, {EWDTS} 2020, Varna,
Bulgaria, September 4-7, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/EWDTS50664.2020.9225151},
doi = {10.1109/EWDTS50664.2020.9225151},
timestamp = {Thu, 22 Oct 2020 12:13:23 +0200},
biburl = {https://dblp.org/rec/conf/ewdts/GorbachovBPK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fie/LiZMY20,
author = {Ying Li and
Jiong Zhang and
Hritik Mitra and
Shicheng Yu},
title = {The Systematic Thinking Ability of Hardware/Software Co-design using
{FPGA}},
booktitle = {{IEEE} Frontiers in Education Conference, {FIE} 2020, Uppsala, Sweden,
October 21-24, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/FIE44824.2020.9274284},
doi = {10.1109/FIE44824.2020.9274284},
timestamp = {Mon, 14 Dec 2020 09:13:16 +0100},
biburl = {https://dblp.org/rec/conf/fie/LiZMY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/AttiaB20,
author = {Sameh Attia and
Vaughn Betz},
editor = {Stephen Neuendorffer and
Lesley Shannon},
title = {StateMover: Combining Simulation and Hardware Execution for Efficient
{FPGA} Debugging},
booktitle = {{FPGA} '20: The 2020 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Seaside, CA, USA, February 23-25, 2020},
pages = {175--185},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3373087.3375307},
doi = {10.1145/3373087.3375307},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/AttiaB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DewanG20,
author = {Samuel Dewan and
Paulo Garcia},
editor = {Stephen Neuendorffer and
Lesley Shannon},
title = {Programming Abstractions for Configurable Hardware: Survey and Research
Directions},
booktitle = {{FPGA} '20: The 2020 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Seaside, CA, USA, February 23-25, 2020},
pages = {310},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3373087.3375324},
doi = {10.1145/3373087.3375324},
timestamp = {Wed, 04 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/DewanG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Martinez-Corral20,
author = {Unai Martinez{-}Corral and
Guillermo Callaghan and
Konstantinos Iordanou and
Cosmin Gorgovan and
Koldo Basterretxea and
Mikel Luj{\'{a}}n},
editor = {Stephen Neuendorffer and
Lesley Shannon},
title = {{DBHI:} {A} Tool for Decoupled Functional Hardware-Software Co-Design
on SoCs},
booktitle = {{FPGA} '20: The 2020 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Seaside, CA, USA, February 23-25, 2020},
pages = {326},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3373087.3375386},
doi = {10.1145/3373087.3375386},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/Martinez-Corral20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MatasLGPK20,
author = {Kaspar Matas and
Tuan La and
Nikola Grunchevski and
Khoa Dang Pham and
Dirk Koch},
editor = {Stephen Neuendorffer and
Lesley Shannon},
title = {Invited Tutorial: {FPGA} Hardware Security for Datacenters and Beyond},
booktitle = {{FPGA} '20: The 2020 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Seaside, CA, USA, February 23-25, 2020},
pages = {11--20},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3373087.3375390},
doi = {10.1145/3373087.3375390},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/MatasLGPK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MiedemaSNAMS20,
author = {Rene Miedema and
Georgios Smaragdos and
Mario Negrello and
Zaid Al{-}Ars and
Matthias M{\"{o}}ller and
Christos Strydis},
editor = {Stephen Neuendorffer and
Lesley Shannon},
title = {Synthesis-Free, Flexible and Fast Hardware Library for Biophysically
Plausible Neurosimulations},
booktitle = {{FPGA} '20: The 2020 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Seaside, CA, USA, February 23-25, 2020},
pages = {319},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3373087.3375374},
doi = {10.1145/3373087.3375374},
timestamp = {Wed, 04 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MiedemaSNAMS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MokriALH20,
author = {Parnian Mokri and
Maziar Amiraskari and
Yuelin Liu and
Mark Hempstead},
editor = {Stephen Neuendorffer and
Lesley Shannon},
title = {Early-stage Automated Identification of Similar Hardware Implementations
with Abstract-Syntax-Tree},
booktitle = {{FPGA} '20: The 2020 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Seaside, CA, USA, February 23-25, 2020},
pages = {312},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3373087.3375376},
doi = {10.1145/3373087.3375376},
timestamp = {Wed, 04 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MokriALH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/PortE20,
author = {Oron Port and
Yoav Etsion},
editor = {Stephen Neuendorffer and
Lesley Shannon},
title = {Hardware Description Beyond Register-Transfer Level Languages},
booktitle = {{FPGA} '20: The 2020 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Seaside, CA, USA, February 23-25, 2020},
pages = {312},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3373087.3375377},
doi = {10.1145/3373087.3375377},
timestamp = {Wed, 04 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/PortE20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/RybalkinW20,
author = {Vladimir Rybalkin and
Norbert Wehn},
editor = {Stephen Neuendorffer and
Lesley Shannon},
title = {When Massive {GPU} Parallelism Ain't Enough: {A} Novel Hardware Architecture
of 2D-LSTM Neural Network},
booktitle = {{FPGA} '20: The 2020 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Seaside, CA, USA, February 23-25, 2020},
pages = {111--121},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3373087.3375301},
doi = {10.1145/3373087.3375301},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/RybalkinW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/TineELVK20,
author = {Blaise Tine and
Fares Elsabbagh and
Seyong Lee and
Jeffrey S. Vetter and
Hyesoon Kim},
editor = {Stephen Neuendorffer and
Lesley Shannon},
title = {Cash: {A} Single-Source Hardware-Software Codesign Framework for Rapid
Prototyping},
booktitle = {{FPGA} '20: The 2020 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Seaside, CA, USA, February 23-25, 2020},
pages = {321},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3373087.3375340},
doi = {10.1145/3373087.3375340},
timestamp = {Wed, 04 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/TineELVK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/TineLVK20,
author = {Blaise Tine and
Seyong Lee and
Jeffrey S. Vetter and
Hyesoon Kim},
editor = {Stephen Neuendorffer and
Lesley Shannon},
title = {Productive Hardware Designs using Hybrid {HLS-RTL} Development},
booktitle = {{FPGA} '20: The 2020 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Seaside, CA, USA, February 23-25, 2020},
pages = {311},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3373087.3375338},
doi = {10.1145/3373087.3375338},
timestamp = {Wed, 04 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/TineLVK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/HaghiAPDHM20,
author = {Abbas Haghi and
Lluc Alvarez and
Jord{\`{a}} Polo and
Dionysios Diamantopoulos and
Christoph Hagleitner and
Miquel Moret{\'{o}}},
editor = {Nele Mentens and
Leonel Sousa and
Pedro Trancoso and
Miquel Peric{\`{a}}s and
Ioannis Sourdis},
title = {A Hardware/Software Co-Design of K-mer Counting Using a CAPI-Enabled
{FPGA}},
booktitle = {30th International Conference on Field-Programmable Logic and Applications,
{FPL} 2020, Gothenburg, Sweden, August 31 - September 4, 2020},
pages = {57--64},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/FPL50879.2020.00020},
doi = {10.1109/FPL50879.2020.00020},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/HaghiAPDHM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/MahmoudHS20,
author = {Dina G. Mahmoud and
Wei Hu and
Mirjana Stojilovic},
editor = {Nele Mentens and
Leonel Sousa and
Pedro Trancoso and
Miquel Peric{\`{a}}s and
Ioannis Sourdis},
title = {X-Attack: Remote Activation of Satisfiability Don't-Care Hardware
Trojans on Shared FPGAs},
booktitle = {30th International Conference on Field-Programmable Logic and Applications,
{FPL} 2020, Gothenburg, Sweden, August 31 - September 4, 2020},
pages = {185--192},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/FPL50879.2020.00039},
doi = {10.1109/FPL50879.2020.00039},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/MahmoudHS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/SkarmanG0K20,
author = {Frans Skarman and
Oscar Gustafsson and
Daniel Jung and
Mattias Krysander},
editor = {Nele Mentens and
Leonel Sousa and
Pedro Trancoso and
Miquel Peric{\`{a}}s and
Ioannis Sourdis},
title = {Acceleration of Simulation Models Through Automatic Conversion to
{FPGA} Hardware},
booktitle = {30th International Conference on Field-Programmable Logic and Applications,
{FPL} 2020, Gothenburg, Sweden, August 31 - September 4, 2020},
pages = {359--360},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/FPL50879.2020.00068},
doi = {10.1109/FPL50879.2020.00068},
timestamp = {Sat, 17 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/SkarmanG0K20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fruct/AntonovBF20,
author = {Alexander P. Antonov and
Denis Besedin and
Alexey S. Filippov},
title = {Research of the Efficiency of High-level Synthesis Tool for {FPGA}
Based Hardware Implementation of Some Basic Algorithms for the Big
Data Analysis and Management Tasks},
booktitle = {26th Conference of Open Innovations Association, {FRUCT} 2020, Yaroslavl,
Russia, April 20-24, 2020},
pages = {1--7},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.23919/FRUCT48808.2020.9087355},
doi = {10.23919/FRUCT48808.2020.9087355},
timestamp = {Mon, 16 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fruct/AntonovBF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/i2mtc/Dai0YZY20,
author = {Xuefeng Dai and
Jun Gu and
Peng Ye and
Yu Zhao and
Kuojun Yang},
title = {{FPGA} Realization of Hardware-Flexible Parallel Structure {FIR} Filters
Using Combined Systolic Arrays},
booktitle = {2020 {IEEE} International Instrumentation and Measurement Technology
Conference, {I2MTC} 2020, Dubrovnik, Croatia, May 25-28, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/I2MTC43012.2020.9129340},
doi = {10.1109/I2MTC43012.2020.9129340},
timestamp = {Fri, 16 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/i2mtc/Dai0YZY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icaart/WiemM20,
author = {Belhedi Wiem and
Hannachi Marwa},
editor = {Ana Paula Rocha and
Luc Steels and
H. Jaap van den Herik},
title = {Supervised Hardware/Software Partitioning Algorithms for FPGA-based
Applications},
booktitle = {Proceedings of the 12th International Conference on Agents and Artificial
Intelligence, {ICAART} 2020, Volume 2, Valletta, Malta, February 22-24,
2020},
pages = {860--864},
publisher = {{SCITEPRESS}},
year = {2020},
url = {https://doi.org/10.5220/0009149708600864},
doi = {10.5220/0009149708600864},
timestamp = {Tue, 06 Jun 2023 14:58:01 +0200},
biburl = {https://dblp.org/rec/conf/icaart/WiemM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icarcv/KopczynskiG20,
author = {Maciej Kopczynski and
Tomasz Grzes},
title = {Parallelized Hardware Rough Set Processor Architecture in {FPGA} for
Core Calculation in Big Datasets},
booktitle = {16th International Conference on Control, Automation, Robotics and
Vision, {ICARCV} 2020, Shenzhen, China, December 13-15, 2020},
pages = {1098--1103},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICARCV50220.2020.9305402},
doi = {10.1109/ICARCV50220.2020.9305402},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icarcv/KopczynskiG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icce-berlin/ColangeloSSM20,
author = {Philip Colangelo and
Oren Segal and
Alexander Speicher and
Martin Margala},
title = {Automated Hardware and Neural Network Architecture co-design of {FPGA}
accelerators using multi-objective Neural Architecture Search},
booktitle = {10th {IEEE} International Conference on Consumer Electronics, ICCE-Berlin
2020, Berlin, Germany, November 9-11, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICCE-Berlin50680.2020.9352153},
doi = {10.1109/ICCE-BERLIN50680.2020.9352153},
timestamp = {Fri, 26 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icce-berlin/ColangeloSSM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icfpt/KwadjoMB20,
author = {Danielle Tchuinkou Kwadjo and
Joel Mandebi Mbongue and
Christophe Bobda},
title = {Performance Exploration on Pre-implemented {CNN} Hardware Accelerator
on {FPGA}},
booktitle = {International Conference on Field-Programmable Technology, {(IC)FPT}
2020, Maui, HI, USA, December 9-11, 2020},
pages = {298--299},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICFPT51103.2020.00055},
doi = {10.1109/ICFPT51103.2020.00055},
timestamp = {Tue, 11 May 2021 10:41:35 +0200},
biburl = {https://dblp.org/rec/conf/icfpt/KwadjoMB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icm2/ChetanMLS20,
author = {S. Chetan and
J. Manikandan and
V. Lekshmi and
S. Sudhakar},
title = {Hardware Implementation of Floating Point Matrix Inversion Modules
on FPGAs},
booktitle = {32nd International Conference on Microelectronics, {ICM} 2020, Aqaba,
Jordan, December 14-17, 2020},
pages = {1--4},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICM50269.2020.9331796},
doi = {10.1109/ICM50269.2020.9331796},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icm2/ChetanMLS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icm2/ShattaAAADHH20,
author = {Maha Shatta and
Ihab Adly and
Hassanein H. Amer and
Gehad I. Alkady and
Ramez M. Daoud and
Sahar Hamed and
Shahenda Hatem},
title = {FPGA-based Architectures to Recover from Hardware Trojan Horses, Single
Event Upsets and Hard Failures},
booktitle = {32nd International Conference on Microelectronics, {ICM} 2020, Aqaba,
Jordan, December 14-17, 2020},
pages = {1--4},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICM50269.2020.9331812},
doi = {10.1109/ICM50269.2020.9331812},
timestamp = {Mon, 01 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icm2/ShattaAAADHH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icta3/LiuW0020,
author = {Ye Liu and
Yin Wang and
Liang Chang and
Jun Zhou},
title = {A Fast and Efficient FPGA-based Level Set Hardware Accelerator for
Image Segmentation},
booktitle = {2020 {IEEE} International Conference on Integrated Circuits, Technologies
and Applications, {ICTA} 2020, Nanjing, China, November 23-25, 2020},
pages = {61--62},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICTA50426.2020.9331957},
doi = {10.1109/ICTA50426.2020.9331957},
timestamp = {Mon, 06 Nov 2023 08:21:32 +0100},
biburl = {https://dblp.org/rec/conf/icta3/LiuW0020.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icton/LeeHW20,
author = {Jeonghun Lee and
Jiayuan He and
Ke Wang},
title = {Neural Networks and {FPGA} Hardware Accelerators for Millimeter-Wave
Radio-over-Fiber Systems},
booktitle = {22nd International Conference on Transparent Optical Networks, {ICTON}
2020, Bari, Italy, July 19-23, 2020},
pages = {1--4},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICTON51198.2020.9203559},
doi = {10.1109/ICTON51198.2020.9203559},
timestamp = {Fri, 07 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icton/LeeHW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipccc/BawejaRDH20,
author = {Randeep S. Baweja and
Devin Ridge and
Harpreet S. Dhillon and
William C. Headley},
title = {{FPGA} Implementation of a Pseudo-Random Signal Generator for {RF}
Hardware Test and Evaluation},
booktitle = {39th {IEEE} International Performance Computing and Communications
Conference, {IPCCC} 2020, Austin, TX, USA, November 6-8, 2020},
pages = {1--7},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/IPCCC50635.2020.9391555},
doi = {10.1109/IPCCC50635.2020.9391555},
timestamp = {Wed, 14 Apr 2021 10:06:40 +0200},
biburl = {https://dblp.org/rec/conf/ipccc/BawejaRDH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/FiscalettiSSSS20,
author = {Giorgia Fiscaletti and
Marco Speziali and
Luca Stornaiuolo and
Marco D. Santambrogio and
Donatella Sciuto},
title = {Hardware resources analysis of BNNs splitting for FARD-based multi-FPGAs
Distributed Systems},
booktitle = {2020 {IEEE} International Parallel and Distributed Processing Symposium
Workshops, {IPDPSW} 2020, New Orleans, LA, USA, May 18-22, 2020},
pages = {135--138},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/IPDPSW50202.2020.00030},
doi = {10.1109/IPDPSW50202.2020.00030},
timestamp = {Wed, 05 Aug 2020 14:05:53 +0200},
biburl = {https://dblp.org/rec/conf/ipps/FiscalettiSSSS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/AhmadPR20,
author = {Afzal Ahmad and
Muhammad Adeel Pasha and
Ghulam Jilani Raza},
title = {Accelerating Tiny YOLOv3 using FPGA-Based Hardware/Software Co-Design},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9180843},
doi = {10.1109/ISCAS45731.2020.9180843},
timestamp = {Thu, 21 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/AhmadPR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DinelliMRF20,
author = {Gianmarco Dinelli and
Gabriele Meoni and
Emilio Rapuano and
Luca Fanucci},
title = {Advantages and Limitations of Fully on-Chip {CNN} FPGA-Based Hardware
Accelerator},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9180867},
doi = {10.1109/ISCAS45731.2020.9180867},
timestamp = {Mon, 18 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/DinelliMRF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GrycelW20,
author = {Jacob T. Grycel and
Robert J. Walls},
title = {{DRAB-LOCUS:} An Area-Efficient {AES} Architecture for Hardware Accelerator
Co-Location on FPGAs},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9181186},
doi = {10.1109/ISCAS45731.2020.9181186},
timestamp = {Mon, 18 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/GrycelW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MadsenTP20,
author = {Anne K. Madsen and
Michael Scott Trimboli and
Darshika G. Perera},
title = {An Optimized FPGA-Based Hardware Accelerator for Physics-Based {EKF}
for Battery Cell Management},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9181073},
doi = {10.1109/ISCAS45731.2020.9181073},
timestamp = {Tue, 20 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/MadsenTP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WangCXZ20,
author = {Hao Wang and
Shan Cao and
Shugong Xu and
Shunqing Zhang},
title = {Hardware-Software Co-Design for Face Recognition on {FPGA} SoCs},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9180922},
doi = {10.1109/ISCAS45731.2020.9180922},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/WangCXZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscc/PengMGGT20,
author = {Ping Peng and
Cunqing Ma and
Jingquan Ge and
Neng Gao and
Chenyang Tu},
title = {A Hardware/Software Collaborative {SM4} Implementation Resistant to
Side-channel Attacks on {ARM-FPGA} Embedded SoC},
booktitle = {{IEEE} Symposium on Computers and Communications, {ISCC} 2020, Rennes,
France, July 7-10, 2020},
pages = {1--7},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCC50000.2020.9219591},
doi = {10.1109/ISCC50000.2020.9219591},
timestamp = {Mon, 19 Oct 2020 11:52:22 +0200},
biburl = {https://dblp.org/rec/conf/iscc/PengMGGT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/ChenFC20,
author = {Yu{-}Hsiang Chen and
Chih{-}Peng Fan and
Robert Chen{-}Hao Chang},
title = {Prototype of Low Complexity {CNN} Hardware Accelerator with FPGA-based
{PYNQ} Platform for Dual-Mode Biometrics Recognition},
booktitle = {International SoC Design Conference, {ISOCC} 2020, Yeosu, South Korea,
October 21-24, 2020},
pages = {189--190},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISOCC50952.2020.9333049},
doi = {10.1109/ISOCC50952.2020.9333049},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isocc/ChenFC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ZhangWMW20,
author = {Hui Zhang and
Wei Wu and
Yufei Ma and
Zhongfeng Wang},
title = {Efficient Hardware Post Processing of Anchor-Based Object Detection
on {FPGA}},
booktitle = {2020 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2020,
Limassol, Cyprus, July 6-8, 2020},
pages = {580--585},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISVLSI49217.2020.00089},
doi = {10.1109/ISVLSI49217.2020.00089},
timestamp = {Wed, 07 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/ZhangWMW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/kka/Wojtulewicz20,
author = {Andrzej Wojtulewicz},
editor = {Andrzej Bartoszewicz and
Jacek Kabzinski and
Janusz Kacprzyk},
title = {Hardware Accelerators for Fast Implementation of {DMC} and {GPC} Control
Algorithms Using {FPGA} and Their Applications to a Servomotor},
booktitle = {Advanced, Contemporary Control - Proceedings of {KKA} 2020 - The 20th
Polish Control Conference, {\L}{\'{o}}d{\'{z}}, Poland,
2020},
series = {Advances in Intelligent Systems and Computing},
volume = {1196},
pages = {1079--1091},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-50936-1\_90},
doi = {10.1007/978-3-030-50936-1\_90},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/kka/Wojtulewicz20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/niles/GadAAM20,
author = {Ali H. Gad and
Seif Eldeen E. Abdalazeem and
Omar A. Abdelmegid and
Hassan Mostafa},
title = {Low power and area {SHA-256} hardware accelerator on Virtex-7 {FPGA}},
booktitle = {2nd Novel Intelligent and Leading Emerging Sciences Conference, {NILES}
2020, Giza, Egypt, October 24-26, 2020},
pages = {181--185},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/NILES50944.2020.9257922},
doi = {10.1109/NILES50944.2020.9257922},
timestamp = {Fri, 27 Nov 2020 11:51:07 +0100},
biburl = {https://dblp.org/rec/conf/niles/GadAAM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/norchip/LiuWWLHYHZ020,
author = {Lizheng Liu and
Deyu Wang and
Yuning Wang and
Anders Lansner and
Ahmed Hemani and
Yu Yang and
Xiaoming Hu and
Zhuo Zou and
Lirong Zheng},
editor = {Jari Nurmi and
Dag T. Wisland and
Snorre Aunet and
Kristian Kjelgaard},
title = {A FPGA-based Hardware Accelerator for Bayesian Confidence Propagation
Neural Network},
booktitle = {{IEEE} Nordic Circuits and Systems Conference, NorCAS 2020, Oslo,
Norway, October 27-28, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/NorCAS51424.2020.9265129},
doi = {10.1109/NORCAS51424.2020.9265129},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/norchip/LiuWWLHYHZ020.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/norchip/WulfWG20,
author = {Cornelia Wulf and
Michael Willig and
Diana G{\"{o}}hringer},
editor = {Jari Nurmi and
Dag T. Wisland and
Snorre Aunet and
Kristian Kjelgaard},
title = {Low Power Scheduling of Periodic Hardware Tasks in Flash-Based FPGAs},
booktitle = {{IEEE} Nordic Circuits and Systems Conference, NorCAS 2020, Oslo,
Norway, October 27-28, 2020},
pages = {1--7},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/NorCAS51424.2020.9265128},
doi = {10.1109/NORCAS51424.2020.9265128},
timestamp = {Thu, 03 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/norchip/WulfWG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ross-ws/HeinzHS020,
author = {Carsten Heinz and
Jaco A. Hofmann and
Lukas Sommer and
Andreas Koch},
title = {Improving Job Launch Rates in the TaPaSCo {FPGA} Middleware by Hardware/Software-Co-Design},
booktitle = {2020 {IEEE/ACM} International Workshop on Runtime and Operating Systems
for Supercomputers, ROSS@SC 2020, Atlanta, GA, USA, November 13, 2020},
pages = {22--30},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ROSS51935.2020.00008},
doi = {10.1109/ROSS51935.2020.00008},
timestamp = {Fri, 30 Apr 2021 12:35:40 +0200},
biburl = {https://dblp.org/rec/conf/ross-ws/HeinzHS020.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rsp/MoreacABHD20,
author = {Erwan Mor{\'{e}}ac and
El Mehdi Abdali and
Fran{\c{c}}ois Berry and
Dominique Heller and
Jean{-}Philippe Diguet},
title = {Hardware-in-the-loop simulation with dynamic partial {FPGA} reconfiguration
applied to computer vision in ROS-based {UAV}},
booktitle = {International Workshop on Rapid System Prototyping, {RSP} 2020, Hamburg,
Germany, September 24-25, 2020},
pages = {1--7},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/RSP51120.2020.9244863},
doi = {10.1109/RSP51120.2020.9244863},
timestamp = {Tue, 10 Nov 2020 11:00:25 +0100},
biburl = {https://dblp.org/rec/conf/rsp/MoreacABHD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sadasc/AtibiBABT20,
author = {Mohamed Atibi and
Mohamed Boussaa and
Issam Atouf and
Abdellatif Bennis and
Mohamed Tabaa},
editor = {Mohamed Hamlich and
Ladjel Bellatreche and
Anirban Mondal and
Carlos Ordonez},
title = {Hardware Implementation of Roadway Classification System in {FPGA}
Platform},
booktitle = {Smart Applications and Data Analysis - Third International Conference,
{SADASC} 2020, Marrakesh, Morocco, June 25-26, 2020, Proceedings},
series = {Communications in Computer and Information Science},
volume = {1207},
pages = {200--208},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-45183-7\_15},
doi = {10.1007/978-3-030-45183-7\_15},
timestamp = {Thu, 08 Apr 2021 08:50:56 +0200},
biburl = {https://dblp.org/rec/conf/sadasc/AtibiBABT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/MenezesHCN20,
author = {N{\'{a}}gila Ribeiro de Menezes and
Hugo Daniel Hern{\'{a}}ndez and
Dionisio Carvalho and
Wilhelmus A. M. Van Noije},
title = {All-digital FPGA-based {RF} pulsed transmitter with hardware complexity
reduction techniques},
booktitle = {33rd Symposium on Integrated Circuits and Systems Design, {SBCCI}
2020, Campinas, Brazil, August 24-28, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/SBCCI50935.2020.9189929},
doi = {10.1109/SBCCI50935.2020.9189929},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/MenezesHCN20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smartcloud/SteinertKWUS20,
author = {Fritjof Steinert and
Philipp Kreowsky and
Eric L. Wisotzky and
Christian Unger and
Benno Stabernack},
title = {A Hardware/Software Framework for the Integration of FPGA-based Accelerators
into Cloud Computing Infrastructures},
booktitle = {{IEEE} International Conference on Smart Cloud, SmartCloud 2020, Washington,
DC, USA, November 6-8, 2020},
pages = {23--28},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/SmartCloud49737.2020.00014},
doi = {10.1109/SMARTCLOUD49737.2020.00014},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/smartcloud/SteinertKWUS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/GaoWAL20,
author = {Jia{-}Bao Gao and
Jian Wang and
Md Tanvir Arafin and
Jin{-}Mei Lai},
title = {{FABLE-DTS:} Hardware-Software Co-Design of a Fast and Stable Data
Transmission System for FPGAs},
booktitle = {33rd {IEEE} International System-on-Chip Conference, SoCC 2020, Las
Vegas, NV, USA, September 8-11, 2020},
pages = {207--212},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/SOCC49529.2020.9524764},
doi = {10.1109/SOCC49529.2020.9524764},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/socc/GaoWAL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/spawc/BenzinODC20,
author = {Andreas Benzin and
Dennis Osterland and
Maksim Dill and
Giuseppe Caire},
title = {Centralized Single {FPGA} Real Time Zero Forcing Massive {MIMO} 5G
Basestation Hardware and Gateware},
booktitle = {21st {IEEE} International Workshop on Signal Processing Advances in
Wireless Communications, {SPAWC} 2020, Atlanta, GA, USA, May 26-29,
2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/SPAWC48557.2020.9154248},
doi = {10.1109/SPAWC48557.2020.9154248},
timestamp = {Tue, 11 Aug 2020 17:06:07 +0200},
biburl = {https://dblp.org/rec/conf/spawc/BenzinODC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChoudhariCCDI20,
author = {Onkar Choudhari and
Marisha Chopade and
Sourabh Chopde and
Swarali Dabhadkar and
Vaishali V. Ingale},
title = {{HARDWARE} {ACCELERATOR:} {IMPLEMENTATION} {OF} {CNN} {ON} {FPGA}
{FOR} {DIGIT} {RECOGNITION}},
booktitle = {2020 24th International Symposium on {VLSI} Design and Test (VDAT),
Bhubaneswar, India, July 23-25, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VDAT50263.2020.9190274},
doi = {10.1109/VDAT50263.2020.9190274},
timestamp = {Tue, 03 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vdat/ChoudhariCCDI20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2001-01955,
author = {Chaoyang Zhu and
Kejie Huang and
Shuyuan Yang and
Ziqi Zhu and
Hejia Zhang and
Haibin Shen},
title = {An Efficient Hardware Accelerator for Structured Sparse Convolutional
Neural Networks on FPGAs},
journal = {CoRR},
volume = {abs/2001.01955},
year = {2020},
url = {http://arxiv.org/abs/2001.01955},
eprinttype = {arXiv},
eprint = {2001.01955},
timestamp = {Mon, 13 Jan 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2001-01955.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2005-07332,
author = {Dillon Staub and
Rashmi Jha and
David Kapp},
title = {A CRISPR-Cas-Inspired Mechanism for Detecting Hardware Trojans in
{FPGA} Devices},
journal = {CoRR},
volume = {abs/2005.07332},
year = {2020},
url = {https://arxiv.org/abs/2005.07332},
eprinttype = {arXiv},
eprint = {2005.07332},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2005-07332.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2007-10560,
author = {Zhaoxiong Yang and
Shuihai Hu and
Kai Chen},
title = {FPGA-Based Hardware Accelerator of Homomorphic Encryption for Efficient
Federated Learning},
journal = {CoRR},
volume = {abs/2007.10560},
year = {2020},
url = {https://arxiv.org/abs/2007.10560},
eprinttype = {arXiv},
eprint = {2007.10560},
timestamp = {Tue, 28 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2007-10560.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2009-01434,
author = {Zhe Lin and
Wei Zhang and
Sharad Sinha},
title = {Decision Tree Based Hardware Power Monitoring for Run Time Dynamic
Power Management in {FPGA}},
journal = {CoRR},
volume = {abs/2009.01434},
year = {2020},
url = {https://arxiv.org/abs/2009.01434},
eprinttype = {arXiv},
eprint = {2009.01434},
timestamp = {Wed, 16 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2009-01434.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iacr/ElkhatibAM20,
author = {Rami Elkhatib and
Reza Azarderakhsh and
Mehran Mozaffari Kermani},
title = {Efficient and Fast Hardware Architectures for {SIKE} Round 2 on {FPGA}},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {611},
year = {2020},
url = {https://eprint.iacr.org/2020/611},
timestamp = {Thu, 02 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iacr/ElkhatibAM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iacr/GhoshKDL20,
author = {Santosh Ghosh and
Luis S. Kida and
Soham Jayesh Desai and
Reshma Lal},
title = {A {\textgreater}100 Gbps Inline {AES-GCM} Hardware Engine and Protected
{DMA} Transfers between {SGX} Enclave and {FPGA} Accelerator Device},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {178},
year = {2020},
url = {https://eprint.iacr.org/2020/178},
timestamp = {Mon, 11 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iacr/GhoshKDL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:series/lnee/SkliarovaS19,
author = {Iouliia Skliarova and
Valery Sklyarov},
title = {{FPGA-BASED} Hardware Accelerators},
series = {Lecture Notes in Electrical Engineering},
volume = {566},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-20721-2},
doi = {10.1007/978-3-030-20721-2},
isbn = {978-3-030-20720-5},
timestamp = {Fri, 31 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/series/lnee/SkliarovaS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/AdhikariHV19,
author = {Prottay M. Adhikari and
Hossein Hooshyar and
Luigi Vanfretti},
title = {Experimental Quantification of Hardware Requirements for FPGA-Based
Reconfigurable PMUs},
journal = {{IEEE} Access},
volume = {7},
pages = {57527--57538},
year = {2019},
url = {https://doi.org/10.1109/ACCESS.2019.2911916},
doi = {10.1109/ACCESS.2019.2911916},
timestamp = {Fri, 31 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/AdhikariHV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/HussainTSR19,
author = {Ahmed A. Hussain and
Nizar Tayem and
Abdel{-}Hamid Soliman and
Redha M. Radaydeh},
title = {FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source
{DOA} Estimation Algorithms},
journal = {{IEEE} Access},
volume = {7},
pages = {88845--88858},
year = {2019},
url = {https://doi.org/10.1109/ACCESS.2019.2926335},
doi = {10.1109/ACCESS.2019.2926335},
timestamp = {Thu, 08 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/HussainTSR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/LiuLHD19,
author = {Qin Liu and
Tian Liang and
Zhen Huang and
Venkata Dinavahi},
title = {Real-Time FPGA-Based Hardware Neural Network for Fault Detection and
Isolation in More Electric Aircraft},
journal = {{IEEE} Access},
volume = {7},
pages = {159831--159841},
year = {2019},
url = {https://doi.org/10.1109/ACCESS.2019.2950918},
doi = {10.1109/ACCESS.2019.2950918},
timestamp = {Tue, 26 Nov 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/LiuLHD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/MedusIFBM19,
author = {Leandro D. Medus and
Taras Iakymchuk and
Jos{\'{e}} Vicente Franc{\'{e}}s{-}V{\'{\i}}llora and
Manuel Bataller{-}Mompe{\'{a}}n and
Alfredo Rosado Mu{\~{n}}oz},
title = {A Novel Systolic Parallel Hardware Architecture for the {FPGA} Acceleration
of Feedforward Neural Networks},
journal = {{IEEE} Access},
volume = {7},
pages = {76084--76103},
year = {2019},
url = {https://doi.org/10.1109/ACCESS.2019.2920885},
doi = {10.1109/ACCESS.2019.2920885},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/MedusIFBM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/MinatiMMGPMAHGM19,
author = {Ludovico Minati and
Vardan Movsisyan and
Matthew McCormick and
Khachatur Gyozalyan and
Tigran Papazyan and
Hrach Makaryan and
Stefano Aldrigo and
Taron Harutyunyan and
Hayk Ghaltaghchyan and
Chris Mccormick and
Mick Fandrich},
title = {iFLEX: {A} Fully Open-Source, High-Density Field-Programmable Gate
Array (FPGA)-Based Hardware Co-Processor for Vector Similarity Searching},
journal = {{IEEE} Access},
volume = {7},
pages = {112269--112283},
year = {2019},
url = {https://doi.org/10.1109/ACCESS.2019.2934715},
doi = {10.1109/ACCESS.2019.2934715},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/MinatiMMGPMAHGM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/RaviSGS19,
author = {Murali Ravi and
Angu Sewa and
Shashidhar T. G. and
Siva Sankara Sai Sanagapati},
title = {{FPGA} as a Hardware Accelerator for Computation Intensive Maximum
Likelihood Expectation Maximization Medical Image Reconstruction Algorithm},
journal = {{IEEE} Access},
volume = {7},
pages = {111727--111735},
year = {2019},
url = {https://doi.org/10.1109/ACCESS.2019.2932647},
doi = {10.1109/ACCESS.2019.2932647},
timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/RaviSGS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/ZhuZZCZJM19,
author = {Zongwei Zhu and
Junneng Zhang and
Jinjin Zhao and
Jing Cao and
Duan Zhao and
Gangyong Jia and
Qingyong Meng},
title = {A Hardware and Software Task-Scheduling Framework Based on {CPU+FPGA}
Heterogeneous Architecture in Edge Computing},
journal = {{IEEE} Access},
volume = {7},
pages = {148975--148988},
year = {2019},
url = {https://doi.org/10.1109/ACCESS.2019.2943179},
doi = {10.1109/ACCESS.2019.2943179},
timestamp = {Thu, 07 Nov 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/ZhuZZCZJM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cssp/BonnyDME19,
author = {Talal Bonny and
Ridhwan Al Debsi and
Sohaib Majzoub and
Ahmed S. Elwakil},
title = {Hardware Optimized {FPGA} Implementations of High-Speed True Random
Bit Generators Based on Switching-Type Chaotic Oscillators},
journal = {Circuits Syst. Signal Process.},
volume = {38},
number = {3},
pages = {1342--1359},
year = {2019},
url = {https://doi.org/10.1007/s00034-018-0905-6},
doi = {10.1007/S00034-018-0905-6},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cssp/BonnyDME19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/ReddyV19,
author = {Kuladeep Sai Reddy and
Kizheppatt Vipin},
title = {OpenNoC: An Open-Source NoC Infrastructure for FPGA-Based Hardware
Acceleration},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {11},
number = {4},
pages = {123--126},
year = {2019},
url = {https://doi.org/10.1109/LES.2019.2905019},
doi = {10.1109/LES.2019.2905019},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/ReddyV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/RanjbarSPA19,
author = {Omid Ranjbar and
Siavash Bayat Sarmadi and
Fatemeh Pooyan and
Hossein Asadi},
title = {A Unified Approach to Detect and Distinguish Hardware Trojans and
Faults in SRAM-based FPGAs},
journal = {J. Electron. Test.},
volume = {35},
number = {2},
pages = {201--214},
year = {2019},
url = {https://doi.org/10.1007/s10836-019-05783-2},
doi = {10.1007/S10836-019-05783-2},
timestamp = {Fri, 14 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/RanjbarSPA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceee/ZhaoJYWG19,
author = {Jiafei Zhao and
Rongkun Jiang and
Hao Yang and
Xuetian Wang and
Hongmin Gao},
title = {Reconfigurable hardware architecture for Mean Level and log-t {CFAR}
detectors in {FPGA} implementations},
journal = {{IEICE} Electron. Express},
volume = {16},
number = {21},
pages = {20190584},
year = {2019},
url = {https://doi.org/10.1587/elex.16.20190584},
doi = {10.1587/ELEX.16.20190584},
timestamp = {Tue, 18 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieiceee/ZhaoJYWG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/RanawakaETDAS19,
author = {Piyumal Ranawaka and
Mongkol Ekpanyapong and
Adriano Tavares and
Mathew Dailey and
Krit Athikulwongse and
Vitor Alberto Silva},
title = {High Performance Application Specific Stream Architecture for Hardware
Acceleration of {HOG-SVM} on {FPGA}},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {102-A},
number = {12},
pages = {1792--1803},
year = {2019},
url = {https://doi.org/10.1587/transfun.E102.A.1792},
doi = {10.1587/TRANSFUN.E102.A.1792},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/RanawakaETDAS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cds/MoussaBK19,
author = {Intissar Moussa and
Adel Bouallegue and
Adel Khedher},
title = {New wind turbine emulator based on {DC} machine: hardware implementation
using {FPGA} board for an open-loop operation},
journal = {{IET} Circuits Devices Syst.},
volume = {13},
number = {6},
pages = {896--902},
year = {2019},
url = {https://doi.org/10.1049/iet-cds.2018.5530},
doi = {10.1049/IET-CDS.2018.5530},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cds/MoussaBK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cds/PandeyGK19,
author = {Jai Gopal Pandey and
Tarun Goel and
Abhijit Karmakar},
title = {Hardware architectures for {PRESENT} block cipher and their {FPGA}
implementations},
journal = {{IET} Circuits Devices Syst.},
volume = {13},
number = {7},
pages = {958--969},
year = {2019},
url = {https://doi.org/10.1049/iet-cds.2018.5273},
doi = {10.1049/IET-CDS.2018.5273},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cds/PandeyGK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijaac/SirineBF19,
author = {Telmoudi Brini Sirine and
Badreddine Bouzouita and
Faouzi Bouani},
title = {A hardware/software architecture dedicated to model predictive control
law and implemented into an {FPGA} platform},
journal = {Int. J. Autom. Control.},
volume = {13},
number = {3},
pages = {301--323},
year = {2019},
url = {https://doi.org/10.1504/IJAAC.2019.098584},
doi = {10.1504/IJAAC.2019.098584},
timestamp = {Thu, 10 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijaac/SirineBF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijes/PereraL19,
author = {Darshika G. Perera and
Kin Fun Li},
title = {A design methodology for mobile and embedded applications on FPGA-based
dynamic reconfigurable hardware},
journal = {Int. J. Embed. Syst.},
volume = {11},
number = {5},
pages = {661--677},
year = {2019},
url = {https://doi.org/10.1504/IJES.2019.102416},
doi = {10.1504/IJES.2019.102416},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijes/PereraL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijmssc/BenhamadoucheDB19,
author = {Abdelouahab D. Benhamadouche and
Farid Djahli and
Adel Ballouti and
Abdeslem Sahli},
title = {FPGA-based hardware-in-the-loop for multi-domain simulation},
journal = {Int. J. Model. Simul. Sci. Comput.},
volume = {10},
number = {4},
pages = {1950020:1--1950020:18},
year = {2019},
url = {https://doi.org/10.1142/S179396231950020X},
doi = {10.1142/S179396231950020X},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijmssc/BenhamadoucheDB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijrc/DinelliMRBF19,
author = {Gianmarco Dinelli and
Gabriele Meoni and
Emilio Rapuano and
Gionata Benelli and
Luca Fanucci},
title = {An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories
Only: Design and Benchmarking with Intel Movidius Neural Compute Stick},
journal = {Int. J. Reconfigurable Comput.},
volume = {2019},
pages = {7218758:1--7218758:13},
year = {2019},
url = {https://doi.org/10.1155/2019/7218758},
doi = {10.1155/2019/7218758},
timestamp = {Tue, 26 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijrc/DinelliMRBF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iotj/ChenGWLL19,
author = {Zhe Chen and
Shize Guo and
Jian Wang and
Yubai Li and
Zhonghai Lu},
title = {Toward {FPGA} Security in IoT: {A} New Detection Technique for Hardware
Trojans},
journal = {{IEEE} Internet Things J.},
volume = {6},
number = {4},
pages = {7061--7068},
year = {2019},
url = {https://doi.org/10.1109/JIOT.2019.2914079},
doi = {10.1109/JIOT.2019.2914079},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iotj/ChenGWLL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/SamirHKEOYAMSM19,
author = {Nagham Samir and
Abdelrahman Sobeih Hussein and
Mohaned Khaled and
Ahmed N. El{-}Zeiny and
Mahetab Osama and
Heba Yassin and
Ali Abdelbaky and
Omar Mahmoud and
Ahmed Shawky and
Hassan Mostafa},
title = {{ASIC} and {FPGA} Comparative Study for IoT Lightweight Hardware Security
Algorithms},
journal = {J. Circuits Syst. Comput.},
volume = {28},
number = {12},
pages = {1930009:1--1930009:25},
year = {2019},
url = {https://doi.org/10.1142/S0218126619300095},
doi = {10.1142/S0218126619300095},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/SamirHKEOYAMSM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/SugiartoAC19,
author = {Indar Sugiarto and
Cristian Axenie and
J{\"{o}}rg Conradt},
title = {FPGA-Based Hardware Accelerator for an Embedded Factor Graph with
Configurable Optimization},
journal = {J. Circuits Syst. Comput.},
volume = {28},
number = {2},
pages = {1950031:1--1950031:30},
year = {2019},
url = {https://doi.org/10.1142/S0218126619500312},
doi = {10.1142/S0218126619500312},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcsc/SugiartoAC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsm/DeviC019,
author = {D. Indhumathi Devi and
S. Chithra and
M. Sethumadhavan},
title = {Hardware Random Number GeneratorUsing {FPGA}},
journal = {J. Cyber Secur. Mobil.},
volume = {8},
number = {4},
pages = {409--418},
year = {2019},
url = {https://doi.org/10.13052/jcsm2245-1439.841},
doi = {10.13052/JCSM2245-1439.841},
timestamp = {Tue, 16 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcsm/DeviC019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrtip/GeS19,
author = {Hangqi Ge and
Jin Sha},
title = {FPGA-based low-complexity high-throughput real-time hardware accelerator
for robust watermarking},
journal = {J. Real Time Image Process.},
volume = {16},
number = {4},
pages = {813--820},
year = {2019},
url = {https://doi.org/10.1007/s11554-019-00882-x},
doi = {10.1007/S11554-019-00882-X},
timestamp = {Thu, 18 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrtip/GeS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrtip/IbraheemHALG19,
author = {Mohammed Shaaban Ibraheem and
Khalil Hachicha and
Syed Zahid Ahmed and
Laurent Lambert and
Patrick Garda},
title = {High-throughput parallel {DWT} hardware architecture implemented on
an FPGA-based platform},
journal = {J. Real Time Image Process.},
volume = {16},
number = {6},
pages = {2043--2057},
year = {2019},
url = {https://doi.org/10.1007/s11554-017-0711-6},
doi = {10.1007/S11554-017-0711-6},
timestamp = {Thu, 18 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrtip/IbraheemHALG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jvcir/RaoY19,
author = {Perumalla Srinivasa Rao and
Yedukondalu Kamatham},
title = {Hardware implementation of digital image skeletonization algorithm
using {FPGA} for computer vision applications},
journal = {J. Vis. Commun. Image Represent.},
volume = {59},
pages = {140--149},
year = {2019},
url = {https://doi.org/10.1016/j.jvcir.2019.01.004},
doi = {10.1016/J.JVCIR.2019.01.004},
timestamp = {Fri, 30 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jvcir/RaoY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/FournarisPK19,
author = {Apostolos P. Fournaris and
Lampros Pyrgas and
Paris Kitsos},
title = {An efficient multi-parameter approach for {FPGA} hardware Trojan detection},
journal = {Microprocess. Microsystems},
volume = {71},
year = {2019},
url = {https://doi.org/10.1016/j.micpro.2019.102863},
doi = {10.1016/J.MICPRO.2019.102863},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/FournarisPK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pvldb/OwaidaAFHM19,
author = {Muhsen Owaida and
Gustavo Alonso and
Laura Fogliarini and
Anthony Hock{-}Koon and
Pierre{-}Etienne Melet},
title = {Lowering the Latency of Data Processing Pipelines Through {FPGA} based
Hardware Acceleration},
journal = {Proc. {VLDB} Endow.},
volume = {13},
number = {1},
pages = {71--85},
year = {2019},
url = {http://www.vldb.org/pvldb/vol13/p71-owaida.pdf},
doi = {10.14778/3357377.3357383},
timestamp = {Tue, 23 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/pvldb/OwaidaAFHM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ria/KumarNM19,
author = {Kaushal Kumar and
Durgesh Nandan and
Ritesh Kumar Mishra},
title = {Compact Hardware of Running Gaussian Average Algorithm for Moving
Object Detection Realized on {FPGA} and {ASIC}},
journal = {Rev. d'Intelligence Artif.},
volume = {33},
number = {4},
pages = {305--311},
year = {2019},
url = {https://doi.org/10.18280/ria.330407},
doi = {10.18280/RIA.330407},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ria/KumarNM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/saj/RouxSV19,
author = {Rikus le Roux and
George van Schoor and
Pieter A. van Vuuren},
title = {Parsing and analysis of a Xilinx {FPGA} bitstream for generating new
hardware by direct bit manipulation in real-time},
journal = {South Afr. Comput. J.},
volume = {31},
number = {1},
year = {2019},
url = {https://doi.org/10.18489/sacj.v31i1.620},
doi = {10.18489/SACJ.V31I1.620},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/saj/RouxSV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/LiYLMY19,
author = {Jian Li and
Xinlei Yan and
Maojin Li and
Ming Meng and
Xin Yan},
title = {A Method of FPGA-Based Extraction of High-Precision Time-Difference
Information and Implementation of Its Hardware Circuit},
journal = {Sensors},
volume = {19},
number = {23},
pages = {5067},
year = {2019},
url = {https://doi.org/10.3390/s19235067},
doi = {10.3390/S19235067},
timestamp = {Sat, 30 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sensors/LiYLMY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/NakaT19,
author = {Taiki Naka and
Hiroyuki Torikai},
title = {A Novel Generalized Hardware-Efficient Neuron Model Based on Asynchronous
{CA} Dynamics and Its Biologically Plausible On-FPGA Learnings},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {66-II},
number = {7},
pages = {1247--1251},
year = {2019},
url = {https://doi.org/10.1109/TCSII.2018.2876974},
doi = {10.1109/TCSII.2018.2876974},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/NakaT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/WisniewskiBS19,
author = {Remigiusz Wisniewski and
Grzegorz Bazydlo and
Pawel Szczesniak},
title = {Low-Cost {FPGA} Hardware Implementation of Matrix Converter Switch
Control},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {66-II},
number = {7},
pages = {1177--1181},
year = {2019},
url = {https://doi.org/10.1109/TCSII.2018.2875589},
doi = {10.1109/TCSII.2018.2875589},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/WisniewskiBS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tci/ChenHCL19,
author = {Huan{-}Yuan Chen and
Wen{-}Jyi Hwang and
Chau{-}Jern Cheng and
Xin{-}Ji Lai},
title = {An FPGA-Based Autofocusing Hardware Architecture for Digital Holography},
journal = {{IEEE} Trans. Computational Imaging},
volume = {5},
number = {2},
pages = {287--300},
year = {2019},
url = {https://doi.org/10.1109/TCI.2019.2892810},
doi = {10.1109/TCI.2019.2892810},
timestamp = {Fri, 31 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tci/ChenHCL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tinstmc/AkbatiUA19,
author = {Onur Akbati and
Hatice Didem {\"{U}}zg{\"{u}}n and
Sirin Akkaya},
title = {Hardware-in-the-loop simulation and implementation of a fuzzy logic
controller with {FPGA:} case study of a magnetic levitation system},
journal = {Trans. Inst. Meas. Control},
volume = {41},
number = {8},
pages = {2150--2159},
year = {2019},
url = {https://doi.org/10.1177/0142331218813425},
doi = {10.1177/0142331218813425},
timestamp = {Wed, 17 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tinstmc/AkbatiUA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/ReichenbachHHLB19,
author = {Marc Reichenbach and
Philipp Holzinger and
Konrad H{\"{a}}ublein and
Tobias Lieske and
Paul Blinzer and
Dietmar Fey},
title = {Heterogeneous Computing Utilizing FPGAs - {A} New and Flexible Approach
Integrating Dedicated Hardware Accelerators into Common Computing
Platforms},
journal = {J. Signal Process. Syst.},
volume = {91},
number = {7},
pages = {745--757},
year = {2019},
url = {https://doi.org/10.1007/s11265-018-1382-7},
doi = {10.1007/S11265-018-1382-7},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/ReichenbachHHLB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/PeltenburgSBHA19,
author = {Johan Peltenburg and
Jeroen van Straten and
Matthijs Brobbel and
H. Peter Hofstee and
Zaid Al{-}Ars},
editor = {Christian Hochberger and
Brent Nelson and
Andreas Koch and
Roger F. Woods and
Pedro C. Diniz},
title = {Supporting Columnar In-memory Formats on {FPGA:} The Hardware Design
of Fletcher for Apache Arrow},
booktitle = {Applied Reconfigurable Computing - 15th International Symposium, {ARC}
2019, Darmstadt, Germany, April 9-11, 2019, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {11444},
pages = {32--47},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-17227-5\_3},
doi = {10.1007/978-3-030-17227-5\_3},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arc/PeltenburgSBHA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/LiMWZY19,
author = {Yafei Li and
Kuizhi Mei and
Xiao Wang and
Zeng Zhang and
Hejie Yu},
title = {Collaborative Implementation of Hardware-Oriented {GBDT} Compress
Algorithm Based on {DSP+FPGA}},
booktitle = {13th {IEEE} International Conference on ASIC, {ASICON} 2019, Chongqing,
China, October 29 - November 1, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ASICON47005.2019.8983639},
doi = {10.1109/ASICON47005.2019.8983639},
timestamp = {Thu, 13 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asicon/LiMWZY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/ZhaoWN19,
author = {Ziwei Zhao and
Fei Wang and
Qi Ni},
title = {An FPGA-based Hardware Accelerator of {RANSAC} Algorithm for Matching
of Images Feature Points},
booktitle = {13th {IEEE} International Conference on ASIC, {ASICON} 2019, Chongqing,
China, October 29 - November 1, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ASICON47005.2019.8983656},
doi = {10.1109/ASICON47005.2019.8983656},
timestamp = {Wed, 12 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asicon/ZhaoWN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ccece/LedwonC019,
author = {Morgan Ledwon and
Bruce F. Cockburn and
Jie Han},
title = {Design and Evaluation of an FPGA-based Hardware Accelerator for Deflate
Data Decompression},
booktitle = {2019 {IEEE} Canadian Conference of Electrical and Computer Engineering,
{CCECE} 2019, Edmonton, AB, Canada, May 5-8, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/CCECE.2019.8861851},
doi = {10.1109/CCECE.2019.8861851},
timestamp = {Sun, 08 Aug 2021 01:40:48 +0200},
biburl = {https://dblp.org/rec/conf/ccece/LedwonC019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ccs/GrossJZS19,
author = {Mathieu Gross and
Nisha Jacob and
Andreas Zankl and
Georg Sigl},
editor = {Chip{-}Hong Chang and
Ulrich R{\"{u}}hrmair and
Daniel E. Holcomb and
Patrick Schaumont},
title = {Breaking TrustZone Memory Isolation through Malicious Hardware on
a Modern FPGA-SoC},
booktitle = {Proceedings of the 3rd {ACM} Workshop on Attacks and Solutions in
Hardware Security Workshop, ASHES@CCS 2019, London, UK, November 15,
2019},
pages = {3--12},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3338508.3359568},
doi = {10.1145/3338508.3359568},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ccs/GrossJZS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/VazquezGS19,
author = {Ruben Vazquez and
Ann Gordon{-}Ross and
Greg Stitt},
title = {Offloading cache configuration prediction to an {FPGA} for hardware
speedup and overhead reduction: work-in-progress},
booktitle = {Proceedings of the International Conference on Hardware/Software Codesign
and System Synthesis Companion, {CODES+ISSS} 2019, part of {ESWEEK}
2019, New York, NY, USA, October 13-18, 2019},
pages = {11:1--11:2},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3349567.3351730},
doi = {10.1145/3349567.3351730},
timestamp = {Wed, 27 Nov 2019 17:07:16 +0100},
biburl = {https://dblp.org/rec/conf/codes/VazquezGS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coins/StratakosGTEMS19,
author = {Ioannis Stratakos and
Dimitrios Gourounas and
Vasileios Tsoutsouras and
Theodore L. Economopoulos and
George K. Matsopoulos and
Dimitrios Soudris},
editor = {Farshad Firouzi and
Krishnendu Chakrabarty and
Bahar J. Farahani and
Fangming Ye and
Vasilis F. Pavlidis},
title = {Hardware Acceleration of Image Registration Algorithm on FPGA-based
Systems on Chip},
booktitle = {Proceedings of the International Conference on Omni-Layer Intelligent
Systems, {COINS} 2019, Crete, Greece, May 5-7, 2019},
pages = {92--97},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3312614.3312636},
doi = {10.1145/3312614.3312636},
timestamp = {Tue, 31 Aug 2021 08:35:29 +0200},
biburl = {https://dblp.org/rec/conf/coins/StratakosGTEMS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/crisis/ChaouchDDMOB19,
author = {Asma Chaouch and
Fangan{-}Yssouf Dosso and
Laurent{-}St{\'{e}}phane Didier and
Nadia El Mrabet and
Bouraoui Ouni and
Belgacem Bouallegue},
editor = {Slim Kallel and
Fr{\'{e}}d{\'{e}}ric Cuppens and
Nora Cuppens{-}Boulahia and
Ahmed Hadj Kacem},
title = {Hardware Optimization on {FPGA} for the Modular Multiplication in
the {AMNS} Representation},
booktitle = {Risks and Security of Internet and Systems, 14th International Conference,
CRiSIS 2019, Hammamet, Tunisia, October 29-31, 2019, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {12026},
pages = {113--127},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-41568-6\_8},
doi = {10.1007/978-3-030-41568-6\_8},
timestamp = {Tue, 03 Mar 2020 17:17:08 +0100},
biburl = {https://dblp.org/rec/conf/crisis/ChaouchDDMOB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csps/AnCZWZ19,
author = {Junru An and
Zhiwei Cui and
Zhenhui Zhang and
Liji Wu and
Xiangmin Zhang},
editor = {Qilian Liang and
Wei Wang and
Xin Liu and
Zhenyu Na and
Min Jia and
Baoju Zhang},
title = {Research on Temperature Characteristics of IoT Chip Hardware Trojan
Based on {FPGA}},
booktitle = {Communications, Signal Processing, and Systems - Proceedings of the
8th International Conference on Communications, Signal Processing,
and Systems, {CSPS} 2019, Urumqi, China, 20-22 July 2019},
series = {Lecture Notes in Electrical Engineering},
volume = {571},
pages = {1222--1230},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-981-13-9409-6\_145},
doi = {10.1007/978-981-13-9409-6\_145},
timestamp = {Thu, 09 Apr 2020 10:53:46 +0200},
biburl = {https://dblp.org/rec/conf/csps/AnCZWZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dcis/GarciaO19,
author = {Javier Cereijo Garc{\'{\i}}a and
Roberto R. Osorio},
title = {Hardware Implementation of Statecharts for FPGA-based Control in Scientific
Facilities},
booktitle = {{XXXIV} Conference on Design of Circuits and Integrated Systems, {DCIS}
2019, Bilbao, Spain, November 20-22, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/DCIS201949030.2019.8959871},
doi = {10.1109/DCIS201949030.2019.8959871},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dcis/GarciaO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ecrts/PaganiRBMLB19,
author = {Marco Pagani and
Enrico Rossi and
Alessandro Biondi and
Mauro Marinoni and
Giuseppe Lipari and
Giorgio C. Buttazzo},
editor = {Sophie Quinton},
title = {A Bandwidth Reservation Mechanism for AXI-Based Hardware Accelerators
on FPGAs},
booktitle = {31st Euromicro Conference on Real-Time Systems, {ECRTS} 2019, July
9-12, 2019, Stuttgart, Germany},
series = {LIPIcs},
volume = {133},
pages = {24:1--24:24},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2019},
url = {https://doi.org/10.4230/LIPIcs.ECRTS.2019.24},
doi = {10.4230/LIPICS.ECRTS.2019.24},
timestamp = {Sat, 18 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ecrts/PaganiRBMLB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/ErbagciAEM19,
author = {Burak Erbagci and
Nail Etkin Can Akkaya and
Cagri Erbagci and
Ken Mai},
title = {An Inherently Secure {FPGA} using {PUF} Hardware-Entanglement and
Side-Channel Resistant Logic in 65nm Bulk {CMOS}},
booktitle = {45th {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2019,
Cracow, Poland, September 23-26, 2019},
pages = {65--68},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ESSCIRC.2019.8902789},
doi = {10.1109/ESSCIRC.2019.8902789},
timestamp = {Tue, 26 Nov 2019 11:02:52 +0100},
biburl = {https://dblp.org/rec/conf/esscirc/ErbagciAEM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eucnc/ChiotakisPP19,
author = {Spyros Chiotakis and
S{\'{e}}bastien Pinneterre and
Michele Paolino},
title = {vFPGAmanager: {A} Hardware-Software Framework for Optimal {FPGA} Resources
Exploitation in Network Function Virtualization},
booktitle = {European Conference on Networks and Communications, EuCNC 2019, Valencia,
Spain, June 18-21, 2019},
pages = {47--51},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/EuCNC.2019.8802043},
doi = {10.1109/EUCNC.2019.8802043},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/eucnc/ChiotakisPP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/GuoLR0C19,
author = {Licheng Guo and
Jason Lau and
Zhenyuan Ruan and
Peng Wei and
Jason Cong},
title = {Hardware Acceleration of Long Read Pairwise Overlapping in Genome
Sequencing: {A} Race Between {FPGA} and {GPU}},
booktitle = {27th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2019, San Diego, CA, USA, April 28 - May
1, 2019},
pages = {127--135},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/FCCM.2019.00027},
doi = {10.1109/FCCM.2019.00027},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fccm/GuoLR0C19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/LuXHZL019,
author = {Liqiang Lu and
Jiaming Xie and
Ruirui Huang and
Jiansong Zhang and
Wei Lin and
Yun Liang},
title = {An Efficient Hardware Accelerator for Sparse Convolutional Neural
Networks on FPGAs},
booktitle = {27th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2019, San Diego, CA, USA, April 28 - May
1, 2019},
pages = {17--25},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/FCCM.2019.00013},
doi = {10.1109/FCCM.2019.00013},
timestamp = {Mon, 12 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fccm/LuXHZL019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/CoughlinCWKW19,
author = {Aimee Coughlin and
Greg Cusack and
Jack Wampler and
Eric Keller and
Eric Wustrow},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Breaking the Trust Dependence on Third Party Processes for Reconfigurable
Secure Hardware},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {282--291},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293895},
doi = {10.1145/3289602.3293895},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/CoughlinCWKW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GuYSPFXW19,
author = {Yanjie Gu and
Jian Yu and
Tieli Sun and
Chen Pan and
Zhenhao Feng and
Liewei Xu and
Chang Wu},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Highly Efficient Sparse Neural Network Computing: Hardware and Software
Solutions},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {121},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293952},
doi = {10.1145/3289602.3293952},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/GuYSPFXW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HeKZ19,
author = {Xin He and
Liu Ke and
Xuan Zhang},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {SparseBNN: Joint Algorithm/Hardware Optimization to Exploit Structured
Sparsity in Binary Neural Network},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {117--118},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293937},
doi = {10.1145/3289602.3293937},
timestamp = {Thu, 02 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/HeKZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KapralosC19,
author = {Michael P. Kapralos and
John A. Chandy},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {HOTMeTaL: Hardware Optimization Tool for Memory Table and Logic Conversion},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {307--308},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3294000},
doi = {10.1145/3289602.3294000},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/KapralosC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ShererFLL19,
author = {Zachary Sherer and
Eric Finnerty and
Yan Luo and
Hang Liu},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Software Hardware Co-Optimized {BFS} on FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {190},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293982},
doi = {10.1145/3289602.3293982},
timestamp = {Fri, 21 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ShererFLL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YangHWZ0GBLVWK19,
author = {Yifan Yang and
Qijing Huang and
Bichen Wu and
Tianjun Zhang and
Liang Ma and
Giulio Gambardella and
Michaela Blott and
Luciano Lavagno and
Kees A. Vissers and
John Wawrzynek and
Kurt Keutzer},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on
Embedded FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {23--32},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293902},
doi = {10.1145/3289602.3293902},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/YangHWZ0GBLVWK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/AgrawalBEK19,
author = {Rashmi S. Agrawal and
Lake Bu and
Alan Ehret and
Michel A. Kinsy},
editor = {Ioannis Sourdis and
Christos{-}Savvas Bouganis and
Carlos {\'{A}}lvarez and
Leonel Antonio Toledo D{\'{\i}}az and
Pedro Valero{-}Lara and
Xavier Martorell},
title = {Open-Source {FPGA} Implementation of Post-Quantum Cryptographic Hardware
Primitives},
booktitle = {29th International Conference on Field Programmable Logic and Applications,
{FPL} 2019, Barcelona, Spain, September 8-12, 2019},
pages = {211--217},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/FPL.2019.00040},
doi = {10.1109/FPL.2019.00040},
timestamp = {Tue, 26 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/AgrawalBEK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/HuTSRSMSS19,
author = {Bo Hu and
Jingxiang Tian and
Mustafa M. Shihab and
Gaurav Rajavendra Reddy and
William Swartz and
Yiorgos Makris and
Benjamin Carri{\'{o}}n Sch{\"{a}}fer and
Carl Sechen},
editor = {Houman Homayoun and
Baris Taskin and
Tinoosh Mohsenin and
Weisheng Zhao},
title = {Functional Obfuscation of Hardware Accelerators through Selective
Partial Design Extraction onto an Embedded {FPGA}},
booktitle = {Proceedings of the 2019 on Great Lakes Symposium on VLSI, {GLSVLSI}
2019, Tysons Corner, VA, USA, May 9-11, 2019},
pages = {171--176},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3299874.3317992},
doi = {10.1145/3299874.3317992},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/HuTSRSMSS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/KagawaIN19,
author = {Hiroshi Kagawa and
Yasuaki Ito and
Koji Nakano},
title = {Throughput-Optimal Hardware Implementation of {LZW} Decompression
on the {FPGA}},
booktitle = {Seventh International Symposium on Computing and Networking Workshops,
{CANDAR} 2019 Workshops, Nagasaki, Japan, November 26-29, 2019},
pages = {78--83},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/CANDARW.2019.00022},
doi = {10.1109/CANDARW.2019.00022},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/KagawaIN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/GeGTXL19,
author = {Jingquan Ge and
Neng Gao and
Chenyang Tu and
Ji Xiang and
Zeyi Liu},
title = {AdapTimer: Hardware/Software Collaborative Timer Resistant to Flush-Based
Cache Attacks on {ARM-FPGA} Embedded SoC},
booktitle = {37th {IEEE} International Conference on Computer Design, {ICCD} 2019,
Abu Dhabi, United Arab Emirates, November 17-20, 2019},
pages = {585--593},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ICCD46524.2019.00085},
doi = {10.1109/ICCD46524.2019.00085},
timestamp = {Tue, 18 Feb 2020 15:29:20 +0100},
biburl = {https://dblp.org/rec/conf/iccd/GeGTXL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icce-tw/ChangF19,
author = {Keng{-}Chia Chang and
Chih{-}Peng Fan},
title = {Cost-Efficient Adaboost-based Face Detection with {FPGA} Hardware
Accelerator},
booktitle = {{IEEE} International Conference on Consumer Electronics - Taiwan,
{ICCE-TW} 2019, Yilan, Taiwan, May 20-22, 2019},
pages = {1--2},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ICCE-TW46550.2019.8991862},
doi = {10.1109/ICCE-TW46550.2019.8991862},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icce-tw/ChangF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/ShinOH19,
author = {Duckgyu Shin and
Naoya Onizawa and
Takahiro Hanyu},
title = {{FPGA} Implementation of Binarized Perceptron Learning Hardware Using
{CMOS} Invertible Logic},
booktitle = {26th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2019, Genoa, Italy, November 27-29, 2019},
pages = {115--116},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ICECS46596.2019.8965097},
doi = {10.1109/ICECS46596.2019.8965097},
timestamp = {Mon, 03 Feb 2020 12:19:05 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/ShinOH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icfpt/LuoX19,
author = {Yukui Luo and
Xiaolin Xu},
title = {{HILL:} {A} Hardware Isolation Framework Against Information Leakage
on Multi-Tenant {FPGA} Long-Wires},
booktitle = {International Conference on Field-Programmable Technology, {FPT} 2019,
Tianjin, China, December 9-13, 2019},
pages = {331--334},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ICFPT47387.2019.00060},
doi = {10.1109/ICFPT47387.2019.00060},
timestamp = {Mon, 17 Feb 2020 13:32:10 +0100},
biburl = {https://dblp.org/rec/conf/icfpt/LuoX19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icfpt/TianPN19,
author = {Ye Tian and
Jean{-}Christophe Pr{\'{e}}votet and
Fabienne Nouvel},
title = {Efficient {OS} Hardware Accelerators Preemption Management in {FPGA}},
booktitle = {International Conference on Field-Programmable Technology, {FPT} 2019,
Tianjin, China, December 9-13, 2019},
pages = {367--370},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ICFPT47387.2019.00069},
doi = {10.1109/ICFPT47387.2019.00069},
timestamp = {Mon, 28 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icfpt/TianPN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icm2/HarethMS19,
author = {Sherry Hareth and
Hassan Mostafa and
Khaled Ali Shehata},
title = {Low power {CNN} hardware {FPGA} implementation},
booktitle = {31st International Conference on Microelectronics, {ICM} 2019, Cairo,
Egypt, December 15-18, 2019},
pages = {162--165},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ICM48031.2019.9021904},
doi = {10.1109/ICM48031.2019.9021904},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icm2/HarethMS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icvs/ScharfVLRTVVG19,
author = {Dietmar Scharf and
Bach Le Viet and
Thi Bich Hoa Le and
Janine Rechenberg and
Stefan Tschierschke and
Ernst Vogl and
Ambra Vandone and
Mattia Giardini},
editor = {Dimitrios Tzovaras and
Dimitrios Giakoumis and
Markus Vincze and
Antonis A. Argyros},
title = {Hardware Accelerated Image Processing on an FPGA-SoC Based Vision
System for Closed Loop Monitoring and Additive Manufacturing Process
Control},
booktitle = {Computer Vision Systems, 12th International Conference, {ICVS} 2019,
Thessaloniki, Greece, September 23-25, 2019, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {11754},
pages = {3--12},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-34995-0\_1},
doi = {10.1007/978-3-030-34995-0\_1},
timestamp = {Wed, 27 Nov 2019 09:42:33 +0100},
biburl = {https://dblp.org/rec/conf/icvs/ScharfVLRTVVG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/GizopoulosPCR0U19,
author = {Dimitris Gizopoulos and
George Papadimitriou and
Athanasios Chatzidimitriou and
Vijay Janapa Reddi and
Behzad Salami and
Osman S. Unsal and
Adri{\'{a}}n Cristal Kestelman and
Jingwen Leng},
editor = {Dimitris Gizopoulos and
Dan Alexandrescu and
Panagiota Papavramidou and
Michail Maniatakos},
title = {Modern Hardware Margins: CPUs, GPUs, FPGAs Recent System-Level Studies},
booktitle = {25th {IEEE} International Symposium on On-Line Testing and Robust
System Design, {IOLTS} 2019, Rhodes, Greece, July 1-3, 2019},
pages = {129--134},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/IOLTS.2019.8854386},
doi = {10.1109/IOLTS.2019.8854386},
timestamp = {Thu, 21 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/GizopoulosPCR0U19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KolonkoVK19,
author = {Lech Kolonko and
J{\"{o}}rg Velten and
Anton Kummert},
title = {Live Demonstration: {A} Raspberry Pi Based Video Pipeline for 2-D
Wave Digital Filters on Low-Cost {FPGA} Hardware},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702197},
doi = {10.1109/ISCAS.2019.8702197},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KolonkoVK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KolonkoVK19a,
author = {Lech Kolonko and
J{\"{o}}rg Velten and
Anton Kummert},
title = {A Raspberry Pi Based Video Pipeline for 2-D Wave Digital Filters on
Low-Cost {FPGA} Hardware},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702369},
doi = {10.1109/ISCAS.2019.8702369},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KolonkoVK19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/PereiraSZM19,
author = {Lucas M. V. Pereira and
Douglas A. dos Santos and
Cesar A. Zeferino and
Douglas R. Melo},
title = {A Low-Cost Hardware Accelerator for {CCSDS} 123 Predictor in {FPGA}},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702428},
doi = {10.1109/ISCAS.2019.8702428},
timestamp = {Fri, 13 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/PereiraSZM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/0003PCM19,
author = {Samik Basu and
Soumya Pandit and
Amlan Chakrabarti and
Soma Barman Mandal},
title = {{FPGA} Based Hardware Design for Noise Suppression and Seismic Event
Detection},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2019
(Formerly iNiS), Rourkela, India, December 16-18, 2019},
pages = {382--385},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/iSES47678.2019.00094},
doi = {10.1109/ISES47678.2019.00094},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ises/0003PCM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc-asia/YangYLHLH19,
author = {Yipei Yang and
Jing Ye and
Xiaowei Li and
Yinhe Han and
Huawei Li and
Yu Hu},
title = {Implementation of Parametric Hardware Trojan in {FPGA}},
booktitle = {{IEEE} International Test Conference in Asia, ITC-Asia 2019, Tokyo,
Japan, September 3-5, 2019},
pages = {37--42},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ITC-Asia.2019.00020},
doi = {10.1109/ITC-ASIA.2019.00020},
timestamp = {Tue, 23 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/itc-asia/YangYLHLH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/BhattiG19,
author = {Faraz Bhatti and
Thomas Greiner},
editor = {Hoi Lee and
Randall L. Geiger},
title = {{HLS} Based Optimizations of an {FPGA} Hardware Design for Plenoptic
Image Processing Algorithm},
booktitle = {62nd {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2019, Dallas, TX, USA, August 4-7, 2019},
pages = {690--693},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/MWSCAS.2019.8885282},
doi = {10.1109/MWSCAS.2019.8885282},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/BhattiG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/newcas/RoshdyTSMR19,
author = {Merna Roshdy and
Mohammed F. Tolba and
Lobna A. Said and
Ahmed H. Madian and
Ahmed G. Radwan},
title = {Generic Hardware of Fractional Order Multi-Scrolls Chaotic Generator
Based on {FPGA}},
booktitle = {17th {IEEE} International New Circuits and Systems Conference, {NEWCAS}
2019, Munich, Germany, June 23-26, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/NEWCAS44328.2019.8961267},
doi = {10.1109/NEWCAS44328.2019.8961267},
timestamp = {Wed, 05 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/newcas/RoshdyTSMR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/norchip/CabaRBTDL19,
author = {Juli{\'{a}}n Caba and
Fernando Rinc{\'{o}}n and
Jes{\'{u}}s Barba and
Jos{\'{e}} Antonio de la Torre and
Julio Dondo and
Juan Carlos L{\'{o}}pez},
editor = {Jari Nurmi and
Peeter Ellervee and
Kari Halonen and
Juha R{\"{o}}ning},
title = {HALib: Hardware Assertion Library for on-board verification of FPGA-based
modules using {HLS}},
booktitle = {2019 {IEEE} Nordic Circuits and Systems Conference, {NORCAS} 2019:
{NORCHIP} and International Symposium of System-on-Chip (SoC), Helsinki,
Finland, October 29-30, 2019},
pages = {1--7},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/NORCHIP.2019.8906966},
doi = {10.1109/NORCHIP.2019.8906966},
timestamp = {Sat, 27 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/norchip/CabaRBTDL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/FerreiraGS19,
author = {Willian de Assis Pedrobon Ferreira and
Ian Andrew Grout and
Alexandre C{\'{e}}sar Rodrigues da Silva},
editor = {Jo{\~{a}}o Antonio Martino and
Marcelo Lubaszewski and
Matteo Sonza Reorda},
title = {{FPGA} hardware linear regression implementation using fixed-point
arithmetic},
booktitle = {Proceedings of the 32nd Symposium on Integrated Circuits and Systems
Design, {SBCCI} 2019, Sao Paulo, Brazil, August 26-30, 2019},
pages = {10},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3338852.3339853},
doi = {10.1145/3338852.3339853},
timestamp = {Wed, 11 Aug 2021 17:02:35 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/FerreiraGS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smartcloud/Nan0LCSH19,
author = {Tianhao Nan and
Yongxin Zhu and
Wanyi Li and
Xintong Chen and
Yuefeng Song and
Junjie Hou},
title = {An FPGA-based Hardware Acceleration For Key Steps of Facet Imaging
Algorithm},
booktitle = {{IEEE} International Conference on Smart Cloud, SmartCloud 2019, Tokyo,
Japan, December 10-12, 2019},
pages = {86--91},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SmartCloud.2019.00025},
doi = {10.1109/SMARTCLOUD.2019.00025},
timestamp = {Wed, 20 May 2020 15:43:38 +0200},
biburl = {https://dblp.org/rec/conf/smartcloud/Nan0LCSH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smartnets/Al-SharaaIB19,
author = {Sara Al{-}Shara'a and
Raid Khalid Ibraheem and
Oguz Bayat},
title = {Implementation of cryptanalysis based on {FPGA} hardware using {AES}
with {SHA-1}},
booktitle = {International Conference on Smart Applications, Communications and
Networking, SmartNets 2019, Sharm El Sheik, Egypt, December 17-19,
2019},
pages = {1--7},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SmartNets48225.2019.9069786},
doi = {10.1109/SMARTNETS48225.2019.9069786},
timestamp = {Thu, 07 May 2020 14:50:04 +0200},
biburl = {https://dblp.org/rec/conf/smartnets/Al-SharaaIB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/space/GovindanKDPC19,
author = {Vidya Govindan and
Sandhya Koteshwara and
Amitabh Das and
Keshab K. Parhi and
Rajat Subhra Chakraborty},
editor = {Shivam Bhasin and
Avi Mendelson and
Mridul Nandi},
title = {ProTro: {A} Probabilistic Counter Based Hardware Trojan Attack on
{FPGA} Based MACSec Enabled Ethernet Switch},
booktitle = {Security, Privacy, and Applied Cryptography Engineering - 9th International
Conference, {SPACE} 2019, Gandhinagar, India, December 3-7, 2019,
Proceedings},
series = {Lecture Notes in Computer Science},
volume = {11947},
pages = {159--175},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-35869-3\_12},
doi = {10.1007/978-3-030-35869-3\_12},
timestamp = {Fri, 22 Nov 2019 13:35:40 +0100},
biburl = {https://dblp.org/rec/conf/space/GovindanKDPC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/tamc/HoraKT19,
author = {Martin Hora and
V{\'{a}}clav Koncick{\'{y}} and
Jakub Tetek},
editor = {T. V. Gopal and
Junzo Watada},
title = {Theoretical Model of Computation and Algorithms for FPGA-Based Hardware
Accelerators},
booktitle = {Theory and Applications of Models of Computation - 15th Annual Conference,
{TAMC} 2019, Kitakyushu, Japan, April 13-16, 2019, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {11436},
pages = {295--312},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-14812-6\_18},
doi = {10.1007/978-3-030-14812-6\_18},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/tamc/HoraKT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1907-03981,
author = {Xunhua Dai and
Chenxu Ke and
Quan Quan and
Kai{-}Yuan Cai},
title = {Simulation Credibility Assessment Methodology with FPGA-based Hardware-in-the-loop
Platform},
journal = {CoRR},
volume = {abs/1907.03981},
year = {2019},
url = {http://arxiv.org/abs/1907.03981},
eprinttype = {arXiv},
eprint = {1907.03981},
timestamp = {Wed, 17 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1907-03981.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1910-05086,
author = {Sergei Skorobogatov},
title = {Hardware Security Evaluation of {MAX} 10 {FPGA}},
journal = {CoRR},
volume = {abs/1910.05086},
year = {2019},
url = {http://arxiv.org/abs/1910.05086},
eprinttype = {arXiv},
eprint = {1910.05086},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1910-05086.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1911-04378,
author = {Jacob T. Grycel and
Robert J. Walls},
title = {{DRAB-LOCUS:} An Area-Efficient {AES} Architecture for Hardware Accelerator
Co-Location on FPGAs},
journal = {CoRR},
volume = {abs/1911.04378},
year = {2019},
url = {http://arxiv.org/abs/1911.04378},
eprinttype = {arXiv},
eprint = {1911.04378},
timestamp = {Sun, 01 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-1911-04378.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1911-05944,
author = {Tolulope A. Odetola and
Katie M. Groves and
Syed Rafay Hasan},
title = {2L-3W: 2-Level 3-Way Hardware-Software Co-Verification for the Mapping
of Deep Learning Architecture {(DLA)} onto {FPGA} Boards},
journal = {CoRR},
volume = {abs/1911.05944},
year = {2019},
url = {http://arxiv.org/abs/1911.05944},
eprinttype = {arXiv},
eprint = {1911.05944},
timestamp = {Mon, 02 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-1911-05944.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iacr/VliegenRCM19,
author = {Jo Vliegen and
Md Masoom Rabbani and
Mauro Conti and
Nele Mentens},
title = {A Novel {FPGA} Architecture and Protocol for the Self-attestation
of Configurable Hardware},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {405},
year = {2019},
url = {https://eprint.iacr.org/2019/405},
timestamp = {Mon, 11 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iacr/VliegenRCM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1910-05683,
title = {Hardware/Software Codesign for Training/Testing Multiple Neural Networks
on Multiple FPGAs},
journal = {CoRR},
volume = {abs/1910.05683},
year = {2019},
note = {Withdrawn.},
url = {http://arxiv.org/abs/1910.05683},
eprinttype = {arXiv},
eprint = {1910.05683},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1910-05683.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/basesearch/Ma18a,
author = {Yufei Ma},
title = {Hardware Acceleration of Deep Convolutional Neural Networks on {FPGA}},
school = {Arizona State University, Tempe, {USA}},
year = {2018},
url = {https://hdl.handle.net/2286/R.I.51620},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/basesearch/Ma18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/hal/Du18,
author = {Ke Du},
title = {Building and analyzing processing graphs on FPGAs with strong time
and hardware constraints. (Cr{\'{e}}ation et analyse de graphes
de traitements sur FPGA, sous contraintes mat{\'{e}}rielles et
contexte temps r{\'{e}}el dur)},
school = {University of Burgundy - Franche-Comt{\'{e}}, France},
year = {2018},
url = {https://tel.archives-ouvertes.fr/tel-01865542},
timestamp = {Fri, 29 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/hal/Du18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/HussainTBSAA18,
author = {Ahmed A. Hussain and
Nizar Tayem and
Muhammad Omair Butt and
Abdel{-}Hamid Soliman and
Abdulrahman A. Alhamed and
Saleh AlShebeili},
title = {{FPGA} Hardware Implementation of {DOA} Estimation Algorithm Employing
{LU} Decomposition},
journal = {{IEEE} Access},
volume = {6},
pages = {17666--17680},
year = {2018},
url = {https://doi.org/10.1109/ACCESS.2018.2820122},
doi = {10.1109/ACCESS.2018.2820122},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/HussainTBSAA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/LiWPHL18,
author = {Shih{-}An Li and
Wei{-}Yen Wang and
Wei{-}Zheng Pan and
Chen{-}Chien James Hsu and
Cheng{-}Kai Lu},
title = {FPGA-Based Hardware Design for Scale-Invariant Feature Transform},
journal = {{IEEE} Access},
volume = {6},
pages = {43850--43864},
year = {2018},
url = {https://doi.org/10.1109/ACCESS.2018.2863019},
doi = {10.1109/ACCESS.2018.2863019},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/LiWPHL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/NguyenHNIP18,
author = {Xuan{-}Thuan Nguyen and
Trong{-}Thuc Hoang and
Hong{-}Thu Nguyen and
Katsumi Inoue and
Cong{-}Kha Pham},
title = {An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index
Creation},
journal = {{IEEE} Access},
volume = {6},
pages = {16046--16059},
year = {2018},
url = {https://doi.org/10.1109/ACCESS.2018.2816039},
doi = {10.1109/ACCESS.2018.2816039},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/NguyenHNIP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computers/SharmaKK18,
author = {Dimple Sharma and
Lev Kirischian and
Valeri Kirischian},
title = {Run-Time Mitigation of Power Budget Variations and Hardware Faults
by Structural Adaptation of FPGA-Based Multi-Modal SoPC},
journal = {Comput.},
volume = {7},
number = {4},
pages = {52},
year = {2018},
url = {https://doi.org/10.3390/computers7040052},
doi = {10.3390/COMPUTERS7040052},
timestamp = {Sun, 21 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computers/SharmaKK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/csr/BakiriGCO18,
author = {Mohammed Bakiri and
Christophe Guyeux and
Jean{-}Fran{\c{c}}ois Couchot and
Abdelkrim Kamel Oudjida},
title = {Survey on hardware implementation of random number generators on {FPGA:}
Theory and experimental analyses},
journal = {Comput. Sci. Rev.},
volume = {27},
pages = {135--153},
year = {2018},
url = {https://doi.org/10.1016/j.cosrev.2018.01.002},
doi = {10.1016/J.COSREV.2018.01.002},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/csr/BakiriGCO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ejwcn/YiN18,
author = {Haibo Yi and
Zhe Nie},
title = {High-speed hardware architecture for implementations of multivariate
signature generations on FPGAs},
journal = {{EURASIP} J. Wirel. Commun. Netw.},
volume = {2018},
pages = {93},
year = {2018},
url = {https://doi.org/10.1186/s13638-018-1117-2},
doi = {10.1186/S13638-018-1117-2},
timestamp = {Thu, 27 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ejwcn/YiN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/SakakibaraMNM18,
author = {Yuma Sakakibara and
Shin Morishima and
Kohei Nakamura and
Hiroki Matsutani},
title = {A Hardware-Based Caching System on {FPGA} {NIC} for Blockchain},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {101-D},
number = {5},
pages = {1350--1360},
year = {2018},
url = {https://doi.org/10.1587/transinf.2017EDP7290},
doi = {10.1587/TRANSINF.2017EDP7290},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/SakakibaraMNM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/JiangLLLL18,
author = {Hongxu Jiang and
Shenglan Li and
Huiyong Li and
Tingshan Liu and
Jinyuan Lu},
title = {A High-Performance and Hardware-Efficient PCIe Transmission for a
Multi-Channel Video Using Command Caching and Dynamic Splicing on
{FPGA}},
journal = {J. Circuits Syst. Comput.},
volume = {27},
number = {4},
pages = {1850067:1--1850067:19},
year = {2018},
url = {https://doi.org/10.1142/S0218126618500676},
doi = {10.1142/S0218126618500676},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/JiangLLLL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jhss/GovindanCSC18,
author = {Vidya Govindan and
Rajat Subhra Chakraborty and
Pranesh Santikellur and
Aditya Kumar Chaudhary},
title = {A Hardware Trojan Attack on FPGA-Based Cryptographic Key Generation:
Impact and Detection},
journal = {J. Hardw. Syst. Secur.},
volume = {2},
number = {3},
pages = {225--239},
year = {2018},
url = {https://doi.org/10.1007/s41635-018-0042-5},
doi = {10.1007/S41635-018-0042-5},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jhss/GovindanCSC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jmmis/SongK18,
author = {Seok Bin Song and
Jin Heon Kim},
title = {Brief Paper: FPGA-based Hardware Prediction Rendering for Low-Latency
Touch Platform},
journal = {J. Multim. Inf. Syst.},
volume = {5},
number = {1},
pages = {59--62},
year = {2018},
url = {https://doi.org/10.9717/JMIS.2018.5.1.59},
doi = {10.9717/JMIS.2018.5.1.59},
timestamp = {Wed, 08 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jmmis/SongK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/ChoiKS18,
author = {Seungdo Choi and
Youngil Kim and
Yong Ho Song},
title = {False history filtering for reducing hardware overhead of FPGA-based
{LZ77} compressor},
journal = {J. Syst. Archit.},
volume = {88},
pages = {110--119},
year = {2018},
url = {https://doi.org/10.1016/j.sysarc.2018.06.001},
doi = {10.1016/J.SYSARC.2018.06.001},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/ChoiKS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/spic/HajiRassoulihaT18,
author = {Amir HajiRassouliha and
Andrew J. Taberner and
Martyn P. Nash and
Poul M. F. Nielsen},
title = {Suitability of recent hardware accelerators (DSPs, FPGAs, and GPUs)
for computer vision and image processing algorithms},
journal = {Signal Process. Image Commun.},
volume = {68},
pages = {101--119},
year = {2018},
url = {https://doi.org/10.1016/j.image.2018.07.007},
doi = {10.1016/J.IMAGE.2018.07.007},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/spic/HajiRassoulihaT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AghaieKA18,
author = {Anita Aghaie and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {Reliable and Fault Diagnosis Architectures for Hardware and Software-Efficient
Block Cipher {KLEIN} Benchmarked on {FPGA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {901--905},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2740286},
doi = {10.1109/TCAD.2017.2740286},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AghaieKA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiangSZ18,
author = {Hao Liang and
Sharad Sinha and
Wei Zhang},
title = {Parallelizing Hardware Tasks on Multicontext {FPGA} With Efficient
Placement and Scheduling Algorithms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {350--363},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2697952},
doi = {10.1109/TCAD.2017.2697952},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiangSZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/CheangMM18,
author = {Chak{-}Fong Cheang and
Pui{-}In Mak and
Rui Paulo Martins},
title = {A Hardware-Efficient Feedback Polynomial Topology for {DPD} Linearization
of Power Amplifiers: Theory and {FPGA} Validation},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {65-I},
number = {9},
pages = {2889--2902},
year = {2018},
url = {https://doi.org/10.1109/TCSI.2017.2788082},
doi = {10.1109/TCSI.2017.2788082},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/CheangMM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcsv/SeyidRCL18,
author = {Kerem Seyid and
Andrea Richaud and
Raffaele Capoccia and
Yusuf Leblebici},
title = {FPGA-Based Hardware Implementation of Real-Time Optical Flow Calculation},
journal = {{IEEE} Trans. Circuits Syst. Video Technol.},
volume = {28},
number = {1},
pages = {206--216},
year = {2018},
url = {https://doi.org/10.1109/TCSVT.2016.2598703},
doi = {10.1109/TCSVT.2016.2598703},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcsv/SeyidRCL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tdsc/Lumbiarres-Lopez18,
author = {Ruben Lumbiarres{-}Lopez and
Mariano L{\'{o}}pez{-}Garc{\'{\i}}a and
Enrique F. Cant{\'{o}}{-}Navarro},
title = {Hardware Architecture Implemented on {FPGA} for Protecting Cryptographic
Keys against Side-Channel Attacks},
journal = {{IEEE} Trans. Dependable Secur. Comput.},
volume = {15},
number = {5},
pages = {898--905},
year = {2018},
url = {https://doi.org/10.1109/TDSC.2016.2610966},
doi = {10.1109/TDSC.2016.2610966},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tdsc/Lumbiarres-Lopez18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tie/XuLXLJ18,
author = {Yunwen Xu and
Dewei Li and
Yugeng Xi and
Jian Lan and
Tengfei Jiang},
title = {An Improved Predictive Controller on the {FPGA} by Hardware Matrix
Inversion},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {65},
number = {9},
pages = {7395--7405},
year = {2018},
url = {https://doi.org/10.1109/TIE.2018.2798563},
doi = {10.1109/TIE.2018.2798563},
timestamp = {Mon, 12 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tie/XuLXLJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tjs/YazdinejadBJ18,
author = {Abbas Yazdinejad and
Ali Bohlooli and
Kamal Jamshidi},
title = {Efficient design and hardware implementation of the OpenFlow v1.3
Switch on the Virtex-6 {FPGA} {ML605}},
journal = {J. Supercomput.},
volume = {74},
number = {3},
pages = {1299--1320},
year = {2018},
url = {https://doi.org/10.1007/s11227-017-2175-7},
doi = {10.1007/S11227-017-2175-7},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tjs/YazdinejadBJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/IngemarssonG18,
author = {Carl Ingemarsson and
Oscar Gustafsson},
title = {{SFF} - The Single-Stream FPGA-Optimized Feedforward {FFT} Hardware
Architecture},
journal = {J. Signal Process. Syst.},
volume = {90},
number = {11},
pages = {1583--1592},
year = {2018},
url = {https://doi.org/10.1007/s11265-018-1370-y},
doi = {10.1007/S11265-018-1370-Y},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsisp/IngemarssonG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ahs/DorflingerASFMK18,
author = {Alexander D{\"{o}}rflinger and
Mark Albers and
Johannes Schlatow and
Bj{\"{o}}rn Fiethe and
Harald Michalik and
Phillip Keldenich and
S{\'{a}}ndor P. Fekete},
title = {Hardware and Software Task Scheduling for {ARM-FPGA} Platforms},
booktitle = {2018 {NASA/ESA} Conference on Adaptive Hardware and Systems, {AHS}
2018, Edinburgh, United Kingdom, August 6-9, 2018},
pages = {66--73},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/AHS.2018.8541481},
doi = {10.1109/AHS.2018.8541481},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/ahs/DorflingerASFMK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ahs/Fahmy18,
author = {Suhaib A. Fahmy},
title = {Design Abstraction for Autonomous Adaptive Hardware Systems on FPGAs},
booktitle = {2018 {NASA/ESA} Conference on Adaptive Hardware and Systems, {AHS}
2018, Edinburgh, United Kingdom, August 6-9, 2018},
pages = {142--147},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/AHS.2018.8541489},
doi = {10.1109/AHS.2018.8541489},
timestamp = {Wed, 28 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ahs/Fahmy18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/KachrisSKS18,
author = {Christoforos Kachris and
Ioannis Stamelos and
Elias Koromilas and
Dimitrios Soudris},
editor = {Nikolaos S. Voros and
Michael H{\"{u}}bner and
Georgios Keramidas and
Diana Goehringer and
Christos P. Antonopoulos and
Pedro C. Diniz},
title = {Seamless {FPGA} Deployment over Spark in Cloud Computing: {A} Use
Case on Machine Learning Hardware Acceleration},
booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications
- 14th International Symposium, {ARC} 2018, Santorini, Greece, May
2-4, 2018, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10824},
pages = {673--684},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-319-78890-6\_54},
doi = {10.1007/978-3-319-78890-6\_54},
timestamp = {Wed, 28 Apr 2021 16:06:57 +0200},
biburl = {https://dblp.org/rec/conf/arc/KachrisSKS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asplos/MoreauCC18,
author = {Thierry Moreau and
Tianqi Chen and
Luis Ceze},
editor = {Luis Ceze and
Natalie D. Enright Jerger and
Babak Falsafi and
Grigori Fursin and
Anton Lokhmotov and
Thierry Moreau and
Adrian Sampson and
Phillip Stanley{-}Marbell},
title = {Leveraging the {VTA-TVM} Hardware-Software Stack for {FPGA} Acceleration
of 8-bit ResNet-18 Inference},
booktitle = {Proceedings of the 1st on Reproducible Quality-Efficient Systems Tournament
on Co-designing Pareto-efficient Deep Learning, ReQuEST@ASPLOS 2018,
Williamsburg, VA, USA, March 24, 2018},
pages = {5},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3229762.3229766},
doi = {10.1145/3229762.3229766},
timestamp = {Sat, 17 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asplos/MoreauCC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/YeH018,
author = {Jing Ye and
Yu Hu and
Xiaowei Li},
title = {Hardware Trojan in {FPGA} {CNN} Accelerator},
booktitle = {27th {IEEE} Asian Test Symposium, {ATS} 2018, Hefei, China, October
15-18, 2018},
pages = {68--73},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ATS.2018.00024},
doi = {10.1109/ATS.2018.00024},
timestamp = {Mon, 22 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ats/YeH018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ccs/MartinasekHSMMK18,
author = {Zdenek Martinasek and
Jan Hajny and
David Smekal and
Lukas Malina and
Denis Matousek and
Michal Kekely and
Nele Mentens},
editor = {Chip{-}Hong Chang and
Ulrich R{\"{u}}hrmair and
Daniel E. Holcomb and
Jorge Guajardo},
title = {200 Gbps Hardware Accelerated Encryption System for {FPGA} Network
Cards},
booktitle = {Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware
Security, ASHES@CCS 2018, Toronto, ON, Canada, October 19, 2018},
pages = {11--17},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3266444.3266446},
doi = {10.1145/3266444.3266446},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ccs/MartinasekHSMMK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ccs/YoonSJCKKK18,
author = {Junghwan Yoon and
Yezee Seo and
Jaedong Jang and
Mingi Cho and
JinGoog Kim and
HyeonSook Kim and
Taekyoung Kwon},
editor = {David Lie and
Mohammad Mannan and
Michael Backes and
XiaoFeng Wang},
title = {A Bitstream Reverse Engineering Tool for {FPGA} Hardware Trojan Detection},
booktitle = {Proceedings of the 2018 {ACM} {SIGSAC} Conference on Computer and
Communications Security, {CCS} 2018, Toronto, ON, Canada, October
15-19, 2018},
pages = {2318--2320},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3243734.3278487},
doi = {10.1145/3243734.3278487},
timestamp = {Thu, 12 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ccs/YoonSJCKKK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cist/Bousmar18,
author = {Khadija Bousmar},
editor = {Mohammed El Mohajir and
Mohammed Al Achhab and
Badr Eddine El Mohajir and
Ismail Jellouli},
title = {A Pure Hardware k-SAT Solver for {FPGA}},
booktitle = {5th {IEEE} International Congress on Information Science and Technology,
CiSt 2018, Marrakech, Morocco, October 21-27, 2018},
pages = {481--485},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/CIST.2018.8596454},
doi = {10.1109/CIST.2018.8596454},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cist/Bousmar18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csae/ZhongLWZL18,
author = {Baoyan Zhong and
Xiaofeng Lu and
Qiaoyuan Wang and
Siqi Zhao and
Qianyun Liu},
editor = {Ali Emrouznejad and
Zhihong Qian},
title = {A Hardware Architecture of Target Tracking System on {FPGA}},
booktitle = {The 2nd International Conference on Computer Science and Application
Engineering, {CSAE} 2018, Hohhot, China, October 22-24, 2018},
pages = {65:1--65:5},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3207677.3278009},
doi = {10.1145/3207677.3278009},
timestamp = {Thu, 10 Jun 2021 16:50:33 +0200},
biburl = {https://dblp.org/rec/conf/csae/ZhongLWZL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiuKWC18,
author = {Xinheng Liu and
Dae Hee Kim and
Chang Wu and
Deming Chen},
editor = {Shiyan Hu},
title = {Resource and data optimization for hardware implementation of deep
neural networks targeting FPGA-based edge devices},
booktitle = {Proceedings of the 20th System Level Interconnect Prediction Workshop,
SLIP@DAC 2018, San Francisco, CA, USA, June 23, 2018},
pages = {1:1--1:8},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3225209.3225214},
doi = {10.1145/3225209.3225214},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LiuKWC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/UllahRPKH0018,
author = {Salim Ullah and
Semeen Rehman and
Bharath Srinivas Prabakaran and
Florian Kriebel and
Muhammad Abdullah Hanif and
Muhammad Shafique and
Akash Kumar},
title = {Area-optimized low-latency approximate multipliers for FPGA-based
hardware accelerators},
booktitle = {Proceedings of the 55th Annual Design Automation Conference, {DAC}
2018, San Francisco, CA, USA, June 24-29, 2018},
pages = {159:1--159:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3195970.3195996},
doi = {10.1145/3195970.3195996},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/UllahRPKH0018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/data2/DhibTM18,
author = {Farah Dhib and
Elmehdi Tatar and
Mohsen Machhout},
editor = {Juan Alfonso Lara Torralbo and
Shadi A. Aljawarneh},
title = {Hardware implementation of a fingerprint recognition algorithm on
{FPGA} cyclone {II}},
booktitle = {Proceedings of the First International Conference on Data Science,
E-learning and Information Systems, {DATA} 2018, Madrid, Spain, October
01-02, 2018},
pages = {5:1--5:7},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3279996.3280001},
doi = {10.1145/3279996.3280001},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/data2/DhibTM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/FournarisPK18,
author = {Apostolos P. Fournaris and
Lampros Pyrgas and
Paris Kitsos},
editor = {Martin Novotn{\'{y}} and
Nikos Konofaos and
Amund Skavhaug},
title = {An {FPGA} Hardware Trojan Detection Approach Based on Multiple Parameter
Analysis},
booktitle = {21st Euromicro Conference on Digital System Design, {DSD} 2018, Prague,
Czech Republic, August 29-31, 2018},
pages = {516--522},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/DSD.2018.00091},
doi = {10.1109/DSD.2018.00091},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/FournarisPK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/GuhaMSC18,
author = {Krishnendu Guha and
Atanu Majumder and
Debasri Saha and
Amlan Chakrabarti},
editor = {Martin Novotn{\'{y}} and
Nikos Konofaos and
Amund Skavhaug},
title = {Reliability Driven Mixed Critical Tasks Processing on FPGAs Against
Hardware Trojan Attacks},
booktitle = {21st Euromicro Conference on Digital System Design, {DSD} 2018, Prague,
Czech Republic, August 29-31, 2018},
pages = {537--544},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/DSD.2018.00094},
doi = {10.1109/DSD.2018.00094},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/GuhaMSC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/WijesunderaPPHS18,
author = {Deshya Wijesundera and
Alok Prakash and
Thilina Perera and
Kalindu Herath and
Thambipillai Srikanthan},
title = {Wibheda: Framework for Data Dependency-Aware Multi-Constrained Hardware-Software
Partitioning in FPGA-Based SoCs for IoT Devices},
booktitle = {26th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2018, Boulder, CO, USA, April 29 - May
1, 2018},
pages = {213},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/FCCM.2018.00047},
doi = {10.1109/FCCM.2018.00047},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/WijesunderaPPHS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DingZMG18,
author = {Nan Ding and
Wei Zhang and
Yanhua Ma and
Zhenguo Gao},
editor = {Jason Helge Anderson and
Kia Bazargan},
title = {Software/Hardware Co-design for Multichannel Scheduling in {IEEE}
802.11p {MLME:} (Abstract Only)},
booktitle = {Proceedings of the 2018 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2018, Monterey, CA, USA, February 25-27, 2018},
pages = {289},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3174243.3174971},
doi = {10.1145/3174243.3174971},
timestamp = {Tue, 23 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/DingZMG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GuerrieriKALBI18,
author = {Andrea Guerrieri and
Sahand Kashani{-}Akhavan and
Mikhail Asiatici and
Pasquale Lombardi and
Bilel Belhadj and
Paolo Ienne},
editor = {Jason Helge Anderson and
Kia Bazargan},
title = {LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing
Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only)},
booktitle = {Proceedings of the 2018 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2018, Monterey, CA, USA, February 25-27, 2018},
pages = {295},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3174243.3175002},
doi = {10.1145/3174243.3175002},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/GuerrieriKALBI18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/HategekimanaMPB18,
author = {Festus Hategekimana and
Joel Mandebi Mbongue and
Md Jubaer Hossain Pantho and
Christophe Bobda},
title = {Secure Hardware Kernels Execution in {CPU+FPGA} Heterogeneous Cloud},
booktitle = {International Conference on Field-Programmable Technology, {FPT} 2018,
Naha, Okinawa, Japan, December 10-14, 2018},
pages = {182--189},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/FPT.2018.00035},
doi = {10.1109/FPT.2018.00035},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/HategekimanaMPB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/DingRYMLLYW18,
author = {Caiwen Ding and
Ao Ren and
Geng Yuan and
Xiaolong Ma and
Jiayu Li and
Ning Liu and
Bo Yuan and
Yanzhi Wang},
editor = {Deming Chen and
Houman Homayoun and
Baris Taskin},
title = {Structured Weight Matrices-Based Hardware Accelerators in Deep Neural
Networks: FPGAs and ASICs},
booktitle = {Proceedings of the 2018 on Great Lakes Symposium on VLSI, {GLSVLSI}
2018, Chicago, IL, USA, May 23-25, 2018},
pages = {353--358},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3194554.3194625},
doi = {10.1145/3194554.3194625},
timestamp = {Wed, 10 Mar 2021 14:55:38 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/DingRYMLLYW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/MohsinP18,
author = {Mokhles A. Mohsin and
Darshika G. Perera},
title = {An FPGA-Based Hardware Accelerator for K-Nearest Neighbor Classification
for Machine Learning on Mobile Devices},
booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
ON, Canada, June 20-22, 2018},
pages = {16:1--16:7},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3241793.3241810},
doi = {10.1145/3241793.3241810},
timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
biburl = {https://dblp.org/rec/conf/heart/MohsinP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/SchmitzZ18,
author = {Jesse Schmitz and
Lei Zhang},
title = {{FPGA} Hardware Implementation and Optimization for Neural Network
based Chaotic System Design},
booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
ON, Canada, June 20-22, 2018},
pages = {18:1--18:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3241793.3241812},
doi = {10.1145/3241793.3241812},
timestamp = {Thu, 31 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/heart/SchmitzZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/WijesunderaPPHS18,
author = {Deshya Wijesundera and
Alok Prakash and
Thilina Perera and
Kalindu Herath and
Thambipillai Srikanthan},
title = {Wibheda+: Framework for Data Dependency-aware Multi-constrained Hardware-Software
Partitioning in FPGA-based SoCs for IoT Applications},
booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
ON, Canada, June 20-22, 2018},
pages = {3:1--3:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3241793.3241796},
doi = {10.1145/3241793.3241796},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/heart/WijesunderaPPHS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icacci/BhardwajCL18,
author = {Aastha Bhardwaj and
Surbhi Chhabra and
Kusum Lata},
title = {{FPGA} Implementation of Traffic Light Controller and its Analysis
in the Presence of Hardware Trojan},
booktitle = {2018 International Conference on Advances in Computing, Communications
and Informatics, {ICACCI} 2018, Bangalore, India, September 19-22,
2018},
pages = {375--380},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ICACCI.2018.8554439},
doi = {10.1109/ICACCI.2018.8554439},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icacci/BhardwajCL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MaZ0VS18,
author = {Yufei Ma and
Tu Zheng and
Yu Cao and
Sarma B. K. Vrudhula and
Jae{-}sun Seo},
editor = {Iris Bahar},
title = {Algorithm-hardware co-design of single shot detector for fast object
detection on FPGAs},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018},
pages = {57},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3240765.3240775},
doi = {10.1145/3240765.3240775},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/MaZ0VS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/YeF018,
author = {Mengmei Ye and
Xianglong Feng and
Sheng Wei},
editor = {Iris Bahar},
title = {{HISA:} hardware isolation-based secure architecture for {CPU-FPGA}
embedded systems},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018},
pages = {90},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3240765.3240814},
doi = {10.1145/3240765.3240814},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/YeF018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhangWZLXHC18,
author = {Xiaofan Zhang and
Junsong Wang and
Chao Zhu and
Yonghua Lin and
Jinjun Xiong and
Wen{-}Mei W. Hwu and
Deming Chen},
editor = {Iris Bahar},
title = {DNNBuilder: an automated tool for building high-performance {DNN}
hardware accelerators for FPGAs},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018},
pages = {56},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3240765.3240801},
doi = {10.1145/3240765.3240801},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ZhangWZLXHC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iciot2/AlhafidhDAA18,
author = {Basman M. Hasan Alhafidh and
Amar I. Daood and
Mohammed M. Alawad and
William H. Allen},
editor = {Dimitrios Georgakopoulos and
Liang{-}Jie Zhang},
title = {{FPGA} Hardware Implementation of Smart Home Autonomous System Based
on Deep Learning},
booktitle = {Internet of Things - {ICIOT} 2018 - Third International Conference,
Held as Part of the Services Conference Federation, {SCF} 2018, Seattle,
WA, USA, June 25-30, 2018, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10972},
pages = {121--133},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-319-94370-1\_9},
doi = {10.1007/978-3-319-94370-1\_9},
timestamp = {Fri, 15 Mar 2024 12:30:44 +0100},
biburl = {https://dblp.org/rec/conf/iciot2/AlhafidhDAA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iconip/AokiKS18,
author = {Shunsuke Aoki and
Seitaro Koyama and
Toshimichi Saito},
editor = {Long Cheng and
Andrew Chi{-}Sing Leung and
Seiichi Ozawa},
title = {{FPGA} Based Hardware Implementation of Simple Dynamic Binary Neural
Networks},
booktitle = {Neural Information Processing - 25th International Conference, {ICONIP}
2018, Siem Reap, Cambodia, December 13-16, 2018, Proceedings, Part
{VII}},
series = {Lecture Notes in Computer Science},
volume = {11307},
pages = {647--655},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-04239-4\_58},
doi = {10.1007/978-3-030-04239-4\_58},
timestamp = {Tue, 14 May 2019 10:00:42 +0200},
biburl = {https://dblp.org/rec/conf/iconip/AokiKS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icteri/KolesnykKP18,
author = {Inna Kolesnyk and
Vitaliy Kulanov and
Artem Perepelitsyn},
editor = {Grigoris Antoniou and
Grygoriy Zholtkevych},
title = {Markov Model of {FPGA} Resources as a Service Considering Hardware
Failures},
booktitle = {Proceedings of the PhD Symposium at 14th International Conference
on {ICT} in Education, Research, and Industrial Applications {ICTERI}
2018 co-located with 14th International Conference on {ICT} in Education,
Research, and Industrial Applications {(ICTERI} 2018), Kyiv, Ukraine,
May 16, 2018},
series = {{CEUR} Workshop Proceedings},
volume = {2122},
pages = {56--62},
publisher = {CEUR-WS.org},
year = {2018},
url = {https://ceur-ws.org/Vol-2122/paper\_143.pdf},
timestamp = {Fri, 10 Mar 2023 16:23:14 +0100},
biburl = {https://dblp.org/rec/conf/icteri/KolesnykKP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iecon/Gil-NarvionNSL18,
author = {Jos{\'{e}} Miguel Gil{-}Narvi{\'{o}}n and
Denis Navarro and
Hector Sarnago and
Oscar Luc{\'{\i}}a},
title = {FPGA-Based Hardware in the Loop Test-Bench for Robust Software Development
of Induction Heating Appliances},
booktitle = {{IECON} 2018 - 44th Annual Conference of the {IEEE} Industrial Electronics
Society, Washington, DC, USA, October 21-23, 2018},
pages = {3497--3501},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/IECON.2018.8591348},
doi = {10.1109/IECON.2018.8591348},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iecon/Gil-NarvionNSL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iecon/KeikhaFMF18,
author = {Mahsa Keikha and
Xiaoliang Fu and
Mehrdad Moallem and
Ken Fong},
title = {Development of {FPGA} based Hardware-in-the-loop Simulator for {RF}
Cavity Resonator},
booktitle = {{IECON} 2018 - 44th Annual Conference of the {IEEE} Industrial Electronics
Society, Washington, DC, USA, October 21-23, 2018},
pages = {2256--2261},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/IECON.2018.8591408},
doi = {10.1109/IECON.2018.8591408},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iecon/KeikhaFMF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iecon/ParmarS18,
author = {Yashrajsinh Parmar and
K. Sridharan},
title = {Hardware-Efficient Velocity Estimation of Dynamic Obstacles Based
on a Novel Radix-4 {CORDIC} and {FPGA} Implementation},
booktitle = {{IECON} 2018 - 44th Annual Conference of the {IEEE} Industrial Electronics
Society, Washington, DC, USA, October 21-23, 2018},
pages = {3770--3775},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/IECON.2018.8591409},
doi = {10.1109/IECON.2018.8591409},
timestamp = {Wed, 07 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iecon/ParmarS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iecon/SaengerH18,
author = {P. Saenger and
Micka{\"{e}}l Hilairet},
title = {Hardware-In-the-Loop simulation of a DC-machine with {INTEL} {FPGA}
boards},
booktitle = {{IECON} 2018 - 44th Annual Conference of the {IEEE} Industrial Electronics
Society, Washington, DC, USA, October 21-23, 2018},
pages = {2815--2820},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/IECON.2018.8591602},
doi = {10.1109/IECON.2018.8591602},
timestamp = {Mon, 14 Jan 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iecon/SaengerH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipccc/JadhavGDKN18,
author = {Shrikant S. Jadhav and
Clay Gloster and
Christopher C. Doss and
Youngsoo Kim and
Jannatun Naher},
title = {AutoRARE: An Automated Tool For Generating FPGA-Based Multi-Memory
Hardware Accelerators For Compute-Intensive Applications},
booktitle = {37th {IEEE} International Performance Computing and Communications
Conference, {IPCCC} 2018, Orlando, FL, USA, November 17-19, 2018},
pages = {1--8},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PCCC.2018.8710782},
doi = {10.1109/PCCC.2018.8710782},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ipccc/JadhavGDKN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/PodobasM18,
author = {Artur Podobas and
Satoshi Matsuoka},
title = {Hardware Implementation of POSITs and Their Application in FPGAs},
booktitle = {2018 {IEEE} International Parallel and Distributed Processing Symposium
Workshops, {IPDPS} Workshops 2018, Vancouver, BC, Canada, May 21-25,
2018},
pages = {138--145},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/IPDPSW.2018.00029},
doi = {10.1109/IPDPSW.2018.00029},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/PodobasM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/TucciCCHDS18,
author = {Lorenzo Di Tucci and
Davide Conficconi and
Alessandro Comodi and
Steven A. Hofmeyr and
David Donofrio and
Marco D. Santambrogio},
title = {A Parallel, Energy Efficient Hardware Architecture for the merAligner
on {FPGA} Using Chisel {HCL}},
booktitle = {2018 {IEEE} International Parallel and Distributed Processing Symposium
Workshops, {IPDPS} Workshops 2018, Vancouver, BC, Canada, May 21-25,
2018},
pages = {214--217},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/IPDPSW.2018.00041},
doi = {10.1109/IPDPSW.2018.00041},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/TucciCCHDS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KarimHMGLHTTMJ18,
author = {Shvan Karim and
Jim Harkin and
Liam McDaid and
Bryan Gardiner and
Junxiu Liu and
David M. Halliday and
Andy M. Tyrrell and
Jon Timmis and
Alan G. Millard and
Anju P. Johnson},
title = {FPGA-based Fault-injection and Data Acquisition of Self-repairing
Spiking Neural Network Hardware},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018,
27-30 May 2018, Florence, Italy},
pages = {1--5},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISCAS.2018.8351512},
doi = {10.1109/ISCAS.2018.8351512},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KarimHMGLHTTMJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WeidleVMZ18,
author = {Guilherme F. Weidle and
Felipe Viel and
Douglas Rossi de Melo and
Cesar A. Zeferino},
title = {A Hardware Accelerator for Anisotropic Diffusion Filtering in {FPGA}},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018,
27-30 May 2018, Florence, Italy},
pages = {1--5},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISCAS.2018.8351279},
doi = {10.1109/ISCAS.2018.8351279},
timestamp = {Fri, 13 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/WeidleVMZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isda/RamCSS18,
author = {R. Gautham Sundar Ram and
Nitin Chaturvedi and
Sumeet Saurav and
Sanjay Singh},
editor = {Ajith Abraham and
Aswani Kumar Cherukuri and
Patricia Melin and
Niketa Gandhi},
title = {An {FPGA} Based Hardware Accelerator for Classification of Handwritten
Digits},
booktitle = {Intelligent Systems Design and Applications - 18th International Conference
on Intelligent Systems Design and Applications, {ISDA} 2018, Vellore,
India, December 6-8, 2018, Volume 1},
series = {Advances in Intelligent Systems and Computing},
volume = {940},
pages = {945--954},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-16657-1\_88},
doi = {10.1007/978-3-030-16657-1\_88},
timestamp = {Wed, 20 Nov 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isda/RamCSS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/VaniCK18,
author = {G. Divya Vani and
M. C. Chinnaiah and
Srinivasa Rao Karumuri},
editor = {Bijoy Antony Jose and
Jimson Mathew},
title = {Hardware Scheme for Autonomous Docking Algorithm using {FPGA} based
Mobile Robot},
booktitle = {8th International Symposium on Embedded Computing and System Design,
{ISED} 2018, Cochin, India, December 13-15, 2018},
pages = {110--115},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISED.2018.8704082},
doi = {10.1109/ISED.2018.8704082},
timestamp = {Wed, 19 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ised/VaniCK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/NazemiEP18,
author = {Mahdi Nazemi and
Amir Erfan Eshratifar and
Massoud Pedram},
title = {A hardware-friendly algorithm for scalable training and deployment
of dimensionality reduction models on {FPGA}},
booktitle = {19th International Symposium on Quality Electronic Design, {ISQED}
2018, Santa Clara, CA, USA, March 13-14, 2018},
pages = {395--400},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISQED.2018.8357319},
doi = {10.1109/ISQED.2018.8357319},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/NazemiEP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/KamaliAGHS18,
author = {Hadi Mardani Kamali and
Kimia Zamiri Azar and
Kris Gaj and
Houman Homayoun and
Avesta Sasan},
title = {LUT-Lock: {A} Novel LUT-Based Logic Obfuscation for FPGA-Bitstream
and ASIC-Hardware Protection},
booktitle = {2018 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2018,
Hong Kong, China, July 8-11, 2018},
pages = {405--410},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ISVLSI.2018.00080},
doi = {10.1109/ISVLSI.2018.00080},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/KamaliAGHS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ivsw/MahmudOK18,
author = {Shakil Mahmud and
Brooks Olney and
Robert Karam},
title = {Architectural Diversity: Bio-Inspired Hardware Security for FPGAs},
booktitle = {3rd {IEEE} International Verification and Security Workshop, {IVSW}
2018, Costa Brava, Spain, July 2-4, 2018},
pages = {48--51},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/IVSW.2018.8494854},
doi = {10.1109/IVSW.2018.8494854},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/ivsw/MahmudOK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/RiessBS18,
author = {Marcel Rie{\ss} and
Cedrik Bock and
Frank Slomka},
title = {Generic Reusable Hardware/Software Co-Design Implementation of a Complete
{FH-FSK} Modem for Robust Multi-User Acoustic Underwater Communication
and System Validation on a {FPGA}},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen, {MBMV} 2018, T{\"{u}}bingen, Germany,
February 8-9, 2018},
publisher = {Universit{\"{a}}t T{\"{u}}bingen},
year = {2018},
url = {https://hdl.handle.net/10900/84284},
timestamp = {Wed, 04 May 2022 13:03:25 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/RiessBS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micsecs/DorofeevaND18,
author = {Eleonora Dorofeeva and
Danila Nikiforovskii and
Ivan Deyneka},
editor = {Dmitry Mouromtsev and
Sergei Bykovskii},
title = {Features of the hardware implementation of real time Hough transform
on {FPGA}},
booktitle = {Proceedings of the 10th Majorov International Conference on Software
Engineering and Computer Systems, {MICSECS} 2018, Saint Petersburg,
Russia, December 20-21, 2018},
series = {{CEUR} Workshop Proceedings},
volume = {2344},
publisher = {CEUR-WS.org},
year = {2018},
url = {https://ceur-ws.org/Vol-2344/paper13.pdf},
timestamp = {Fri, 10 Mar 2023 16:22:45 +0100},
biburl = {https://dblp.org/rec/conf/micsecs/DorofeevaND18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micsecs/NikiforovskiiDS18,
author = {Danila Nikiforovskii and
Ivan Deyneka and
Daniil Smirnov},
editor = {Dmitry Mouromtsev and
Sergei Bykovskii},
title = {Features of hardware implementation of Particle Swarm Optimization
{(PSO)} on {FPGA}},
booktitle = {Proceedings of the 10th Majorov International Conference on Software
Engineering and Computer Systems, {MICSECS} 2018, Saint Petersburg,
Russia, December 20-21, 2018},
series = {{CEUR} Workshop Proceedings},
volume = {2344},
publisher = {CEUR-WS.org},
year = {2018},
url = {https://ceur-ws.org/Vol-2344/paper3.pdf},
timestamp = {Fri, 10 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micsecs/NikiforovskiiDS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/NairMG18,
author = {Arathy B. Nair and
Arijit Mondal and
Shayan Srinivasa Garani},
title = {A Low-complexity Hardware {AWGN} Channel Emulator on {FPGA} using
Central Limit Theorem},
booktitle = {{IEEE} 61st International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2018, Windsor, ON, Canada, August 5-8, 2018},
pages = {428--431},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/MWSCAS.2018.8623918},
doi = {10.1109/MWSCAS.2018.8623918},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/NairMG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/WuHMMGZ18,
author = {Zhongpan Wu and
Karim Hammad and
Robinson Mittmann and
Sebastian Magierowski and
Ebrahim Ghafar{-}Zadeh and
Xiaoyong Zhong},
title = {FPGA-based {DNA} Basecalling Hardware Acceleration},
booktitle = {{IEEE} 61st International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2018, Windsor, ON, Canada, August 5-8, 2018},
pages = {1098--1101},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/MWSCAS.2018.8623988},
doi = {10.1109/MWSCAS.2018.8623988},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/WuHMMGZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/noms/NagyOTKV18,
author = {Bal{\'{a}}zs Nagy and
Peter Orosz and
Tamas Tothfalusi and
L{\'{a}}szl{\'{o}} Kov{\'{a}}cs and
P{\'{a}}l Varga},
title = {Detecting DDoS attacks within milliseconds by using FPGA-based hardware
acceleration},
booktitle = {2018 {IEEE/IFIP} Network Operations and Management Symposium, {NOMS}
2018, Taipei, Taiwan, April 23-27, 2018},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/NOMS.2018.8406299},
doi = {10.1109/NOMS.2018.8406299},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/noms/NagyOTKV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/racs/HungHYLL18,
author = {Shih{-}Hao Hung and
Yi{-}Mo Ho and
Chih Wei Yeh and
Cheng{-}Yueh Liu and
Chen{-}Pang Lee},
editor = {Chih{-}Cheng Hung and
Lamjed Ben Said},
title = {Hardware-accelerated cache simulation for multicore by {FPGA}},
booktitle = {Proceedings of the 2018 Conference on Research in Adaptive and Convergent
Systems, {RACS} 2018, Honolulu, HI, USA, October 09-12, 2018},
pages = {231--236},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3264746.3264766},
doi = {10.1145/3264746.3264766},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/racs/HungHYLL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/AkgunKEG18,
author = {G{\"{o}}khan Akg{\"{u}}n and
Habib ul Hasan Khan and
Mahmoud Ahmed Elshimy and
Diana G{\"{o}}hringer},
editor = {David Andrews and
Ren{\'{e}} Cumplido and
Claudia Feregrino and
Dirk Stroobandt},
title = {Dynamic tunable and reconfigurable hardware controller with EKF-based
state reconstruction through FPGA-in the loop},
booktitle = {2018 International Conference on ReConFigurable Computing and FPGAs,
ReConFig 2018, Cancun, Mexico, December 3-5, 2018},
pages = {1--8},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/RECONFIG.2018.8641704},
doi = {10.1109/RECONFIG.2018.8641704},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/AkgunKEG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/AveyJZ18,
author = {Joe Avey and
Phillip H. Jones and
Joseph Zambreno},
editor = {David Andrews and
Ren{\'{e}} Cumplido and
Claudia Feregrino and
Dirk Stroobandt},
title = {An FPGA-based Hardware Accelerator for Iris Segmentation},
booktitle = {2018 International Conference on ReConFigurable Computing and FPGAs,
ReConFig 2018, Cancun, Mexico, December 3-5, 2018},
pages = {1--8},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/RECONFIG.2018.8641726},
doi = {10.1109/RECONFIG.2018.8641726},
timestamp = {Sun, 17 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/reconfig/AveyJZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/CacciottiCSPE18,
author = {Mattia Cacciotti and
Vincent Camus and
Jeremy Schlachter and
Alessandro Pezzotta and
Christian C. Enz},
title = {Hardware Acceleration of HDR-Image Tone Mapping on an {FPGA-CPU} Platform
Through High-Level Synthesis},
booktitle = {31st {IEEE} International System-on-Chip Conference, {SOCC} 2018,
Arlington, VA, USA, September 4-7, 2018},
pages = {158--162},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/SOCC.2018.8618490},
doi = {10.1109/SOCC.2018.8618490},
timestamp = {Fri, 23 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/socc/CacciottiCSPE18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/tsp/SmekalHM18,
author = {David Smekal and
Jan Hajny and
Zdenek Martinasek},
title = {Hardware-Accelerated Twofish Core for {FPGA}},
booktitle = {41st International Conference on Telecommunications and Signal Processing,
{TSP} 2018, Athens, Greece, July 4-6, 2018},
pages = {1--5},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/TSP.2018.8441386},
doi = {10.1109/TSP.2018.8441386},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/tsp/SmekalHM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JuniorB18,
author = {Luiz Antonio de Oliveira Junior and
Edna Barros},
title = {An FPGA-based Hardware Accelerator for Scene Text Character Recognition},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {125--130},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644776},
doi = {10.1109/VLSI-SOC.2018.8644776},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JuniorB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/sp/18/SanoN18,
author = {Kentaro Sano and
Hiroki Nakahara},
editor = {Hideharu Amano},
title = {Hardware Algorithms},
booktitle = {Principles and Structures of FPGAs},
pages = {137--177},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-981-13-0824-6\_6},
doi = {10.1007/978-981-13-0824-6\_6},
timestamp = {Tue, 11 Sep 2018 08:33:58 +0200},
biburl = {https://dblp.org/rec/books/sp/18/SanoN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1801-04014,
author = {Mahdi Nazemi and
Amir Erfan Eshratifar and
Massoud Pedram},
title = {A Hardware-Friendly Algorithm for Scalable Training and Deployment
of Dimensionality Reduction Models on {FPGA}},
journal = {CoRR},
volume = {abs/1801.04014},
year = {2018},
url = {http://arxiv.org/abs/1801.04014},
eprinttype = {arXiv},
eprint = {1801.04014},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1801-04014.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1803-11207,
author = {Xuan{-}Thuan Nguyen and
Trong{-}Thuc Hoang and
Hong{-}Thu Nguyen and
Katsumi Inoue and
Cong{-}Kha Pham},
title = {An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index
Creation},
journal = {CoRR},
volume = {abs/1803.11207},
year = {2018},
url = {http://arxiv.org/abs/1803.11207},
eprinttype = {arXiv},
eprint = {1803.11207},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1803-11207.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1804-11239,
author = {Caiwen Ding and
Ao Ren and
Geng Yuan and
Xiaolong Ma and
Jiayu Li and
Ning Liu and
Bo Yuan and
Yanzhi Wang},
title = {Structured Weight Matrices-Based Hardware Accelerators in Deep Neural
Networks: FPGAs and ASICs},
journal = {CoRR},
volume = {abs/1804.11239},
year = {2018},
url = {http://arxiv.org/abs/1804.11239},
eprinttype = {arXiv},
eprint = {1804.11239},
timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1804-11239.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1804-11275,
author = {Hadi Mardani Kamali and
Kimia Zamiri Azar and
Kris Gaj and
Houman Homayoun and
Avesta Sasan},
title = {LUT-Lock: {A} Novel LUT-based Logic Obfuscation for FPGA-Bitstream
and ASIC-Hardware Protection},
journal = {CoRR},
volume = {abs/1804.11275},
year = {2018},
url = {http://arxiv.org/abs/1804.11275},
eprinttype = {arXiv},
eprint = {1804.11275},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1804-11275.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1807-03611,
author = {Martin Hora and
V{\'{a}}clav Koncick{\'{y}} and
Jakub Tetek},
title = {Theoretical Model of Computation and Algorithms for FPGA-based Hardware
Accelerators},
journal = {CoRR},
volume = {abs/1807.03611},
year = {2018},
url = {http://arxiv.org/abs/1807.03611},
eprinttype = {arXiv},
eprint = {1807.03611},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1807-03611.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1811-08634,
author = {Yifan Yang and
Qijing Huang and
Bichen Wu and
Tianjun Zhang and
Liang Ma and
Giulio Gambardella and
Michaela Blott and
Luciano Lavagno and
Kees A. Vissers and
John Wawrzynek and
Kurt Keutzer},
title = {Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on
Embedded FPGAs},
journal = {CoRR},
volume = {abs/1811.08634},
year = {2018},
url = {http://arxiv.org/abs/1811.08634},
eprinttype = {arXiv},
eprint = {1811.08634},
timestamp = {Thu, 18 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1811-08634.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/dnb/Werner17,
author = {Stefan Werner},
title = {Hybrid architecture for hardware-accelerated query processing in semantic
web databases based on runtime reconfigurable FPGAs},
school = {University of L{\"{u}}beck, Germany},
year = {2017},
url = {http://www.zhb.uni-luebeck.de/epubs/ediss1886.pdf},
urn = {urn:nbn:de:gbv:841-20170927373},
timestamp = {Sat, 17 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/dnb/Werner17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/EbrahimiZ17,
author = {Abbas Ebrahimi and
Mohammad Zandsalimy},
title = {Evaluation of {FPGA} Hardware as a New Approach for Accelerating the
Numerical Solution of {CFD} Problems},
journal = {{IEEE} Access},
volume = {5},
pages = {9717--9727},
year = {2017},
url = {https://doi.org/10.1109/ACCESS.2017.2705434},
doi = {10.1109/ACCESS.2017.2705434},
timestamp = {Wed, 04 Jul 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/EbrahimiZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/asc/BenrejebS17,
author = {Mohamed Sadok Ben Ameur and
Anis Sakly},
title = {{FPGA} based hardware implementation of Bat Algorithm},
journal = {Appl. Soft Comput.},
volume = {58},
pages = {378--387},
year = {2017},
url = {https://doi.org/10.1016/j.asoc.2017.04.015},
doi = {10.1016/J.ASOC.2017.04.015},
timestamp = {Mon, 28 Aug 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/asc/BenrejebS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/concurrency/LiGQDL17,
author = {Yibin Li and
Keke Gai and
Meikang Qiu and
Wenyun Dai and
Meiqin Liu},
title = {Adaptive human detection approach using FPGA-based parallel architecture
in reconfigurable hardware},
journal = {Concurr. Comput. Pract. Exp.},
volume = {29},
number = {14},
year = {2017},
url = {https://doi.org/10.1002/cpe.3923},
doi = {10.1002/CPE.3923},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/concurrency/LiGQDL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/elektrik/AbdelaliKM17,
author = {Abdessalem Ben Abdelali and
Mohamed Nidhal Krifa and
Abdellatif Mtibaa},
title = {FPGA-based {SOC} for hardware implementation of a local histogram-based
video shot detector},
journal = {Turkish J. Electr. Eng. Comput. Sci.},
volume = {25},
pages = {3300--3318},
year = {2017},
url = {https://doi.org/10.3906/elk-1608-94},
doi = {10.3906/ELK-1608-94},
timestamp = {Fri, 04 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/elektrik/AbdelaliKM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/BlockM17,
author = {Henry Block and
Tsutomu Maruyama},
title = {{FPGA} Hardware Acceleration of a Phylogenetic Tree Reconstruction
with Maximum Parsimony Algorithm},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {100-D},
number = {2},
pages = {256--264},
year = {2017},
url = {https://doi.org/10.1587/transinf.2015EDP7433},
doi = {10.1587/TRANSINF.2015EDP7433},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/BlockM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/ParmarRD17,
author = {Chintan A. Parmar and
Bhaskar Ramanadham and
Anand D. Darji},
title = {{FPGA} implementation of hardware efficient adaptive filter robust
to impulsive noise},
journal = {{IET} Comput. Digit. Tech.},
volume = {11},
number = {3},
pages = {107--116},
year = {2017},
url = {https://doi.org/10.1049/iet-cdt.2016.0067},
doi = {10.1049/IET-CDT.2016.0067},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/ParmarRD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijcomsys/StuartP17,
author = {Celine Mary Stuart and
Deepthi P. Pattathil},
title = {{FPGA} implementation of highly secure, hardware-efficient {QC-LDPC}
code-based nonlinear cryptosystem for wireless sensor networks},
journal = {Int. J. Commun. Syst.},
volume = {30},
number = {10},
year = {2017},
url = {https://doi.org/10.1002/dac.3233},
doi = {10.1002/DAC.3233},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijcomsys/StuartP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijhpcn/WangBP17,
author = {Wei Wang and
Miodrag Bolic and
Jonathan Parri},
title = {pvFPGA: paravirtualising an FPGA-based hardware accelerator towards
general purpose computing},
journal = {Int. J. High Perform. Comput. Netw.},
volume = {10},
number = {3},
pages = {179--193},
year = {2017},
url = {https://doi.org/10.1504/IJHPCN.2017.10005140},
doi = {10.1504/IJHPCN.2017.10005140},
timestamp = {Thu, 09 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijhpcn/WangBP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijig/Nnolim17,
author = {Uche Afam Nnolim},
title = {FPGA-Based Multiplier-Less Log-Based Hardware Architectures for Hybrid
Color Image Enhancement System},
journal = {Int. J. Image Graph.},
volume = {17},
number = {1},
pages = {1750004:1--1750004:53},
year = {2017},
url = {https://doi.org/10.1142/S0219467817500048},
doi = {10.1142/S0219467817500048},
timestamp = {Wed, 24 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijig/Nnolim17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijig/Nnolim17a,
author = {Uche Afam Nnolim},
title = {FPGA-Based Hardware Architecture for Fuzzy Homomorphic Enhancement
Based on Partial Differential Equations},
journal = {Int. J. Image Graph.},
volume = {17},
number = {4},
pages = {1750022:1--1750022:46},
year = {2017},
url = {https://doi.org/10.1142/S021946781750022X},
doi = {10.1142/S021946781750022X},
timestamp = {Sat, 21 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijig/Nnolim17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijwmc/Al-HussainiAVHF17,
author = {Khalid Al{-}Hussaini and
Borhanuddin Mohd Ali and
Pooria Varahram and
Shaiful J. Hashim and
Ronan Farrell},
title = {Hardware co-simulation for a low complexity {PAPR} reduction scheme
on an {FPGA}},
journal = {Int. J. Wirel. Mob. Comput.},
volume = {12},
number = {1},
pages = {49--61},
year = {2017},
url = {https://doi.org/10.1504/IJWMC.2017.10003984},
doi = {10.1504/IJWMC.2017.10003984},
timestamp = {Fri, 03 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijwmc/Al-HussainiAVHF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/ZaidanZ17,
author = {B. B. Zaidan and
A. A. Zaidan},
title = {Software and Hardware FPGA-Based Digital Watermarking and Steganography
Approaches: Toward New Methodology for Evaluation and Benchmarking
Using Multi-Criteria Decision-Making Techniques},
journal = {J. Circuits Syst. Comput.},
volume = {26},
number = {7},
pages = {1750116:1--1750116:27},
year = {2017},
url = {https://doi.org/10.1142/S021812661750116X},
doi = {10.1142/S021812661750116X},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/ZaidanZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrtip/SahlbachTE17,
author = {Henning Sahlbach and
Daniel Thiele and
Rolf Ernst},
title = {A system-level {FPGA} design methodology for video applications with
weakly-programmable hardware components},
journal = {J. Real Time Image Process.},
volume = {13},
number = {2},
pages = {291--309},
year = {2017},
url = {https://doi.org/10.1007/s11554-014-0403-4},
doi = {10.1007/S11554-014-0403-4},
timestamp = {Thu, 18 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrtip/SahlbachTE17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/SirkunanOSHM17,
author = {Jeevan Sirkunan and
Chia Yee Ooi and
Nasir Shaikh{-}Husin and
Yuan Wen Hau and
Muhammad N. Marsono},
title = {Hardware transactional memory architecture with adaptive version management
for multi-processor {FPGA} platforms},
journal = {J. Syst. Archit.},
volume = {73},
pages = {42--52},
year = {2017},
url = {https://doi.org/10.1016/j.sysarc.2016.12.006},
doi = {10.1016/J.SYSARC.2016.12.006},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/SirkunanOSHM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/MandalPSCC17,
author = {Swagata Mandal and
Rourab Paul and
Suman Sau and
Amlan Chakrabarti and
Subhasis Chattopadhyay},
title = {Efficient dynamic priority based soft error mitigation techniques
for configuration memory of {FPGA} hardware},
journal = {Microprocess. Microsystems},
volume = {51},
pages = {313--330},
year = {2017},
url = {https://doi.org/10.1016/j.micpro.2016.12.003},
doi = {10.1016/J.MICPRO.2016.12.003},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/MandalPSCC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/MiskovskyKN17,
author = {Vojtech Miskovsk{\'{y}} and
Hana Kub{\'{a}}tov{\'{a}} and
Martin Novotn{\'{y}}},
title = {Influence of passive hardware redundancy on differential power analysis
resistance of {AES} cipher implemented in {FPGA}},
journal = {Microprocess. Microsystems},
volume = {51},
pages = {220--226},
year = {2017},
url = {https://doi.org/10.1016/j.micpro.2017.04.014},
doi = {10.1016/J.MICPRO.2017.04.014},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/MiskovskyKN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/PirpilidisSVK17,
author = {Filippos Pirpilidis and
Kyriakos G. Stefanidis and
Artemios G. Voyiatzis and
Paris Kitsos},
title = {On the effects of ring oscillator length and hardware Trojan size
on an FPGA-based implementation of {AES}},
journal = {Microprocess. Microsystems},
volume = {54},
pages = {75--82},
year = {2017},
url = {https://doi.org/10.1016/j.micpro.2017.09.001},
doi = {10.1016/J.MICPRO.2017.09.001},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/PirpilidisSVK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/WijeyasingheT17,
author = {Marlon Wijeyasinghe and
David Thomas},
title = {Combining hardware and software codecs to enhance data channels in
{FPGA} streaming systems},
journal = {Microprocess. Microsystems},
volume = {51},
pages = {275--288},
year = {2017},
url = {https://doi.org/10.1016/j.micpro.2017.05.003},
doi = {10.1016/J.MICPRO.2017.05.003},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/WijeyasingheT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/Lara-NinoDM17,
author = {Carlos Andres Lara{-}Nino and
Arturo Diaz{-}Perez and
Miguel Morales{-}Sandoval},
title = {Lightweight Hardware Architectures for the Present Cipher in {FPGA}},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {64-I},
number = {9},
pages = {2544--2555},
year = {2017},
url = {https://doi.org/10.1109/TCSI.2017.2686783},
doi = {10.1109/TCSI.2017.2686783},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/Lara-NinoDM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/TakedaT17,
author = {Kentaro Takeda and
Hiroyuki Torikai},
title = {A Novel Hardware-Efficient Cochlea Model Based on Asynchronous Cellular
Automaton Dynamics: Theoretical Analysis and {FPGA} Implementation},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {64-II},
number = {9},
pages = {1107--1111},
year = {2017},
url = {https://doi.org/10.1109/TCSII.2017.2672824},
doi = {10.1109/TCSII.2017.2672824},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/TakedaT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tci/ChenHHC17,
author = {Huan{-}Yuan Chen and
Shu{-}Hao Hsu and
Wen{-}Jyi Hwang and
Chau{-}Jern Cheng},
title = {An Efficient FPGA-Based Parallel Phase Unwrapping Hardware Architecture},
journal = {{IEEE} Trans. Computational Imaging},
volume = {3},
number = {4},
pages = {996--1007},
year = {2017},
url = {https://doi.org/10.1109/TCI.2017.2663767},
doi = {10.1109/TCI.2017.2663767},
timestamp = {Thu, 14 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tci/ChenHHC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoiBA17,
author = {Jongsok Choi and
Stephen Dean Brown and
Jason Helge Anderson},
title = {From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis
for FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2867--2880},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2720623},
doi = {10.1109/TVLSI.2017.2720623},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoiBA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShiLYO17,
author = {Weijing Shi and
Xin Li and
Zhiyi Yu and
Gary Overett},
title = {An FPGA-Based Hardware Accelerator for Traffic Sign Detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1362--1372},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2631428},
doi = {10.1109/TVLSI.2016.2631428},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShiLYO17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/wpc/Al-HussainiAVH17,
author = {Khalid Al{-}Hussaini and
Borhanuddin Mohd Ali and
Pooria Varahram and
Shaiful Jahari Hashim},
title = {Designing and Implementing a Novel Single {IFFT} Scrambling {PAPR}
Reduction Scheme in {OFDM} Systems Using {FPGA} with Hardware Co-simulation},
journal = {Wirel. Pers. Commun.},
volume = {95},
number = {4},
pages = {4763--4788},
year = {2017},
url = {https://doi.org/10.1007/s11277-017-4123-5},
doi = {10.1007/S11277-017-4123-5},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/wpc/Al-HussainiAVH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ahs/SharmaKK17,
author = {Dimple Sharma and
Lev Kirischian and
Valeri Kirischian},
title = {Run-time adaptation method for mitigation of hardware faults and power
budget variations in space-borne FPGA-based systems},
booktitle = {2017 {NASA/ESA} Conference on Adaptive Hardware and Systems, {AHS}
2017, Pasadena, CA, USA, July 24-27, 2017},
pages = {32--39},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/AHS.2017.8046356},
doi = {10.1109/AHS.2017.8046356},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/ahs/SharmaKK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/SantosTBTK17,
author = {Andr{\'{e}} Flores dos Santos and
Lucas Antunes Tambara and
Fabio Benevenuti and
Jorge L. Tonfat and
Fernanda Lima Kastensmidt},
editor = {Stephan Wong and
Antonio Carlos Schneider Beck and
Koen Bertels and
Luigi Carro},
title = {Applying {TMR} in Hardware Accelerators Generated by High-Level Synthesis
Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs},
booktitle = {Applied Reconfigurable Computing - 13th International Symposium, {ARC}
2017, Delft, The Netherlands, April 3-7, 2017, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10216},
pages = {202--213},
year = {2017},
url = {https://doi.org/10.1007/978-3-319-56258-2\_18},
doi = {10.1007/978-3-319-56258-2\_18},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arc/SantosTBTK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ches/JacobHZRS17,
author = {Nisha Jacob and
Johann Heyszl and
Andreas Zankl and
Carsten Rolfes and
Georg Sigl},
editor = {Wieland Fischer and
Naofumi Homma},
title = {How to Break Secure Boot on {FPGA} SoCs Through Malicious Hardware},
booktitle = {Cryptographic Hardware and Embedded Systems - {CHES} 2017 - 19th International
Conference, Taipei, Taiwan, September 25-28, 2017, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10529},
pages = {425--442},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-319-66787-4\_21},
doi = {10.1007/978-3-319-66787-4\_21},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ches/JacobHZRS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicba/MandalMPC17,
author = {Himadri S. Mandal and
Goutam Kr. Maity and
Amit Phadikar and
Tien{-}Lung Chiu},
editor = {Jyotsna Kumar Mandal and
Paramartha Dutta and
Somnath Mukhopadhyay},
title = {{FPGA} Based Low Power Hardware Implementation for Quality Access
Control of a Compressed Gray Scale Image},
booktitle = {Computational Intelligence, Communications, and Business Analytics
- First International Conference, {CICBA} 2017, Kolkata, India, March
24-25, 2017, Revised Selected Papers, Part {I}},
series = {Communications in Computer and Information Science},
volume = {775},
pages = {416--430},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-981-10-6427-2\_34},
doi = {10.1007/978-981-10-6427-2\_34},
timestamp = {Tue, 20 Apr 2021 14:33:22 +0200},
biburl = {https://dblp.org/rec/conf/cicba/MandalMPC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/ReichenbachHHLB17,
author = {Marc Reichenbach and
Philipp Holzinger and
Konrad H{\"{a}}ublein and
Tobias Lieske and
Paul Blinzer and
Dietmar Fey},
title = {LibHSA: One step towards mastering the era of heterogeneous hardware
accelerators using FPGAs},
booktitle = {2017 Conference on Design and Architectures for Signal and Image Processing,
{DASIP} 2017, Dresden, Germany, September 27-29, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/DASIP.2017.8122108},
doi = {10.1109/DASIP.2017.8122108},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/ReichenbachHHLB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/JacobRZHS17,
author = {Nisha Jacob and
Carsten Rolfes and
Andreas Zankl and
Johann Heyszl and
Georg Sigl},
editor = {David Atienza and
Giorgio Di Natale},
title = {Compromising {FPGA} SoCs using malicious hardware blocks},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {1122--1127},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7927157},
doi = {10.23919/DATE.2017.7927157},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/JacobRZHS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/PyrgasPPK17,
author = {Lampros Pyrgas and
Filippos Pirpilidis and
Aliki Panayiotarou and
Paris Kitsos},
editor = {Hana Kub{\'{a}}tov{\'{a}} and
Martin Novotn{\'{y}} and
Amund Skavhaug},
title = {Thermal Sensor Based Hardware Trojan Detection in FPGAs},
booktitle = {Euromicro Conference on Digital System Design, {DSD} 2017, Vienna,
Austria, August 30 - Sept. 1, 2017},
pages = {268--273},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/DSD.2017.36},
doi = {10.1109/DSD.2017.36},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/PyrgasPPK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/BanerjeeELCKCI17,
author = {Subho S. Banerjee and
Mohamed El{-}Hadedy and
Jong Bin Lim and
Daniel Chen and
Zbigniew T. Kalbarczyk and
Deming Chen and
Ravishankar K. Iyer},
editor = {Jonathan W. Greene and
Jason Helge Anderson},
title = {{ASAP:} Accelerated Short Read Alignment on Programmable Hardware
(Abstract Only)},
booktitle = {Proceedings of the 2017 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2017, Monterey, CA, USA, February 22-24, 2017},
pages = {293--294},
publisher = {{ACM}},
year = {2017},
url = {http://dl.acm.org/citation.cfm?id=3021796},
timestamp = {Thu, 02 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/BanerjeeELCKCI17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/BobdaWKKN17,
author = {Christophe Bobda and
Taylor J. L. Whitaker and
Charles A. Kamhoua and
Kevin A. Kwiat and
Laurent Njilla},
editor = {Jonathan W. Greene and
Jason Helge Anderson},
title = {Automatic Generation of Hardware Sandboxes for Trojan Mitigation in
Systems on Chip (Abstract Only)},
booktitle = {Proceedings of the 2017 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2017, Monterey, CA, USA, February 22-24, 2017},
pages = {289},
publisher = {{ACM}},
year = {2017},
url = {http://dl.acm.org/citation.cfm?id=3021774},
timestamp = {Sun, 05 Mar 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/BobdaWKKN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HuangMRRHC17,
author = {Sitao Huang and
Gowthami Jayashri Manikandan and
Anand Ramachandran and
Kyle Rupnow and
Wen{-}mei W. Hwu and
Deming Chen},
editor = {Jonathan W. Greene and
Jason Helge Anderson},
title = {Hardware Acceleration of the Pair-HMM Algorithm for {DNA} Variant
Calling},
booktitle = {Proceedings of the 2017 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2017, Monterey, CA, USA, February 22-24, 2017},
pages = {275--284},
publisher = {{ACM}},
year = {2017},
url = {http://dl.acm.org/citation.cfm?id=3021749},
timestamp = {Fri, 08 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/HuangMRRHC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/PezzottiINCVA17,
author = {Emanuele Pezzotti and
Alex Iacobucci and
Gregory Nash and
Umer I. Cheema and
Paolo Vinella and
Rashid Ansari},
editor = {Jonathan W. Greene and
Jason Helge Anderson},
title = {FPGA-based Hardware Accelerator for Image Reconstruction in Magnetic
Resonance Imaging (Abstract Only)},
booktitle = {Proceedings of the 2017 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2017, Monterey, CA, USA, February 22-24, 2017},
pages = {293},
publisher = {{ACM}},
year = {2017},
url = {http://dl.acm.org/citation.cfm?id=3021793},
timestamp = {Fri, 03 Feb 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/PezzottiINCVA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/RamanathanFWC17,
author = {Nadesh Ramanathan and
Shane T. Fleming and
John Wickerson and
George A. Constantinides},
editor = {Jonathan W. Greene and
Jason Helge Anderson},
title = {Hardware Synthesis of Weakly Consistent {C} Concurrency},
booktitle = {Proceedings of the 2017 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2017, Monterey, CA, USA, February 22-24, 2017},
pages = {169--178},
publisher = {{ACM}},
year = {2017},
url = {http://dl.acm.org/citation.cfm?id=3021733},
timestamp = {Fri, 03 Feb 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/RamanathanFWC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpgaworld/WehbeMKIJ17,
author = {Taimour Wehbe and
Vincent John Mooney and
David C. Keezer and
Omer T. Inan and
Abdul Qadir Javaid},
editor = {Lennart Lindh and
Ketil R{\o}ed and
Vincent John Mooney III and
Johnny {\"{O}}berg and
Johan Alme and
Santiago De Pablo and
Mohamed Shalan},
title = {Use of Analog Signatures for Hardware Trojan Detection},
booktitle = {Proceedings of the 14th FPGAworld Conference, FPGAworld '17, Stockholm,
Sweden, September 19, 2017},
pages = {15--22},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3135997.3135998},
doi = {10.1145/3135997.3135998},
timestamp = {Fri, 28 Jan 2022 15:02:55 +0100},
biburl = {https://dblp.org/rec/conf/fpgaworld/WehbeMKIJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/BlockM17,
author = {Henry Block and
Tsutomu Maruyama},
editor = {Marco D. Santambrogio and
Diana G{\"{o}}hringer and
Dirk Stroobandt and
Nele Mentens and
Jari Nurmi},
title = {An {FPGA} hardware implementation approach for a phylogenetic tree
reconstruction algorithm with incremental tree optimization},
booktitle = {27th International Conference on Field Programmable Logic and Applications,
{FPL} 2017, Ghent, Belgium, September 4-8, 2017},
pages = {1--8},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/FPL.2017.8056839},
doi = {10.23919/FPL.2017.8056839},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/BlockM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/Bolsens17,
author = {Ivo Bolsens},
editor = {Marco D. Santambrogio and
Diana G{\"{o}}hringer and
Dirk Stroobandt and
Nele Mentens and
Jari Nurmi},
title = {"All programmable FPGA, providing hardware efficiency to software
programmers"},
booktitle = {27th International Conference on Field Programmable Logic and Applications,
{FPL} 2017, Ghent, Belgium, September 4-8, 2017},
pages = {1--3},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/FPL.2017.8056755},
doi = {10.23919/FPL.2017.8056755},
timestamp = {Wed, 11 Oct 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/Bolsens17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/CabaRG17,
author = {Juli{\'{a}}n Caba and
Fernando Rinc{\'{o}}n and
Julio Dondo Gazzano},
editor = {Marco D. Santambrogio and
Diana G{\"{o}}hringer and
Dirk Stroobandt and
Nele Mentens and
Jari Nurmi},
title = {Functional {\&} timing in-hardware verification of FPGA-based
designs using unit testing frameworks},
booktitle = {27th International Conference on Field Programmable Logic and Applications,
{FPL} 2017, Ghent, Belgium, September 4-8, 2017},
pages = {1--2},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/FPL.2017.8056849},
doi = {10.23919/FPL.2017.8056849},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/CabaRG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/LinZS17,
author = {Zhe Lin and
Wei Zhang and
Sharad Sinha},
editor = {Marco D. Santambrogio and
Diana G{\"{o}}hringer and
Dirk Stroobandt and
Nele Mentens and
Jari Nurmi},
title = {Decision tree based hardware power monitoring for run time dynamic
power management in {FPGA}},
booktitle = {27th International Conference on Field Programmable Logic and Applications,
{FPL} 2017, Ghent, Belgium, September 4-8, 2017},
pages = {1--8},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/FPL.2017.8056832},
doi = {10.23919/FPL.2017.8056832},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/LinZS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/DHollanderCB17,
author = {Erik H. D'Hollander and
Bruno Chevalier and
Koen De Bosschere},
title = {Calling hardware procedures in a reconfigurable accelerator using
{RPC-FPGA}},
booktitle = {International Conference on Field Programmable Technology, {FPT} 2017,
Melbourne, Australia, December 11-13, 2017},
pages = {271--274},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/FPT.2017.8280158},
doi = {10.1109/FPT.2017.8280158},
timestamp = {Mon, 17 Feb 2020 13:32:07 +0100},
biburl = {https://dblp.org/rec/conf/fpt/DHollanderCB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Putnam17,
author = {Andrew Putnam},
editor = {Laleh Behjat and
Jie Han and
Miroslav N. Velev and
Deming Chen},
title = {FPGAs in the Datacenter: Combining the Worlds of Hardware and Software
Development},
booktitle = {Proceedings of the on Great Lakes Symposium on {VLSI} 2017, Banff,
AB, Canada, May 10-12, 2017},
pages = {5},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3060403.3066860},
doi = {10.1145/3060403.3066860},
timestamp = {Tue, 06 Nov 2018 16:59:34 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Putnam17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/SakakibaraNM17,
author = {Yuma Sakakibara and
Kohei Nakamura and
Hiroki Matsutani},
editor = {Diana G{\"{o}}hringer and
Michael H{\"{u}}bner},
title = {An {FPGA} {NIC} Based Hardware Caching for Blockchain},
booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
Germany, June 7-9, 2017},
pages = {1:1--1:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3120895.3120897},
doi = {10.1145/3120895.3120897},
timestamp = {Wed, 28 Apr 2021 16:06:55 +0200},
biburl = {https://dblp.org/rec/conf/heart/SakakibaraNM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/SozzoBAS17,
author = {Emanuele Del Sozzo and
Riyadh Baghdadi and
Saman P. Amarasinghe and
Marco D. Santambrogio},
title = {A Common Backend for Hardware Acceleration on {FPGA}},
booktitle = {2017 {IEEE} International Conference on Computer Design, {ICCD} 2017,
Boston, MA, USA, November 5-8, 2017},
pages = {427--430},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ICCD.2017.75},
doi = {10.1109/ICCD.2017.75},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/SozzoBAS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icdsc/AbdaliHPDB17,
author = {El Mehdi Abdali and
Abderrahmane Walid Hanniche and
Maxime Pelcat and
Jean{-}Philippe Diguet and
Fran{\c{c}}ois Berry},
editor = {Miguel O. Arias{-}Estrada and
Christian Micheloni and
Hamid K. Aghajan and
Octavia I. Camps and
V{\'{\i}}ctor M. Brea},
title = {Hardware Acceleration of the Tracking Learning Detection {(TLD)} Algorithm
on {FPGA}},
booktitle = {Proceedings of the 11th International Conference on Distributed Smart
Cameras, Stanford, CA, USA, September 5-7, 2017},
pages = {180--185},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3131885.3131933},
doi = {10.1145/3131885.3131933},
timestamp = {Tue, 29 Jun 2021 10:04:17 +0200},
biburl = {https://dblp.org/rec/conf/icdsc/AbdaliHPDB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icm2/BousmarMHDD17,
author = {Khadija Bousmar and
Fabrice Monteiro and
Zineb Habbas and
Sofi{\`{e}}ne Dellagi and
Abbas Dandache},
title = {A pure hardware k-SAT solver architecture for {FPGA} based on generic
tree-search},
booktitle = {29th International Conference on Microelectronics, {ICM} 2017, Beirut,
Lebanon, December 10-13, 2017},
pages = {1--5},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ICM.2017.8268894},
doi = {10.1109/ICM.2017.8268894},
timestamp = {Mon, 09 Aug 2021 14:54:02 +0200},
biburl = {https://dblp.org/rec/conf/icm2/BousmarMHDD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iconip/YeohMT17,
author = {Yoeng Jye Yeoh and
Takashi Morie and
Hakaru Tamukoh},
editor = {Derong Liu and
Shengli Xie and
Yuanqing Li and
Dongbin Zhao and
El{-}Sayed M. El{-}Alfy},
title = {A Hardware-Oriented Dropout Algorithm for Efficient {FPGA} Implementation},
booktitle = {Neural Information Processing - 24th International Conference, {ICONIP}
2017, Guangzhou, China, November 14-18, 2017, Proceedings, Part {VI}},
series = {Lecture Notes in Computer Science},
volume = {10639},
pages = {821--829},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-319-70136-3\_87},
doi = {10.1007/978-3-319-70136-3\_87},
timestamp = {Tue, 14 May 2019 10:00:42 +0200},
biburl = {https://dblp.org/rec/conf/iconip/YeohMT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icufn/SenouciRHB17,
author = {Benaoumeur Senouci and
H. Rouis and
Dong{-}Seog Han and
E. Bourennanea},
title = {A hardware skin-segmentation {IP} for vision based smart {ADAS} through
an {FPGA} prototyping},
booktitle = {Ninth International Conference on Ubiquitous and Future Networks,
{ICUFN} 2017, Milan, Italy, July 4-7, 2017},
pages = {197--199},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ICUFN.2017.7993774},
doi = {10.1109/ICUFN.2017.7993774},
timestamp = {Wed, 16 Oct 2019 14:14:51 +0200},
biburl = {https://dblp.org/rec/conf/icufn/SenouciRHB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/idaacs/KravetsSS17,
author = {Petro I. Kravets and
Volodymyr M. Shymkovych and
Volodymyr Samotyy},
title = {Method and technology of synthesis of neural network models of object
control with their hardware implementation on {FPGA}},
booktitle = {9th {IEEE} International Conference on Intelligent Data Acquisition
and Advanced Computing Systems: Technology and Applications, {IDAACS}
2017, Bucharest, Romania, September 21-23, 2017},
pages = {947--951},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/IDAACS.2017.8095226},
doi = {10.1109/IDAACS.2017.8095226},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/idaacs/KravetsSS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChangC17,
author = {Andre Xian Ming Chang and
Eugenio Culurciello},
title = {Hardware accelerators for recurrent neural networks on {FPGA}},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,
Baltimore, MD, USA, May 28-31, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISCAS.2017.8050816},
doi = {10.1109/ISCAS.2017.8050816},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChangC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/EnemaliAA17,
author = {Godwin Enemali and
Adewale Adetomi and
Tughrul Arslan},
title = {A placement management circuit for efficient realtime hardware reuse
on FPGAs targeting reliable autonomous systems},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,
Baltimore, MD, USA, May 28-31, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISCAS.2017.8050796},
doi = {10.1109/ISCAS.2017.8050796},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/EnemaliAA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispa/ZhangWGLSXLZ17,
author = {Yiwei Zhang and
Chao Wang and
Lei Gong and
Yuntao Lu and
Fan Sun and
Chongchong Xu and
Xi Li and
Xuehai Zhou},
title = {Implementation and Optimization of the Accelerator Based on {FPGA}
Hardware for {LSTM} Network},
booktitle = {2017 {IEEE} International Symposium on Parallel and Distributed Processing
with Applications and 2017 {IEEE} International Conference on Ubiquitous
Computing and Communications (ISPA/IUCC), Guangzhou, China, December
12-15, 2017},
pages = {614--621},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISPA/IUCC.2017.00098},
doi = {10.1109/ISPA/IUCC.2017.00098},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispa/ZhangWGLSXLZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/KamaleldinHMGHE17,
author = {Ahmed Kamaleldin and
Sherif Hosny and
Khaled Mohamed and
Mostafa Gamal and
Abdelrhman Hussien and
Eslam Elnader and
Ahmed Shalash and
Abdelfattah Mohammad Obeid and
Yehea Ismail and
Hassan Mostafa},
title = {A reconfigurable hardware platform implementation for software defined
radio using dynamic partial reconfiguration on Xilinx Zynq {FPGA}},
booktitle = {{IEEE} 60th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2017, Boston, MA, USA, August 6-9, 2017},
pages = {1540--1543},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/MWSCAS.2017.8053229},
doi = {10.1109/MWSCAS.2017.8053229},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/KamaleldinHMGHE17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nds/VeltenWKKTSK17,
author = {J{\"{o}}rg Velten and
Daniel Wagner and
Lech Kolonko and
Kathrin Kalischewski and
Stephan Tilgner and
Tim Schwerdtfeger and
Anton Kummert},
title = {Examination of direct form vs. {WDF} realization of a 2-D quadrantal
fan filter in {FPGA} hardware},
booktitle = {10th International Workshop on Multidimensional (nD) Systems (nDS),
nDS 2017, Zielona G{\'{o}}ra, Poland, September 13-15, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/NDS.2017.8070614},
doi = {10.1109/NDS.2017.8070614},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nds/VeltenWKKTSK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rcar/FanLLZJLC17,
author = {Kun Fan and
Congyi Lyu and
Yunhui Liu and
Weiguo Zhou and
Xin Jiang and
Peng Li and
Haoyao Chen},
title = {Hardware implementation of a virtual blind cane on {FPGA}},
booktitle = {2017 {IEEE} International Conference on Real-time Computing and Robotics,
{RCAR} 2017, Okinawa, Japan, July 14-18, 2017},
pages = {344--348},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/RCAR.2017.8311885},
doi = {10.1109/RCAR.2017.8311885},
timestamp = {Mon, 01 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rcar/FanLLZJLC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/SilvaANSHF17,
author = {Lucas B. da Silva and
Danilo Dami{\~{a}}o Almeida and
Jos{\'{e}} Augusto Miranda Nacif and
Ismael Sanchez{-}Osorio and
Carlos A. Hernandez{-}Martinez and
Ricardo Ferreira},
title = {Exploring the dynamics of large-scale gene regulatory networks using
hardware acceleration on a heterogeneous {CPU-FPGA} platform},
booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig
2017, Cancun, Mexico, December 4-6, 2017},
pages = {1--7},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/RECONFIG.2017.8279791},
doi = {10.1109/RECONFIG.2017.8279791},
timestamp = {Tue, 07 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/SilvaANSHF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtas/ShriramBJS17,
author = {S. Shriram and
Raghavendra Barkur and
Joshua Produkku and
B. Shanthibhushan},
editor = {Gabriel Parmer},
title = {Work-in-Progress: {FPGA} Implementation of Synchronous Serial Interface
for Hardware in Loop Simulation},
booktitle = {2017 {IEEE} Real-Time and Embedded Technology and Applications Symposium,
{RTAS} 2017, Pittsburg, PA, USA, April 18-21, 2017},
pages = {133--136},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/RTAS.2017.28},
doi = {10.1109/RTAS.2017.28},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rtas/ShriramBJS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sac/MakniBNA17,
author = {Mariem Makni and
Mouna Baklouti and
Sma{\"{\i}}l Niar and
Mohamed Abid},
editor = {Ahmed Seffah and
Birgit Penzenstadler and
Carina Alves and
Xin Peng},
title = {Hardware resource estimation for heterogeneous FPGA-based SoCs},
booktitle = {Proceedings of the Symposium on Applied Computing, {SAC} 2017, Marrakech,
Morocco, April 3-7, 2017},
pages = {1481--1487},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3019612.3019683},
doi = {10.1145/3019612.3019683},
timestamp = {Wed, 01 Feb 2023 17:58:48 +0100},
biburl = {https://dblp.org/rec/conf/sac/MakniBNA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/BortolonM17,
author = {Felipe T. Bortolon and
Fernando Gehm Moraes},
editor = {Jarbas A. N. Silveira},
title = {Hardware and software infrastructure to implement many-core systems
in modern FPGAs},
booktitle = {Proceedings of the 30th Symposium on Integrated Circuits and Systems
Design: Chip on the Sands, {SBCCI} 2017, Fortaleza, Cear{\'{a}},
Brazil, August 28 - September 01, 2017},
pages = {79--83},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3109984.3109997},
doi = {10.1145/3109984.3109997},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/BortolonM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:series/sci/Ontiveros-RoblesVCC17,
author = {Emanuel Ontiveros{-}Robles and
Jos{\'{e}} Gonz{\'{a}}lez V{\'{a}}zquez and
Juan R. Castro and
Oscar Castillo},
editor = {Patricia Melin and
Oscar Castillo and
Janusz Kacprzyk},
title = {A FPGA-Based Hardware Architecture Approach for Real-Time Fuzzy Edge
Detection},
booktitle = {Nature-Inspired Design of Hybrid Intelligent Systems},
series = {Studies in Computational Intelligence},
volume = {667},
pages = {519--540},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-319-47054-2\_34},
doi = {10.1007/978-3-319-47054-2\_34},
timestamp = {Tue, 07 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/series/sci/Ontiveros-RoblesVCC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/BayerCEM17,
author = {F{\'{a}}bio M. Bayer and
Renato J. Cintra and
Amila Edirisuriya and
Arjuna Madanayake},
title = {A Digital Hardware Fast Algorithm and FPGA-based Prototype for a Novel
16-point Approximate {DCT} for Image Compression Applications},
journal = {CoRR},
volume = {abs/1702.01805},
year = {2017},
url = {http://arxiv.org/abs/1702.01805},
eprinttype = {arXiv},
eprint = {1702.01805},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/BayerCEM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/BreierH17,
author = {Jakub Breier and
Wei He},
title = {Multiple Fault Attack on {PRESENT} with a Hardware Trojan Implementation
in {FPGA}},
journal = {CoRR},
volume = {abs/1702.08208},
year = {2017},
url = {http://arxiv.org/abs/1702.08208},
eprinttype = {arXiv},
eprint = {1702.08208},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/BreierH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1711-01010,
author = {Amr Al{-}Anwar and
Mona A. Aboelnaga and
Yousra Alkabani and
M. Watheq El{-}Kharashi and
Hassan Bedour},
title = {Dynamic {FPGA} Detection and Protection of Hardware Trojan: {A} Comparative
Analysis},
journal = {CoRR},
volume = {abs/1711.01010},
year = {2017},
url = {http://arxiv.org/abs/1711.01010},
eprinttype = {arXiv},
eprint = {1711.01010},
timestamp = {Tue, 15 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-1711-01010.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1711-05860,
author = {Yufeng Hao},
title = {A General Neural Network Hardware Architecture on {FPGA}},
journal = {CoRR},
volume = {abs/1711.05860},
year = {2017},
url = {http://arxiv.org/abs/1711.05860},
eprinttype = {arXiv},
eprint = {1711.05860},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1711-05860.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iacr/JacobHZRS17,
author = {Nisha Jacob and
Johann Heyszl and
Andreas Zankl and
Carsten Rolfes and
Georg Sigl},
title = {How to Break Secure Boot on {FPGA} SoCs through Malicious Hardware},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {625},
year = {2017},
url = {http://eprint.iacr.org/2017/625},
timestamp = {Mon, 11 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iacr/JacobHZRS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/ch/George16,
author = {Nithin George},
title = {FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific
Languages},
school = {EPFL, Switzerland},
year = {2016},
url = {https://doi.org/10.5075/epfl-thesis-7004},
doi = {10.5075/EPFL-THESIS-7004},
timestamp = {Fri, 29 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/ch/George16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/hal/Alhamwi16,
author = {Ali Alhamwi},
title = {Co-design Hardware/Software of Real time Vision System on {FPGA} for
Obstacle Detection. (Conception conjointe mat{\'{e}}riel/logiciel
de syst{\`{e}}me de Vision en temps r{\'{e}}el sur le {FPGA}
pour la d{\'{e}}tection d'Obstacle)},
school = {Paul Sabatier University, Toulouse, France},
year = {2016},
url = {https://tel.archives-ouvertes.fr/tel-01483746},
timestamp = {Tue, 21 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/hal/Alhamwi16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/hal/Bourge16,
author = {Alban Bourge},
title = {Changement de contexte mat{\'{e}}riel sur {FPGA} entre {\'{e}}quipements
reconfigurables et h{\'{e}}t{\'{e}}rog{\`{e}}nes dans un
environnement de calcul distribu{\'{e}}. (Hardware task context
switch on {FPGA} between heterogeneous reconfigurable devices in a
cloud-FPGA environment)},
school = {Grenoble Alpes University, France},
year = {2016},
url = {https://tel.archives-ouvertes.fr/tel-01474177},
timestamp = {Tue, 21 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/hal/Bourge16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cee/Frances-Villora16,
author = {Jos{\'{e}} Vicente Franc{\'{e}}s{-}V{\'{\i}}llora and
Alfredo Rosado Mu{\~{n}}oz and
Jos{\'{e}} M. Mart{\'{\i}}nez{-}Villena and
Manuel Bataller{-}Mompe{\'{a}}n and
Juan{-}Francisco Guerrero{-}Mart{\'{\i}}nez and
Marek Wegrzyn},
title = {Hardware implementation of real-time Extreme Learning Machine in {FPGA:}
Analysis of precision, resource occupation and performance},
journal = {Comput. Electr. Eng.},
volume = {51},
pages = {139--156},
year = {2016},
url = {https://doi.org/10.1016/j.compeleceng.2016.02.007},
doi = {10.1016/J.COMPELECENG.2016.02.007},
timestamp = {Wed, 19 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cee/Frances-Villora16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cee/ShahadiJW16,
author = {Haider Ismael Shahadi and
Razali Jidin and
Wong Hung Way},
title = {Concurrent hardware architecture for dual-mode audio steganography
processor-based {FPGA}},
journal = {Comput. Electr. Eng.},
volume = {49},
pages = {95--116},
year = {2016},
url = {https://doi.org/10.1016/j.compeleceng.2015.03.007},
doi = {10.1016/J.COMPELECENG.2015.03.007},
timestamp = {Wed, 19 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cee/ShahadiJW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cse/Arcas-AbellaA0M16,
author = {Oriol Arcas{-}Abella and
Adri{\`{a}} Armejach and
Timothy Hayes and
Gorker Alp Malazgirt and
Oscar Palomar and
Behzad Salami and
Nehir S{\"{o}}nmez},
title = {Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs,
and Memory},
journal = {Comput. Sci. Eng.},
volume = {18},
number = {1},
pages = {80--87},
year = {2016},
url = {https://doi.org/10.1109/MCSE.2016.16},
doi = {10.1109/MCSE.2016.16},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cse/Arcas-AbellaA0M16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ejes/MuttilloVFPFTF16,
author = {Vittoriano Muttillo and
Giacomo Valente and
Fabio Federici and
Luigi Pomante and
Marco Faccio and
Carlo Tieri and
Serenella Ferri},
title = {A design methodology for soft-core platforms on {FPGA} with {SMP}
Linux, OpenMP support, and distributed hardware profiling system},
journal = {{EURASIP} J. Embed. Syst.},
volume = {2016},
pages = {15},
year = {2016},
url = {https://doi.org/10.1186/s13639-016-0051-9},
doi = {10.1186/S13639-016-0051-9},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ejes/MuttilloVFPFTF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/evs/YahiTBM16,
author = {Amira Yahi and
Salah Toumi and
El{-}Bay Bourennane and
Kamel Messaoudi},
title = {A speed {FPGA} hardware accelerator based {FSBMA-VBSME} used in {H.264/AVC}},
journal = {Evol. Syst.},
volume = {7},
number = {4},
pages = {233--241},
year = {2016},
url = {https://doi.org/10.1007/s12530-015-9140-6},
doi = {10.1007/S12530-015-9140-6},
timestamp = {Wed, 12 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/evs/YahiTBM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijcat/FredjAMA16,
author = {Amira Hadj Fredj and
Mariem Ben Abdallah and
Jihene Malek and
Ahmad Taher Azar},
title = {Fundus image denoising using {FPGA} hardware architecture},
journal = {Int. J. Comput. Appl. Technol.},
volume = {54},
number = {1},
pages = {1--13},
year = {2016},
url = {https://doi.org/10.1504/IJCAT.2016.077791},
doi = {10.1504/IJCAT.2016.077791},
timestamp = {Sat, 27 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijcat/FredjAMA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijon/ClementeMASMZFV16,
author = {Juan Antonio Clemente and
Wassim Mansour and
Rafic Ayoubi and
Felipe Serrano and
Hortensia Mecha and
Haissam Ziade and
Wassim El Falou and
Raoul Velazco},
title = {Hardware implementation of a fault-tolerant Hopfield Neural Network
on FPGAs},
journal = {Neurocomputing},
volume = {171},
pages = {1606--1609},
year = {2016},
url = {https://doi.org/10.1016/j.neucom.2015.06.038},
doi = {10.1016/J.NEUCOM.2015.06.038},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijon/ClementeMASMZFV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrtip/Kurdthongmee16,
author = {W. Kurdthongmee},
title = {A hardware centric algorithm for the best matching unit searching
stage of the SOM-based quantizer and its {FPGA} implementation},
journal = {J. Real Time Image Process.},
volume = {12},
number = {1},
pages = {71--80},
year = {2016},
url = {https://doi.org/10.1007/s11554-013-0387-5},
doi = {10.1007/S11554-013-0387-5},
timestamp = {Thu, 18 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrtip/Kurdthongmee16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/CotretGF16,
author = {Pascal Cotret and
Guy Gogniat and
Martha Johanna Sep{\'{u}}lveda Fl{\'{o}}rez},
title = {Protection of heterogeneous architectures on FPGAs: An approach based
on hardware firewalls},
journal = {Microprocess. Microsystems},
volume = {42},
pages = {127--141},
year = {2016},
url = {https://doi.org/10.1016/j.micpro.2016.01.013},
doi = {10.1016/J.MICPRO.2016.01.013},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/CotretGF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/Milik16,
author = {Adam Milik},
title = {On hardware synthesis and implementation of {PLC} programs in FPGAs},
journal = {Microprocess. Microsystems},
volume = {44},
pages = {2--16},
year = {2016},
url = {https://doi.org/10.1016/j.micpro.2016.02.003},
doi = {10.1016/J.MICPRO.2016.02.003},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/Milik16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tmscs/Mal-SarkarKNGKB16,
author = {Sanchita Mal{-}Sarkar and
Robert Karam and
Seetharam Narasimhan and
Anandaroop Ghosh and
Aswin Raghav Krishna and
Swarup Bhunia},
title = {Design and Validation for {FPGA} Trust under Hardware Trojan Attacks},
journal = {{IEEE} Trans. Multi Scale Comput. Syst.},
volume = {2},
number = {3},
pages = {186--198},
year = {2016},
url = {https://doi.org/10.1109/TMSCS.2016.2584052},
doi = {10.1109/TMSCS.2016.2584052},
timestamp = {Wed, 02 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tmscs/Mal-SarkarKNGKB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/Ortega-Zamorano16,
author = {Francisco Ortega{-}Zamorano and
Marcelo A. Montemurro and
Sergio Alejandro Cannas and
Jos{\'{e}} M. Jerez and
Leonardo Franco},
title = {{FPGA} Hardware Acceleration of Monte Carlo Simulations for the Ising
Model},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {27},
number = {9},
pages = {2618--2627},
year = {2016},
url = {https://doi.org/10.1109/TPDS.2015.2505725},
doi = {10.1109/TPDS.2015.2505725},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/Ortega-Zamorano16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/WangZLWZ16,
author = {Chao Wang and
Junneng Zhang and
Xi Li and
Aili Wang and
Xuehai Zhou},
title = {Hardware Implementation on {FPGA} for Task-Level Parallel Dataflow
Execution Engine},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {27},
number = {8},
pages = {2303--2315},
year = {2016},
url = {https://doi.org/10.1109/TPDS.2015.2487346},
doi = {10.1109/TPDS.2015.2487346},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/WangZLWZ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/LeeOJLKL16,
author = {Sang Muk Lee and
Jung{-}Hwan Oh and
Ji Hoon Jang and
Seong Mo Lee and
Ji Kwang Kim and
Seung Eun Lee},
title = {Live demonstration: An {FPGA} based hardware compression accelerator
for Hadoop system},
booktitle = {2016 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
2016, Jeju, South Korea, October 25-28, 2016},
pages = {744--745},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/APCCAS.2016.7804035},
doi = {10.1109/APCCAS.2016.7804035},
timestamp = {Fri, 01 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/apccas/LeeOJLKL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/KellySBWWR16,
author = {Colm Kelly and
Fahad Manzoor Siddiqui and
Burak Bardak and
Yun Wu and
Roger F. Woods and
Karen Rafferty},
editor = {Vanderlei Bonato and
Christos Bouganis and
Marek Gorgon},
title = {{FPGA} Soft-Core Processors, Compiler and Hardware Optimizations Validated
Using {HOG}},
booktitle = {Applied Reconfigurable Computing - 12th International Symposium, {ARC}
2016, Mangaratiba, RJ, Brazil, March 22-24, 2016, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {9625},
pages = {78--90},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-30481-6\_7},
doi = {10.1007/978-3-319-30481-6\_7},
timestamp = {Tue, 14 May 2019 10:00:49 +0200},
biburl = {https://dblp.org/rec/conf/arc/KellySBWWR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/ChoiLBA16,
author = {Jongsok Choi and
Ruolong Lian and
Stephen Dean Brown and
Jason Helge Anderson},
title = {A unified software approach to specify pipeline and spatial parallelism
in {FPGA} hardware},
booktitle = {27th {IEEE} International Conference on Application-specific Systems,
Architectures and Processors, {ASAP} 2016, London, United Kingdom,
July 6-8, 2016},
pages = {75--82},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ASAP.2016.7760775},
doi = {10.1109/ASAP.2016.7760775},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/ChoiLBA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/YuanLLY16,
author = {Zhe Yuan and
Yongpan Liu and
Hehe Li and
Huazhong Yang},
title = {{CP-FPGA:} Computation data-aware software/hardware co-design for
nonvolatile FPGAs based on checkpointing techniques},
booktitle = {21st Asia and South Pacific Design Automation Conference, {ASP-DAC}
2016, Macao, Macao, January 25-28, 2016},
pages = {569--574},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASPDAC.2016.7428072},
doi = {10.1109/ASPDAC.2016.7428072},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/YuanLLY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cd/BarbareschiCM16,
author = {Mario Barbareschi and
Alessandro Cilardo and
Antonino Mazzeo},
editor = {Gianluca Palermo and
John Feo},
title = {Partial {FPGA} bitstream encryption enabling hardware {DRM} in mobile
environments},
booktitle = {Proceedings of the {ACM} International Conference on Computing Frontiers,
CF'16, Como, Italy, May 16-19, 2016},
pages = {443--448},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2903150.2911711},
doi = {10.1145/2903150.2911711},
timestamp = {Tue, 06 Nov 2018 11:07:33 +0100},
biburl = {https://dblp.org/rec/conf/cd/BarbareschiCM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ches/JarvinenMAL16,
author = {Kimmo J{\"{a}}rvinen and
Andrea Miele and
Reza Azarderakhsh and
Patrick Longa},
editor = {Benedikt Gierlichs and
Axel Y. Poschmann},
title = {Four {\(\mathbb{Q}\)} on {FPGA:} New Hardware Speed Records for Elliptic
Curve Cryptography over Large Prime Characteristic Fields},
booktitle = {Cryptographic Hardware and Embedded Systems - {CHES} 2016 - 18th International
Conference, Santa Barbara, CA, USA, August 17-19, 2016, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {9813},
pages = {517--537},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-662-53140-2\_25},
doi = {10.1007/978-3-662-53140-2\_25},
timestamp = {Tue, 14 May 2019 10:00:47 +0200},
biburl = {https://dblp.org/rec/conf/ches/JarvinenMAL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/chinacom/TangZ0Z16,
author = {Shaoxian Tang and
Zhifeng Zhang and
Jun Wu and
Hui Zhu},
editor = {Qianbin Chen and
Weixiao Meng and
Liqiang Zhao},
title = {FPGA-Based Turbo Decoder Hardware Accelerator in Cloud Radio Access
Network {(C-RAN)}},
booktitle = {Communications and Networking - 11th {EAI} International Conference,
ChinaCom 2016, Chongqing, China, September 24-26, 2016, Proceedings,
Part {I}},
series = {Lecture Notes of the Institute for Computer Sciences, Social Informatics
and Telecommunications Engineering},
volume = {209},
pages = {211--220},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-66625-9\_21},
doi = {10.1007/978-3-319-66625-9\_21},
timestamp = {Mon, 01 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/chinacom/TangZ0Z16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/compsac/El-WafaSH16,
author = {Wael Abou El{-}Wafa and
Asmaa G. Seliem and
Hesham F. A. Hamed},
title = {Hardware Acceleration of Smith-Waterman Algorithm for Short Read {DNA}
Alignment Using {FPGA}},
booktitle = {40th {IEEE} Annual Computer Software and Applications Conference,
{COMPSAC} Workshops 2016, Atlanta, GA, USA, June 10-14, 2016},
pages = {604--605},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/COMPSAC.2016.127},
doi = {10.1109/COMPSAC.2016.127},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/compsac/El-WafaSH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/conielecomp/Lopez-RamirezLR16,
author = {Misael Lopez{-}Ramirez and
Luis Manuel Ledesma{-}Carrillo and
Carlos Rodriguez{-}Donate and
Eduardo Cabal{-}Yepez and
Homero Miranda{-}Vidales and
Arturo Garcia{-}Perez},
title = {FPGA-based hardware processing unit for time-frequency representation
of a signal through Wigner-Ville distribution},
booktitle = {2016 International Conference on Electronics, Communications and Computers,
{CONIELECOMP} 2016, Cholula, Mexico, February 24-26, 2016},
pages = {162--167},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/CONIELECOMP.2016.7438569},
doi = {10.1109/CONIELECOMP.2016.7438569},
timestamp = {Thu, 18 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/conielecomp/Lopez-RamirezLR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/KomorkiewiczTSK16,
author = {Mateusz Komorkiewicz and
Krzysztof Turek and
Pawel Skruch and
Tomasz Kryjak and
Marek Gorgon},
title = {FPGA-based Hardware-in-the-Loop environment using video injection
concept for camera-based systems in automotive applications},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {183--190},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853817},
doi = {10.1109/DASIP.2016.7853817},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/dasip/KomorkiewiczTSK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/Morales-Villanueva16,
author = {Aurelio Morales{-}Villanueva and
Rohit Kumar and
Ann Gordon{-}Ross},
editor = {Luca Fanucci and
J{\"{u}}rgen Teich},
title = {Configuration prefetching and reuse for preemptive hardware multitasking
on partially reconfigurable FPGAs},
booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
pages = {1505--1508},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/document/7459551/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/Morales-Villanueva16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/KitsosSV16,
author = {Paris Kitsos and
Kyriakos Stefanidis and
Artemios G. Voyiatzis},
editor = {Paris Kitsos},
title = {TERO-Based Detection of Hardware Trojans on {FPGA} Implementation
of the {AES} Algorithm},
booktitle = {2016 Euromicro Conference on Digital System Design, {DSD} 2016, Limassol,
Cyprus, August 31 - September 2, 2016},
pages = {678--681},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/DSD.2016.47},
doi = {10.1109/DSD.2016.47},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/KitsosSV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/Lara-NinoMD16,
author = {Carlos Andres Lara{-}Nino and
Miguel Morales{-}Sandoval and
Arturo Diaz{-}Perez},
editor = {Paris Kitsos},
title = {Novel FPGA-Based Low-Cost Hardware Architecture for the {PRESENT}
Block Cipher},
booktitle = {2016 Euromicro Conference on Digital System Design, {DSD} 2016, Limassol,
Cyprus, August 31 - September 2, 2016},
pages = {646--650},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/DSD.2016.46},
doi = {10.1109/DSD.2016.46},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/Lara-NinoMD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dtis/Salvador16,
author = {Rub{\'{e}}n Salvador},
title = {Evolvable Hardware in FPGAs: Embedded tutorial},
booktitle = {2016 International Conference on Design and Technology of Integrated
Systems in Nanoscale Era, {DTIS} 2016, Istanbul, Turkey, April 12-14,
2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DTIS.2016.7483877},
doi = {10.1109/DTIS.2016.7483877},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/dtis/Salvador16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LiNL16,
author = {Bingzhe Li and
M. Hassan Najafi and
David J. Lilja},
editor = {Deming Chen and
Jonathan W. Greene},
title = {Using Stochastic Computing to Reduce the Hardware Requirements for
a Restricted Boltzmann Machine Classifier},
booktitle = {Proceedings of the 2016 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 21-23, 2016},
pages = {36--41},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2847263.2847340},
doi = {10.1145/2847263.2847340},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LiNL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ZhangAC16,
author = {Sizhuo Zhang and
Hari Angepat and
Derek Chiou},
editor = {Deming Chen and
Jonathan W. Greene},
title = {HGum: Messaging Framework for Hardware Accelerators (Abstact Only)},
booktitle = {Proceedings of the 2016 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 21-23, 2016},
pages = {283},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2847263.2847289},
doi = {10.1145/2847263.2847289},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ZhangAC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/KalmsEJ16,
author = {Lester Kalms and
Ahmed Elhossini and
Ben H. H. Juurlink},
editor = {Yuchen Song and
Shaojun Wang and
Brent Nelson and
Junbao Li and
Yu Peng},
title = {{FPGA} based hardware accelerator for {KAZE} feature extraction algorithm},
booktitle = {2016 International Conference on Field-Programmable Technology, {FPT}
2016, Xi'an, China, December 7-9, 2016},
pages = {281--284},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/FPT.2016.7929553},
doi = {10.1109/FPT.2016.7929553},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/KalmsEJ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/VeerannaS16,
author = {Nandeesha Veeranna and
Benjamin Carri{\'{o}}n Sch{\"{a}}fer},
editor = {Yuchen Song and
Shaojun Wang and
Brent Nelson and
Junbao Li and
Yu Peng},
title = {Hardware Trojan avoidance and detection for dynamically re-configurable
FPGAs},
booktitle = {2016 International Conference on Field-Programmable Technology, {FPT}
2016, Xi'an, China, December 7-9, 2016},
pages = {193--196},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/FPT.2016.7929531},
doi = {10.1109/FPT.2016.7929531},
timestamp = {Tue, 16 Oct 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/VeerannaS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hotchips/GuoSQYHWY16,
author = {Kaiyuan Guo and
Lingzhi Sui and
Jiantao Qiu and
Song Yao and
Song Han and
Yu Wang and
Huazhong Yang},
title = {From model to {FPGA:} Software-hardware co-design for efficient neural
network acceleration},
booktitle = {2016 {IEEE} Hot Chips 28 Symposium (HCS), Cupertino, CA, USA, August
21-23, 2016},
pages = {1--27},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/HOTCHIPS.2016.7936208},
doi = {10.1109/HOTCHIPS.2016.7936208},
timestamp = {Fri, 20 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hotchips/GuoSQYHWY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/huc/AhmadLC16,
author = {Abdul Mutaal Ahmad and
Paul Lukowicz and
Jingyuan Cheng},
editor = {Paul Lukowicz and
Antonio Kr{\"{u}}ger and
Andreas Bulling and
Youn{-}Kyung Lim and
Shwetak N. Patel},
title = {{FPGA} based hardware acceleration of sensor matrix},
booktitle = {Proceedings of the 2016 {ACM} International Joint Conference on Pervasive
and Ubiquitous Computing and Proceedings of the 2016 {ACM} International
Symposium on Wearable Computers, UbiComp/ISWC Adjunct 2016, Heidelberg,
Germany, September 12-16, 2016},
pages = {793--802},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2968219.2968289},
doi = {10.1145/2968219.2968289},
timestamp = {Tue, 26 Mar 2024 12:15:04 +0100},
biburl = {https://dblp.org/rec/conf/huc/AhmadLC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/HaradaMNI16,
author = {Naoaki Harada and
Naoyuki Matsumoto and
Koji Nakano and
Yasuaki Ito},
title = {A Hardware Sorter for Almost Sorted Sequences, with {FPGA} Implementations},
booktitle = {Fourth International Symposium on Computing and Networking, {CANDAR}
2016, Hiroshima, Japan, November 22-25, 2016},
pages = {565--571},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/CANDAR.2016.0103},
doi = {10.1109/CANDAR.2016.0103},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/HaradaMNI16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icacci/ChhabraJS16,
author = {Surbhi Chhabra and
Himanshu Jain and
Sandeep Saini},
title = {{FPGA} based hardware implementation of automatic vehicle license
plate detection system},
booktitle = {2016 International Conference on Advances in Computing, Communications
and Informatics, {ICACCI} 2016, Jaipur, India, September 21-24, 2016},
pages = {1181--1187},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ICACCI.2016.7732205},
doi = {10.1109/ICACCI.2016.7732205},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icacci/ChhabraJS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icaisc/PrzybylE16,
author = {Andrzej Przybyl and
Meng Joo Er},
editor = {Leszek Rutkowski and
Marcin Korytkowski and
Rafal Scherer and
Ryszard Tadeusiewicz and
Lotfi A. Zadeh and
Jacek M. Zurada},
title = {The Method of Hardware Implementation of Fuzzy Systems on {FPGA}},
booktitle = {Artificial Intelligence and Soft Computing - 15th International Conference,
{ICAISC} 2016, Zakopane, Poland, June 12-16, 2016, Proceedings, Part
{I}},
series = {Lecture Notes in Computer Science},
volume = {9692},
pages = {284--298},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-39378-0\_25},
doi = {10.1007/978-3-319-39378-0\_25},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icaisc/PrzybylE16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/MomeniTSK16,
author = {Amir Momeni and
Hamed Tabkhi and
Gunar Schirner and
David R. Kaeli},
title = {Hardware thread reordering to boost OpenCL throughput on FPGAs},
booktitle = {34th {IEEE} International Conference on Computer Design, {ICCD} 2016,
Scottsdale, AZ, USA, October 2-5, 2016},
pages = {257--264},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ICCD.2016.7753288},
doi = {10.1109/ICCD.2016.7753288},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/MomeniTSK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccp2/VanceaN16,
author = {Cristian{-}Cosmin Vancea and
Sergiu Nedevschi},
title = {FPGA-based stereo vision hardware for generating dense disparity maps},
booktitle = {{IEEE} 12th International Conference on Intelligent Computer Communication
and Processing, {ICCP} 2016, Cluj-Napoca, Romania, September 8-10,
2016},
pages = {225--232},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ICCP.2016.7737151},
doi = {10.1109/ICCP.2016.7737151},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccp2/VanceaN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icdsc/BrenotPF16,
author = {Fran{\c{c}}ois Brenot and
Jonathan Piat and
Philippe Fillatreau},
title = {{FPGA} based hardware acceleration of a {BRIEF} correlator module
for a monocular {SLAM} application},
booktitle = {Proceedings of the 10th International Conference on Distributed Smart
Camera, Paris, France, September 12-15, 2016},
pages = {184--189},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2967413.2967426},
doi = {10.1145/2967413.2967426},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icdsc/BrenotPF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icm2/GamalEF16,
author = {Mohammed Gamal and
Mohamed El{-}Banna and
Mohammed M. Farag},
title = {Hardware implementation of an {LQR} controller of a drum-type boiler
turbine on {FPGA}},
booktitle = {28th International Conference on Microelectronics, {ICM} 2016, Giza,
Egypt, December 17-20, 2016},
pages = {137--140},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ICM.2016.7847928},
doi = {10.1109/ICM.2016.7847928},
timestamp = {Mon, 09 Aug 2021 14:54:02 +0200},
biburl = {https://dblp.org/rec/conf/icm2/GamalEF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icuimc/JoLJ16,
author = {Byeong{-}Oh Jo and
Sang{-}Jun Lee and
Jae Wook Jeon},
title = {The Development of Hardware Architecture for Real-time Chain Code
based on {FPGA}},
booktitle = {Proceedings of the 10th International Conference on Ubiquitous Information
Management and Communication, {IMCOM} 2016, Danang, Vietnam, January
4-6, 2016},
pages = {24:1--24:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2857546.2857571},
doi = {10.1145/2857546.2857571},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icuimc/JoLJ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/idt/FarhatFSB16,
author = {Wajdi Farhat and
Hassene Faiedh and
Chokri Souani and
Kamel Besbes},
title = {Real-time hardware/software co-design of a traffic sign recognition
system using Zynq {FPGA}},
booktitle = {11th International Design {\&} Test Symposium, {IDT} 2016, Hammamet,
Tunisia, December 18-20, 2016},
pages = {302--307},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/IDT.2016.7843059},
doi = {10.1109/IDT.2016.7843059},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/idt/FarhatFSB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/indocrypt/KozielAK16,
author = {Brian Koziel and
Reza Azarderakhsh and
Mehran Mozaffari Kermani},
editor = {Orr Dunkelman and
Somitra Kumar Sanadhya},
title = {Fast Hardware Architectures for Supersingular Isogeny Diffie-Hellman
Key Exchange on {FPGA}},
booktitle = {Progress in Cryptology - {INDOCRYPT} 2016 - 17th International Conference
on Cryptology in India, Kolkata, India, December 11-14, 2016, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10095},
pages = {191--206},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-49890-4\_11},
doi = {10.1007/978-3-319-49890-4\_11},
timestamp = {Tue, 14 May 2019 10:00:51 +0200},
biburl = {https://dblp.org/rec/conf/indocrypt/KozielAK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipas2/AkkadEA16,
author = {Ghattas Akkad and
Moustapha El Hassan and
Rafic Ayoubi},
title = {{FPGA} hardware architecture for stereoscopic image compression based
on block matching, watermarking and hamming code},
booktitle = {International Image Processing, Applications and Systems, {IPAS} 2016,
Hammamet, Tunisia, November 5-7, 2016},
pages = {1--5},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/IPAS.2016.7880065},
doi = {10.1109/IPAS.2016.7880065},
timestamp = {Tue, 05 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ipas2/AkkadEA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/KourfaliS16,
author = {Alexandra Kourfali and
Dirk Stroobandt},
title = {Efficient Hardware Debugging Using Parameterized {FPGA} Reconfiguration},
booktitle = {2016 {IEEE} International Parallel and Distributed Processing Symposium
Workshops, {IPDPS} Workshops 2016, Chicago, IL, USA, May 23-27, 2016},
pages = {277--282},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/IPDPSW.2016.95},
doi = {10.1109/IPDPSW.2016.95},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/KourfaliS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isicir/LomuscioCNR16,
author = {Andrea Lomuscio and
Gian Carlo Cardarilli and
Alberto Nannarelli and
Marco Re},
title = {A hardware framework for on-chip {FPGA} acceleration},
booktitle = {International Symposium on Integrated Circuits, {ISIC} 2016, Singapore,
December 12-14, 2016},
pages = {1--4},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISICIR.2016.7829683},
doi = {10.1109/ISICIR.2016.7829683},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/isicir/LomuscioCNR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isie/MorelloBTCRRJLI16,
author = {Rocco Morello and
Federico Baronti and
X. Tian and
Thomas Chau and
Roberto Di Rienzo and
Roberto Roncella and
B. P. Jeppesen and
W. H. Lin and
T. Ikushima and
Roberto Saletti},
title = {Hardware-in-the-loop simulation of FPGA-based state estimators for
electric vehicle batteries},
booktitle = {25th {IEEE} International Symposium on Industrial Electronics, {ISIE}
2016, Santa Clara, CA, USA, June 8-10, 2016},
pages = {280--285},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISIE.2016.7744903},
doi = {10.1109/ISIE.2016.7744903},
timestamp = {Sun, 11 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isie/MorelloBTCRRJLI16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/YousufG16,
author = {Shaon Yousuf and
Ann Gordon{-}Ross},
title = {An Automated Hardware/Software Co-Design Flow for Partially Reconfigurable
FPGAs},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2016, Pittsburgh,
PA, USA, July 11-13, 2016},
pages = {30--35},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ISVLSI.2016.73},
doi = {10.1109/ISVLSI.2016.73},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/YousufG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mixdes/PetrutAB16,
author = {Patricia Carla Petrut and
Alexandru Amaricai and
Oana Boncalo},
title = {Configurable {FPGA} architecture for hardware-software merge sorting},
booktitle = {2016 {MIXDES} - 23rd International Conference Mixed Design of Integrated
Circuits and Systems, Lodz, Poland, June 23-25, 2016},
pages = {179--182},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/MIXDES.2016.7529727},
doi = {10.1109/MIXDES.2016.7529727},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/mixdes/PetrutAB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rcar/PengLLLZF16,
author = {Jianqing Peng and
Yunhui Liu and
Congyi Lyu and
Yunhui Li and
Weiguo Zhou and
Kun Fan},
title = {FPGA-based parallel hardware architecture for {SIFT} algorithm},
booktitle = {{IEEE} International Conference on Real-time Computing and Robotics,
{RCAR} 2016, Angkor Wat, Cambodia, June 6-10, 2016},
pages = {277--282},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/RCAR.2016.7784039},
doi = {10.1109/RCAR.2016.7784039},
timestamp = {Fri, 23 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rcar/PengLLLZF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sas2/EiderKP16,
author = {Markus Eider and
Stefan Kunze and
Rainer Poeschl},
title = {{FPGA} based emulation of multiple 1-wire sensors for hardware in
the loop tests},
booktitle = {{IEEE} Sensors Applications Symposium, {SAS} 2016, Catania, Italy,
April 20-22, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/SAS.2016.7479859},
doi = {10.1109/SAS.2016.7479859},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/sas2/EiderKP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbac-pad/KimJG16,
author = {Youngsoo Kim and
Shrikant Jadhav and
Clay S. Gloster Jr.},
title = {Dataflow to Hardware Synthesis Framework on FPGAs},
booktitle = {2016 International Symposium on Computer Architecture and High Performance
Computing Workshops, {SBAC-PAD} Workshops 2016, Los Angeles, CA, USA,
October 26-28, 2016},
pages = {91--96},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/SBAC-PADW.2016.24},
doi = {10.1109/SBAC-PADW.2016.24},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbac-pad/KimJG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sies/HarbVPG16,
author = {Naim Harb and
Carlos Valderrama and
Esteban Pelaez and
Alexandre Girardi},
title = {{FPGA} hardware in the loop system for {ERTMS-ETCS} train equipment
testing},
booktitle = {11th {IEEE} Symposium on Industrial Embedded Systems, {SIES} 2016,
Krakow, Poland, May 23-25, 2016},
pages = {55--62},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/SIES.2016.7509412},
doi = {10.1109/SIES.2016.7509412},
timestamp = {Sun, 03 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sies/HarbVPG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ssci/JohnsonHMTTLHMK16,
author = {Anju P. Johnson and
David M. Halliday and
Alan G. Millard and
Andy M. Tyrrell and
Jon Timmis and
Junxiu Liu and
Jim Harkin and
Liam McDaid and
Shvan Karim},
title = {An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network},
booktitle = {2016 {IEEE} Symposium Series on Computational Intelligence, {SSCI}
2016, Athens, Greece, December 6-9, 2016},
pages = {1--8},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/SSCI.2016.7850175},
doi = {10.1109/SSCI.2016.7850175},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ssci/JohnsonHMTTLHMK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/trustcom/LiCLSCL16,
author = {Xiaochao Li and
Chunhui Cao and
Pengtao Li and
Shuli Shen and
Yihui Chen and
Lin Li},
title = {Energy-Efficient Hardware Implementation of {LUKS} {PBKDF2} with {AES}
on {FPGA}},
booktitle = {2016 {IEEE} Trustcom/BigDataSE/ISPA, Tianjin, China, August 23-26,
2016},
pages = {402--409},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/TrustCom.2016.0090},
doi = {10.1109/TRUSTCOM.2016.0090},
timestamp = {Thu, 31 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/trustcom/LiCLSCL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LiHC16a,
author = {Yanzhe Li and
Kai Huang and
Luc Claesen},
editor = {Thomas Hollstein and
Jaan Raik and
Sergei Kostin and
Anton Tsertov and
Ian O'Connor and
Ricardo Reis},
title = {A Novel Hardware-Oriented Stereo Matching Algorithm and Its Architecture
Design in {FPGA}},
booktitle = {VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification
and Reliability - 24th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia,
September 26-28, 2016, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {508},
pages = {213--232},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-67104-8\_11},
doi = {10.1007/978-3-319-67104-8\_11},
timestamp = {Wed, 01 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LiHC16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/CotretGF16,
author = {Pascal Cotret and
Guy Gogniat and
Martha Johanna Sep{\'{u}}lveda Fl{\'{o}}rez},
title = {Protection of heterogeneous architectures on FPGAs: An approach based
on hardware firewalls},
journal = {CoRR},
volume = {abs/1602.05106},
year = {2016},
url = {http://arxiv.org/abs/1602.05106},
eprinttype = {arXiv},
eprint = {1602.05106},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/CotretGF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/Ortega-Zamorano16,
author = {Francisco Ortega{-}Zamorano and
Marcelo A. Montemurro and
Sergio A. Cannas and
Jos{\'{e}} M. Jerez and
Leonardo Franco},
title = {{FPGA} Hardware Acceleration of Monte Carlo Simulations for the Ising
Model},
journal = {CoRR},
volume = {abs/1602.03016},
year = {2016},
url = {http://arxiv.org/abs/1602.03016},
eprinttype = {arXiv},
eprint = {1602.03016},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/Ortega-Zamorano16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iacr/JarvinenMAL16,
author = {Kimmo J{\"{a}}rvinen and
Andrea Miele and
Reza Azarderakhsh and
Patrick Longa},
title = {FourQ on {FPGA:} New Hardware Speed Records for Elliptic Curve Cryptography
over Large Prime Characteristic Fields},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {569},
year = {2016},
url = {http://eprint.iacr.org/2016/569},
timestamp = {Mon, 11 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iacr/JarvinenMAL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iacr/KozielAK16,
author = {Brian Koziel and
Reza Azarderakhsh and
Mehran Mozaffari Kermani},
title = {Fast Hardware Architectures for Supersingular Isogeny Diffie-Hellman
Key Exchange on {FPGA}},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {1044},
year = {2016},
url = {http://eprint.iacr.org/2016/1044},
timestamp = {Mon, 11 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iacr/KozielAK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/hal/Huriaux15,
author = {Christophe Huriaux},
title = {Enhanced {FPGA} Architecture and {CAD} Flow for Efficient Runtime
Hardware Reconfiguration. (Architecture {FPGA} ame'liore'e et flot
de conception pour une reconfiguration mate'rielle en ligne efficace)},
school = {University of Rennes 1, France},
year = {2015},
url = {https://tel.archives-ouvertes.fr/tel-01253498},
timestamp = {Tue, 21 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/hal/Huriaux15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/ndltd/Oliveira15e,
author = {Cristiano Bacelar de Oliveira},
title = {{LALP+:} a framework for developing FPGA-based hardware accelerators
{(LALP+:} um framework para o desenvolvimento de aceleradores de hardware
em FPGAs)},
school = {University of S{\~{a}}o Paulo, Brazil},
year = {2015},
url = {http://www.teses.usp.br/teses/disponiveis/55/55134/tde-30082016-160232/},
timestamp = {Sun, 15 Jul 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/ndltd/Oliveira15e.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/KhaleghiAAS15,
author = {Behnam Khaleghi and
Ali Ahari and
Hossein Asadi and
Siavash Bayat Sarmadi},
title = {FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion
Using Dummy Logic},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {7},
number = {2},
pages = {46--50},
year = {2015},
url = {https://doi.org/10.1109/LES.2015.2406791},
doi = {10.1109/LES.2015.2406791},
timestamp = {Fri, 14 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/KhaleghiAAS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceee/GuoDLW15,
author = {Song Guo and
Yong Dou and
Yuanwu Lei and
Guiming Wu},
title = {A deeply-pipelined FPGA-based SpMV accelerator with a hardware-friendly
storage scheme},
journal = {{IEICE} Electron. Express},
volume = {12},
number = {11},
pages = {20150161},
year = {2015},
url = {https://doi.org/10.1587/elex.12.20150161},
doi = {10.1587/ELEX.12.20150161},
timestamp = {Tue, 14 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieiceee/GuoDLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/YazawaYTDYYF15,
author = {Yoshifumi Yazawa and
Tsutomu Yoshimi and
Teruyasu Tsuzuki and
Tomomi Dohi and
Yuji Yamauchi and
Takayoshi Yamashita and
Hironobu Fujiyoshi},
title = {{FPGA} Hardware with Target-Reconfigurable Object Detector},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {98-D},
number = {9},
pages = {1637--1645},
year = {2015},
url = {https://doi.org/10.1587/transinf.2014OPP0008},
doi = {10.1587/TRANSINF.2014OPP0008},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/YazawaYTDYYF15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijcat/HamdaouiSM15,
author = {Fay{\c{c}}al Hamdaoui and
Anis Sakly and
Abdellatif Mtibaa},
title = {{FPGA} hardware architecture of correlation-based {MRI} images classification
using {XSG}},
journal = {Int. J. Comput. Appl. Technol.},
volume = {52},
number = {1},
pages = {77--85},
year = {2015},
url = {https://doi.org/10.1504/IJCAT.2015.071422},
doi = {10.1504/IJCAT.2015.071422},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijcat/HamdaouiSM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijguc/Zhu15,
author = {Shi{-}hai Zhu},
title = {Hardware implementation based on {FPGA} of semaphore management in
{\(\mu\)}C/OS-II real-time operating system},
journal = {Int. J. Grid Util. Comput.},
volume = {6},
number = {3/4},
pages = {192--199},
year = {2015},
url = {https://doi.org/10.1504/IJGUC.2015.070677},
doi = {10.1504/IJGUC.2015.070677},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijguc/Zhu15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijon/TanR15,
author = {Yong Tat Tan and
Bakhtiar Affendi Rosdi},
title = {FPGA-based hardware accelerator for the prediction of protein secondary
class via fuzzy K-nearest neighbors with Lempel-Ziv complexity based
distance measure},
journal = {Neurocomputing},
volume = {148},
pages = {409--419},
year = {2015},
url = {https://doi.org/10.1016/j.neucom.2014.06.001},
doi = {10.1016/J.NEUCOM.2014.06.001},
timestamp = {Tue, 06 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijon/TanR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijpp/SukhwaniTMDBAD15,
author = {Bharat Sukhwani and
Mathew Thoennes and
Hong Min and
Parijat Dube and
Bernard Brezzo and
Sameh W. Asaad and
Donna Dillenberger},
title = {A Hardware/Software Approach for Database Query Acceleration with
FPGAs},
journal = {Int. J. Parallel Program.},
volume = {43},
number = {6},
pages = {1129--1159},
year = {2015},
url = {https://doi.org/10.1007/s10766-014-0327-4},
doi = {10.1007/S10766-014-0327-4},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijpp/SukhwaniTMDBAD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jce/VliegenMKSV15,
author = {Jo Vliegen and
Nele Mentens and
Dirk Koch and
Dries Schellekens and
Ingrid Verbauwhede},
title = {Practical feasibility evaluation and improvement of a pay-per-use
licensing scheme for hardware {IP} cores in Xilinx FPGAs},
journal = {J. Cryptogr. Eng.},
volume = {5},
number = {2},
pages = {113--122},
year = {2015},
url = {https://doi.org/10.1007/s13389-014-0088-4},
doi = {10.1007/S13389-014-0088-4},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jce/VliegenMKSV15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsci/JuniorOJ15,
author = {S{\'{e}}rgio Bimbi Junior and
Vitor Chaves de Oliveira and
Gunnar Bedicks Junior},
title = {Software Defined Radio Implementation of a {QPSK} Modulator/Demodulator
in an Extensive Hardware Platform Based on FPGAs Xilinx {ZYNQ}},
journal = {J. Comput. Sci.},
volume = {11},
number = {4},
pages = {598--611},
year = {2015},
url = {https://doi.org/10.3844/jcssp.2015.598.611},
doi = {10.3844/JCSSP.2015.598.611},
timestamp = {Sat, 25 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsci/JuniorOJ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jicce/ChooCM15,
author = {Chang Choo and
Young{-}Uk Chang and
Il{-}Young Moon},
title = {FPGA-Based Hardware Accelerator for Feature Extraction in Automatic
Speech Recognition},
journal = {J. Inform. and Commun. Convergence Engineering},
volume = {13},
number = {3},
year = {2015},
url = {https://doi.org/10.6109/jicce.2015.13.3.145},
doi = {10.6109/JICCE.2015.13.3.145},
timestamp = {Tue, 16 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jicce/ChooCM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrtip/Rodriguez-Gomez15,
author = {Rafael Rodr{\'{\i}}guez{-}G{\'{o}}mez and
Enrique J. Fernandez{-}Sanchez and
Javier D{\'{\i}}az and
Eduardo Ros Vidal},
title = {Codebook hardware implementation on {FPGA} for background subtraction},
journal = {J. Real Time Image Process.},
volume = {10},
number = {1},
pages = {43--57},
year = {2015},
url = {https://doi.org/10.1007/s11554-012-0249-6},
doi = {10.1007/S11554-012-0249-6},
timestamp = {Thu, 18 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrtip/Rodriguez-Gomez15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/AysuS15,
author = {Aydin Aysu and
Patrick Schaumont},
title = {Hardware/software co-design of physical unclonable function based
authentications on FPGAs},
journal = {Microprocess. Microsystems},
volume = {39},
number = {7},
pages = {589--597},
year = {2015},
url = {https://doi.org/10.1016/j.micpro.2015.04.001},
doi = {10.1016/J.MICPRO.2015.04.001},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/AysuS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/DammakBBNA15,
author = {Bouthaina Dammak and
Mouna Baklouti and
Rachid Benmansour and
Sma{\"{\i}}l Niar and
Mohamed Abid},
title = {Hardware resource utilization optimization in FPGA-based Heterogeneous
MPSoC architectures},
journal = {Microprocess. Microsystems},
volume = {39},
number = {8},
pages = {1108--1118},
year = {2015},
url = {https://doi.org/10.1016/j.micpro.2015.05.006},
doi = {10.1016/J.MICPRO.2015.05.006},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/DammakBBNA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/TangB15,
author = {Yi Tang and
Neil W. Bergmann},
title = {A Hardware Scheduler Based on Task Queues for FPGA-Based Embedded
Real-Time Systems},
journal = {{IEEE} Trans. Computers},
volume = {64},
number = {5},
pages = {1254--1267},
year = {2015},
url = {https://doi.org/10.1109/TC.2014.2315637},
doi = {10.1109/TC.2014.2315637},
timestamp = {Thu, 08 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/TangB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcbb/FernandezVLN15,
author = {Edward B. Fernandez and
Jason R. Villarreal and
Stefano Lonardi and
Walid A. Najjar},
title = {{FHAST:} FPGA-Based Acceleration of Bowtie in Hardware},
journal = {{IEEE} {ACM} Trans. Comput. Biol. Bioinform.},
volume = {12},
number = {5},
pages = {973--981},
year = {2015},
url = {https://doi.org/10.1109/TCBB.2015.2405333},
doi = {10.1109/TCBB.2015.2405333},
timestamp = {Mon, 03 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcbb/FernandezVLN15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tci/QasaimehSS15,
author = {Murad Qasaimeh and
Assim Sagahyroon and
Tamer Shanableh},
title = {FPGA-Based Parallel Hardware Architecture for Real-Time Image Classification},
journal = {{IEEE} Trans. Computational Imaging},
volume = {1},
number = {1},
pages = {56--70},
year = {2015},
url = {https://doi.org/10.1109/TCI.2015.2424077},
doi = {10.1109/TCI.2015.2424077},
timestamp = {Thu, 18 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tci/QasaimehSS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tie/JimenezLUBND15,
author = {{\'{O}}scar Jim{\'{e}}nez and
Oscar Luc{\'{\i}}a and
Isidoro Urriza and
Luis Angel Barragan and
Denis Navarro and
Venkata Dinavahi},
title = {Implementation of an FPGA-Based Online Hardware-in-the-Loop Emulator
Using High-Level Synthesis Tools for Resonant Power Converters Applied
to Induction Heating Appliances},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {62},
number = {4},
pages = {2206--2214},
year = {2015},
url = {https://doi.org/10.1109/TIE.2014.2360138},
doi = {10.1109/TIE.2014.2360138},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tie/JimenezLUBND15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/0001DIM15,
author = {Michael R. Smith and
Dongcheng Deng and
Syed Islam and
James Miller},
title = {Enhancing Hardware Assisted Test Insertion Capabilities on Embedded
Processors using an FPGA-based Agile Test Support Co-processor},
journal = {J. Signal Process. Syst.},
volume = {79},
number = {3},
pages = {285--298},
year = {2015},
url = {https://doi.org/10.1007/s11265-013-0845-0},
doi = {10.1007/S11265-013-0845-0},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/0001DIM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEssd/AnaneA15a,
author = {Mohamed Anane and
Nadjia Anane},
title = {{SHA-2} hardware core for virtex-5 {FPGA}},
booktitle = {12th {IEEE} International Multi-Conference on Systems, Signals {\&}
Devices, {SSD} 2015, Mahdia, Tunisia, March 16-19, 2015},
pages = {1--5},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/SSD.2015.7348110},
doi = {10.1109/SSD.2015.7348110},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/IEEEssd/AnaneA15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEssd/KahriMBM15,
author = {Fatma Kahri and
Hassen Mestiri and
Belgacem Bouallegue and
Mohsen Machhout},
title = {Efficient {FPGA} hardware implementation of secure hash function SHA-256/Blake-256},
booktitle = {12th {IEEE} International Multi-Conference on Systems, Signals {\&}
Devices, {SSD} 2015, Mahdia, Tunisia, March 16-19, 2015},
pages = {1--5},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/SSD.2015.7348105},
doi = {10.1109/SSD.2015.7348105},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/IEEEssd/KahriMBM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/acsac/LiDP15,
author = {Letitia W. Li and
Guillaume Duc and
Renaud Pacalet},
title = {Hardware-assisted Memory Tracing on New SoCs Embedding {FPGA} Fabrics},
booktitle = {Proceedings of the 31st Annual Computer Security Applications Conference,
Los Angeles, CA, USA, December 7-11, 2015},
pages = {461--470},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2818000.2818030},
doi = {10.1145/2818000.2818030},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/acsac/LiDP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/CharitopoulosKP15,
author = {George Charitopoulos and
Iosif Koidis and
Kyprianos Papadimitriou and
Dionisios N. Pnevmatikatos},
editor = {Kentaro Sano and
Dimitrios Soudris and
Michael H{\"{u}}bner and
Pedro C. Diniz},
title = {Hardware Task Scheduling for Partially Reconfigurable FPGAs},
booktitle = {Applied Reconfigurable Computing - 11th International Symposium, {ARC}
2015, Bochum, Germany, April 13-17, 2015, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {9040},
pages = {487--498},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-16214-0\_45},
doi = {10.1007/978-3-319-16214-0\_45},
timestamp = {Wed, 28 Apr 2021 16:06:56 +0200},
biburl = {https://dblp.org/rec/conf/arc/CharitopoulosKP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/ZhangCW15,
author = {Yangjie Zhang and
Wei Cao and
Lingli Wang},
title = {Implementation of high performance hardware architecture of face recognition
algorithm based on local binary pattern on {FPGA}},
booktitle = {2015 {IEEE} 11th International Conference on ASIC, {ASICON} 2015,
Chengdu, China, November 3-6, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASICON.2015.7516877},
doi = {10.1109/ASICON.2015.7516877},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/asicon/ZhangCW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cis/QuWZ15,
author = {Kaige Qu and
Liji Wu and
Xiangmin Zhang},
title = {A Novel Detection Algorithm for Ring Oscillator Network Based Hardware
Trojan Detection with Tactful {FPGA} Implementation},
booktitle = {11th International Conference on Computational Intelligence and Security,
{CIS} 2015, Shenzhen, China, December 19-20, 2015},
pages = {299--302},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/CIS.2015.80},
doi = {10.1109/CIS.2015.80},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cis/QuWZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cisis-spain/EpeldeMLM15,
author = {Gorka Epelde and
Andoni Mujika and
Peter Leskovsk{\'{y}} and
Alessandro De Mauro},
editor = {{\'{A}}lvaro Herrero and
Bruno Baruque and
Javier Sedano and
H{\'{e}}ctor Quinti{\'{a}}n and
Emilio Corchado},
title = {Public Access Architecture Design of an FPGA-Hardware-Based Nervous
System Emulation Remote Lab},
booktitle = {International Joint Conference - CISIS'15 and ICEUTE'15, 8th International
Conference on Computational Intelligence in Security for Information
Systems / 6th International Conference on EUropean Transnational Education,
Burgos, Spain, 15-17 June, 2015},
series = {Advances in Intelligent Systems and Computing},
volume = {369},
pages = {559--569},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-19713-5\_49},
doi = {10.1007/978-3-319-19713-5\_49},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cisis-spain/EpeldeMLM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KainthKNVT15,
author = {Meha Kainth and
Lekshmi Krishnan and
Chaitra Narayana and
Sandesh Gubbi Virupaksha and
Russell Tessier},
editor = {Wolfgang Nebel and
David Atienza},
title = {Hardware-assisted code obfuscation for {FPGA} soft microprocessors},
booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe
Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March
9-13, 2015},
pages = {127--132},
publisher = {{ACM}},
year = {2015},
url = {http://dl.acm.org/citation.cfm?id=2755781},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/KainthKNVT15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/etfa/GrimmJNH15,
author = {Tom{\'{a}}s Grimm and
Benedikt Jan{\ss}en and
Osvaldo Navarro and
Michael H{\"{u}}bner},
title = {The value of FPGAs as reconfigurable hardware enabling Cyber-Physical
Systems},
booktitle = {20th {IEEE} Conference on Emerging Technologies {\&} Factory Automation,
{ETFA} 2015, Luxembourg, September 8-11, 2015},
pages = {1--8},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ETFA.2015.7301496},
doi = {10.1109/ETFA.2015.7301496},
timestamp = {Wed, 28 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/etfa/GrimmJNH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/SalamiAS15,
author = {Behzad Salami and
Oriol Arcas{-}Abella and
Nehir S{\"{o}}nmez},
title = {{HATCH:} Hash Table Caching in Hardware for Efficient Relational Join
on {FPGA}},
booktitle = {23rd {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2015, Vancouver, BC, Canada, May 2-6, 2015},
pages = {163},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/FCCM.2015.28},
doi = {10.1109/FCCM.2015.28},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/SalamiAS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/BymaTXBLC15,
author = {Stuart Byma and
Naif Tarafdar and
Talia Xu and
Hadi Bannazadeh and
Alberto Leon{-}Garcia and
Paul Chow},
editor = {George A. Constantinides and
Deming Chen},
title = {Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware},
booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
pages = {94--97},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2684746.2689086},
doi = {10.1145/2684746.2689086},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/BymaTXBLC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChackoSPKD15,
author = {James Chacko and
Cem Sahin and
Douglas Pfiel and
Nagarajan Kandasamy and
Kapil R. Dandekar},
editor = {George A. Constantinides and
Deming Chen},
title = {Rapid Prototyping of Wireless Physical Layer Modules Using Flexible
Software/Hardware Design Flow},
booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
pages = {32--35},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2684746.2689084},
doi = {10.1145/2684746.2689084},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ChackoSPKD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/FlemingTCG15,
author = {Shane T. Fleming and
David B. Thomas and
George A. Constantinides and
Dan R. Ghica},
editor = {George A. Constantinides and
Deming Chen},
title = {System-level Linking of Synthesised Hardware and Compiled Software
Using a Higher-order Type System},
booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
pages = {214--217},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2684746.2689089},
doi = {10.1145/2684746.2689089},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/FlemingTCG15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GarciaCORB15,
author = {Gerardo Soria Garc{\'{\i}}a and
Adrian Pedroza de{-}la{-}Cr{\'{u}}z and
Susana Ortega{-}Cisneros and
Juan Jos{\'{e}} Raygoza{-}Panduro and
Eduardo Bayro{-}Corrochano},
editor = {George A. Constantinides and
Deming Chen},
title = {A Hardware Implementation of a Unit for Geometric Algebra Operations
With Parallel Memory Arrays (Abstract Only)},
booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
pages = {272},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2684746.2689132},
doi = {10.1145/2684746.2689132},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/GarciaCORB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JaicS15,
author = {Keerthan Jaic and
Melissa C. Smith},
editor = {George A. Constantinides and
Deming Chen},
title = {Enhancing Hardware Design Flows with MyHDL},
booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
pages = {28--31},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2684746.2689092},
doi = {10.1145/2684746.2689092},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/JaicS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KingHA15,
author = {Myron King and
Jamey Hicks and
John Ankcorn},
editor = {George A. Constantinides and
Deming Chen},
title = {Software-Driven Hardware Development},
booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
pages = {13--22},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2684746.2689064},
doi = {10.1145/2684746.2689064},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KingHA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/PapadopoulosTKT15,
author = {Martinianos Papadopoulos and
Christos Ttofis and
Christos Kyrkou and
Theocharis Theocharides},
editor = {George A. Constantinides and
Deming Chen},
title = {Real-Time Obstacle Avoidance for Mobile Robots via Stereoscopic Vision
Using Reconfigurable Hardware (Abstract Only)},
booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
pages = {262},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2684746.2689099},
doi = {10.1145/2684746.2689099},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/PapadopoulosTKT15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/TakasuTAK15,
author = {Ryota Takasu and
Yoichi Tomioka and
Takashi Aoki and
Hitoshi Kitazawa},
editor = {George A. Constantinides and
Deming Chen},
title = {An {FPGA} Implementation of Multi-stream Tracking Hardware using 2D
{SIMD} Array (Abstract Only)},
booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
pages = {268},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2684746.2689119},
doi = {10.1145/2684746.2689119},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/TakasuTAK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpgaworld/MalazgirtSYCU15,
author = {Gorker Alp Malazgirt and
Nehir S{\"{o}}nmez and
Arda Yurdakul and
Adri{\'{a}}n Cristal and
Osman S. Unsal},
editor = {Lennart Lindh and
Vincent J. Mooney III and
Ketil R{\o}ed and
David K{\"{a}}llberg and
Santiago de Pablo and
Mohamed Shalan and
Johnny {\"{O}}berg and
Peeter Ellervee},
title = {High Level Synthesis Based Hardware Accelerator Design for Processing
{SQL} Queries},
booktitle = {Proceedings of the 12th FPGAworld Conference 2015, FPGAworld '15,
Stockholm, Sweden, September 8-10, 2015},
pages = {27--32},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2889287.2889299},
doi = {10.1145/2889287.2889299},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpgaworld/MalazgirtSYCU15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/LiangSWZ15,
author = {Hao Liang and
Sharad Sinha and
Rakesh Warrier and
Wei Zhang},
title = {Static hardware task placement on multi-context {FPGA} using hybrid
genetic algorithm},
booktitle = {25th International Conference on Field Programmable Logic and Applications,
{FPL} 2015, London, United Kingdom, September 2-4, 2015},
pages = {1--8},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/FPL.2015.7293954},
doi = {10.1109/FPL.2015.7293954},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/LiangSWZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/ChoiBA15,
author = {Jongsok Choi and
Stephen Dean Brown and
Jason Helge Anderson},
title = {Resource and memory management techniques for the high-level synthesis
of software threads into parallel {FPGA} hardware},
booktitle = {2015 International Conference on Field Programmable Technology, {FPT}
2015, Queenstown, New Zealand, December 7-9, 2015},
pages = {152--159},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/FPT.2015.7393142},
doi = {10.1109/FPT.2015.7393142},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/ChoiBA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/host/BloomNSNL15,
author = {Gedare Bloom and
Bhagirath Narahari and
Rahul Simha and
Ali Namazi and
Renato Levy},
title = {{FPGA} SoC architecture and runtime to prevent hardware Trojans from
leaking secrets},
booktitle = {{IEEE} International Symposium on Hardware Oriented Security and Trust,
{HOST} 2015, Washington, DC, USA, 5-7 May, 2015},
pages = {48--51},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/HST.2015.7140235},
doi = {10.1109/HST.2015.7140235},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/host/BloomNSNL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icce-tw/MuzammilASK15,
author = {Muhammad Muzammil and
I. Ali and
M. Sharif and
K. A. Khalil},
title = {An efficient {FPGA} architecture for hardware realization of hexagonal
based motion estimation algorithm},
booktitle = {{IEEE} International Conference on Consumer Electronics - Taiwan,
{ICCE-TW} 2015, Taipei, Taiwan, June 6-8, 2015},
pages = {422--423},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICCE-TW.2015.7216977},
doi = {10.1109/ICCE-TW.2015.7216977},
timestamp = {Fri, 14 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icce-tw/MuzammilASK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccsce/AyatHB15,
author = {Sayed Omid Ayat and
Mohamed Khalil Hani and
Rabia Bakhteri},
title = {OpenCL-based hardware-software co-design methodology for image processing
implementation on heterogeneous {FPGA} platform},
booktitle = {2015 {IEEE} International Conference on Control System, Computing
and Engineering, {ICCSCE} 2015, Penang, Malaysia, November 27-29,
2015},
pages = {36--41},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICCSCE.2015.7482154},
doi = {10.1109/ICCSCE.2015.7482154},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/iccsce/AyatHB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icit2/Calvo-GallegoSJ15,
author = {Elisa Calvo{-}Gallego and
Santiago S{\'{a}}nchez{-}Solano and
Piedad Brox Jim{\'{e}}nez},
title = {Hardware implementation of a background substraction algorithm in
FPGA-based platforms},
booktitle = {{IEEE} International Conference on Industrial Technology, {ICIT} 2015,
Seville, Spain, March 17-19, 2015},
pages = {1688--1693},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICIT.2015.7125340},
doi = {10.1109/ICIT.2015.7125340},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icit2/Calvo-GallegoSJ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icsenst/NakayamaSYI15,
author = {Masashi Nakayama and
Naoki Shigekawa and
Takashi Yokouchi and
Shunsuke Ishimitsu},
title = {Frame-by-frame speech recognition as hardware decoding on {FPGA} devices},
booktitle = {9th International Conference on Sensing Technology, {ICST} 2015, Auckland,
New Zealand, December 8-10, 2015},
pages = {785--788},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICSensT.2015.7438503},
doi = {10.1109/ICSENST.2015.7438503},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/icsenst/NakayamaSYI15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/Morales-Villanueva15,
author = {Aurelio Morales{-}Villanueva and
Ann Gordon{-}Ross},
title = {Partial Region and Bitstream Cost Models for Hardware Multitasking
on Partially Reconfigurable FPGAs},
booktitle = {2015 {IEEE} International Parallel and Distributed Processing Symposium
Workshop, {IPDPS} 2015, Hyderabad, India, May 25-29, 2015},
pages = {90--96},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/IPDPSW.2015.148},
doi = {10.1109/IPDPSW.2015.148},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/Morales-Villanueva15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/BenacerHK15a,
author = {Imad Benacer and
Aicha Hamissi and
Abdelhakim Khouas},
title = {Hardware design and {FPGA} implementation for road plane extraction
based on V-disparity approach},
booktitle = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2015, Lisbon, Portugal, May 24-27, 2015},
pages = {2053--2056},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISCAS.2015.7169081},
doi = {10.1109/ISCAS.2015.7169081},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/BenacerHK15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispass/HoGNNMAFCS15,
author = {Chen{-}Han Ho and
Venkatraman Govindaraju and
Tony Nowatzki and
Ranjini Nagaraju and
Zachary Marzec and
Preeti Agarwal and
Chris Frericks and
Ryan Cofell and
Karthikeyan Sankaralingam},
title = {Performance evaluation of a DySER {FPGA} prototype system spanning
the compiler, microarchitecture, and hardware implementation},
booktitle = {2015 {IEEE} International Symposium on Performance Analysis of Systems
and Software, {ISPASS} 2015, Philadelphia, PA, USA, March 29-31, 2015},
pages = {203--214},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ISPASS.2015.7095806},
doi = {10.1109/ISPASS.2015.7095806},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispass/HoGNNMAFCS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispdc/MatsumotoNI15,
author = {Naoyuki Matsumoto and
Koji Nakano and
Yasuaki Ito},
editor = {Daniel Grosu and
Hai Jin and
George Papadopoulos},
title = {Optimal Parallel Hardware K-Sorter and Top K-Sorter, with {FPGA} Implementations},
booktitle = {14th International Symposium on Parallel and Distributed Computing,
{ISPDC} 2015, Limassol, Cyprus, June 29 - July 2, 2015},
pages = {138--147},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ISPDC.2015.23},
doi = {10.1109/ISPDC.2015.23},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispdc/MatsumotoNI15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isspit/CardarilliCNPR15,
author = {Gian Carlo Cardarilli and
Leonardo Di Carlo and
Alberto Nannarelli and
Federico Maria Pandolfi and
Marco Re},
title = {A framework for dynamically-loaded hardware library {(HLL)} in {FPGA}
acceleration},
booktitle = {{IEEE} International Symposium on Signal Processing and Information
Technology, {ISSPIT} 2015, Abu Dhabi, United Arab Emirates, December
7-10, 2015},
pages = {291--296},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ISSPIT.2015.7394346},
doi = {10.1109/ISSPIT.2015.7394346},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isspit/CardarilliCNPR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwst/SangLFLB15,
author = {Le Xuan Sang and
Lo{\"{\i}}c Lagadec and
Luc Fabresse and
Jannik Laval and
Noury Bouraqadi},
editor = {Jannik Laval and
Anne Etien},
title = {A Meta Model Supporting Both Hardware and Smalltalk-Based Execution
of Fpga Circuits},
booktitle = {Proceedings of the International Workshop on Smalltalk Technologies,
{IWST} 2015, Brescia, Italy, July 15-16, 2015},
pages = {6:1--6:14},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2811237.2811296},
doi = {10.1145/2811237.2811296},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwst/SangLFLB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lascas/SanchezPML15,
author = {Luis Sanchez and
Giancarlo Patino and
V{\'{\i}}ctor Murray and
James Lyke},
title = {Hardware implementation of a FPGA-based universal link for {LVDS}
communications},
booktitle = {{IEEE} 6th Latin American Symposium on Circuits {\&} Systems,
{LASCAS} 2015, Montevideo, Uruguay, February 24-27, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/LASCAS.2015.7250480},
doi = {10.1109/LASCAS.2015.7250480},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/lascas/SanchezPML15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mixdes/MatogaKGZP15,
author = {Lukasz Matoga and
Arkadiusz Koczor and
Michal Golek and
Pawel Zadek and
Piotr Penkala},
title = {Modular FPGA-based hardware platform for emulation},
booktitle = {22nd International Conference Mixed Design of Integrated Circuits
{\&} Systems, {MIXDES} 2015, Torun, Poland, June 25-27, 2015},
pages = {402--408},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/MIXDES.2015.7208551},
doi = {10.1109/MIXDES.2015.7208551},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/mixdes/MatogaKGZP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mmar/MohammediKMH15,
author = {Amine Mohammedi and
Nadir Kabache and
Samir Moulahoum and
Hamza Houassine},
title = {{FPGA} hardware in the loop validation of direct torque control for
induction motor},
booktitle = {20th International Conference on Methods and Models in Automation
and Robotics, {MMAR} 2015, Mi{\k{e}}dzyzdroje, Poland, August 24-27,
2015},
pages = {812--816},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/MMAR.2015.7283980},
doi = {10.1109/MMAR.2015.7283980},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/mmar/MohammediKMH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ner/JindalSDCD15,
author = {Utkarsh Jindal and
Mehak Sood and
Abhijit Das and
Shubhajit Roy Chowdhury and
Anirban Dutta},
title = {Near infra-red spectroscopy combined with transcranial direct current
stimulation in FPGA-based hardware for point of care testing of cerebral
vascular status - {A} stroke study},
booktitle = {7th International {IEEE/EMBS} Conference on Neural Engineering, {NER}
2015, Montpellier, France, April 22-24, 2015},
pages = {1040--1043},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/NER.2015.7146805},
doi = {10.1109/NER.2015.7146805},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ner/JindalSDCD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/ContrerasCML15,
author = {Luis Contreras and
S{\'{e}}rgio Cruz and
Jos{\'{e}} Maur{\'{\i}}cio S. T. Motta and
Carlos H. Llanos},
editor = {Michael H{\"{u}}bner and
Maya B. Gokhale and
Ren{\'{e}} Cumplido},
title = {{FPGA} implementation of the {EKF} algorithm for localization in mobile
robotics using a unified hardware module approach},
booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig
2015, Riviera Maya, Mexico, December 7-9, 2015},
pages = {1--6},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ReConFig.2015.7393315},
doi = {10.1109/RECONFIG.2015.7393315},
timestamp = {Wed, 28 Apr 2021 16:06:54 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/ContrerasCML15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/JaeschkeIZHP15,
author = {Timo Jaeschke and
Patrick Imberg and
Michael Zapke and
Michael H{\"{u}}bner and
Nils Pohl},
editor = {Michael H{\"{u}}bner and
Maya B. Gokhale and
Ren{\'{e}} Cumplido},
title = {Scalable modular hardware platform for {FPGA} based industrial radar
flowmeters},
booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig
2015, Riviera Maya, Mexico, December 7-9, 2015},
pages = {1--6},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ReConFig.2015.7393357},
doi = {10.1109/RECONFIG.2015.7393357},
timestamp = {Wed, 28 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/JaeschkeIZHP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/RodriguezVT15,
author = {Alfonso Rodr{\'{\i}}guez and
Juan Valverde and
Eduardo de la Torre},
editor = {Michael H{\"{u}}bner and
Maya B. Gokhale and
Ren{\'{e}} Cumplido},
title = {Design of OpenCL-compatible multithreaded hardware accelerators with
dynamic support for embedded FPGAs},
booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig
2015, Riviera Maya, Mexico, December 7-9, 2015},
pages = {1--7},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ReConFig.2015.7393297},
doi = {10.1109/RECONFIG.2015.7393297},
timestamp = {Tue, 03 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/reconfig/RodriguezVT15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rivp/KachouriA15,
author = {Rostom Kachouri and
Mohamed Akil},
editor = {Nasser Kehtarnavaz and
Matthias F. Carlsohn},
title = {Hardware design to accelerate {PNG} encoder for binary mask compression
on {FPGA}},
booktitle = {Real-Time Image and Video Processing 2015, San Francisco, CA, USA,
February 10, 2015},
series = {{SPIE} Proceedings},
volume = {9400},
pages = {940003},
publisher = {{SPIE}},
year = {2015},
url = {https://doi.org/10.1117/12.2076483},
doi = {10.1117/12.2076483},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rivp/KachouriA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/siot/BreierH15,
author = {Jakub Breier and
Wei He},
editor = {Gabriel Ghinita and
Pedro Peris{-}Lopez},
title = {Multiple Fault Attack on {PRESENT} with a Hardware Trojan Implementation
in {FPGA}},
booktitle = {2015 International Workshop on Secure Internet of Things, SIoT 2015,
Vienna, Austria, September 21-25, 2015},
pages = {58--64},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/SIOT.2015.15},
doi = {10.1109/SIOT.2015.15},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/siot/BreierH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/GargALS15,
author = {Kratika Garg and
Yan Lin Aung and
Siew Kei Lam and
Thambipillai Srikanthan},
title = {KnapSim - Run-time efficient hardware-software partitioning technique
for FPGAs},
booktitle = {28th {IEEE} International System-on-Chip Conference, {SOCC} 2015,
Beijing, China, September 8-11, 2015},
pages = {64--69},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/SOCC.2015.7406912},
doi = {10.1109/SOCC.2015.7406912},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/GargALS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KhanKBK15,
author = {Asim Khan and
Muhammad Umar Karim Khan and
Muhammad Bilal and
Chong{-}Min Kyung},
title = {Hardware architecture and optimization of sliding window based pedestrian
detection on {FPGA} for high resolution images by varying local features},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {142--148},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314406},
doi = {10.1109/VLSI-SOC.2015.7314406},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KhanKBK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vtc/TadzaTL15,
author = {Nina Tadza and
John S. Thompson and
David I. Laurenson},
title = {Power Performance Analysis of the Iterative-MIMO Adaptive Switching
Algorithm Detector on the {FPGA} Hardware},
booktitle = {{IEEE} 81st Vehicular Technology Conference, {VTC} Spring 2015, Glasgow,
United Kingdom, 11-14 May, 2015},
pages = {1--5},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VTCSpring.2015.7146022},
doi = {10.1109/VTCSPRING.2015.7146022},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/vtc/TadzaTL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:series/sfsc/MhadhbiLOS15,
author = {Im{\`{e}}ne Mhadhbi and
Nabil Litayem and
Slim Ben Othman and
Slim Ben Saoud},
editor = {Quanmin Zhu and
Ahmad Taher Azar},
title = {Impact of Hardware/Software Partitioning and MicroBlaze {FPGA} Configurations
on the Embedded Systems Performances},
booktitle = {Complex System Modelling and Control Through Intelligent Soft Computations},
series = {Studies in Fuzziness and Soft Computing},
volume = {319},
pages = {711--744},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-12883-2\_25},
doi = {10.1007/978-3-319-12883-2\_25},
timestamp = {Mon, 16 Sep 2019 14:42:59 +0200},
biburl = {https://dblp.org/rec/series/sfsc/MhadhbiLOS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/ChangMC15,
author = {Andre Xian Ming Chang and
Berin Martini and
Eugenio Culurciello},
title = {Recurrent Neural Networks Hardware Implementation on {FPGA}},
journal = {CoRR},
volume = {abs/1511.05552},
year = {2015},
url = {http://arxiv.org/abs/1511.05552},
eprinttype = {arXiv},
eprint = {1511.05552},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/ChangMC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/MollerKMZ15,
author = {Konrad M{\"{o}}ller and
Martin Kumm and
Charles{-}Frederic M{\"{u}}ller and
Peter Zipf},
title = {Model-based Hardware Design for FPGAs using Folding Transformations
based on Subcircuits},
journal = {CoRR},
volume = {abs/1508.06811},
year = {2015},
url = {http://arxiv.org/abs/1508.06811},
eprinttype = {arXiv},
eprint = {1508.06811},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/MollerKMZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iacr/BrinciKMRB15,
author = {Riadh Brinci and
Walid Khmiri and
Mefteh Mbarek and
Abdellatif Ben Rabaa and
Ammar Bouall{\`{e}}gue},
title = {Efficient Hardware Design for Computing Pairings Using Few {FPGA}
In-built DSPs},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {116},
year = {2015},
url = {http://eprint.iacr.org/2015/116},
timestamp = {Mon, 11 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iacr/BrinciKMRB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/asc/JuangJ14,
author = {Chia{-}Feng Juang and
Wen{-}Sheng Jang},
title = {A type-2 neural fuzzy system learned through type-1 fuzzy rules and
its FPGA-based hardware implementation},
journal = {Appl. Soft Comput.},
volume = {18},
pages = {302--313},
year = {2014},
url = {https://doi.org/10.1016/j.asoc.2014.01.006},
doi = {10.1016/J.ASOC.2014.01.006},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/asc/JuangJ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/LeCIP14,
author = {Duc{-}Hung Le and
Tran Bao Thuong Cao and
Katsumi Inoue and
Cong{-}Kha Pham},
title = {A CAM-Based Information Detection Hardware System for Fast Image Matching
on {FPGA}},
journal = {{IEICE} Trans. Electron.},
volume = {97-C},
number = {1},
pages = {65--76},
year = {2014},
url = {https://doi.org/10.1587/transele.E97.C.65},
doi = {10.1587/TRANSELE.E97.C.65},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/LeCIP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijdsn/MalikTSL14,
author = {Abdul Waheed Malik and
Benny Th{\"{o}}rnberg and
Muhammad Imran and
Najeem Lawal},
title = {Hardware Architecture for Real-Time Computation of Image Component
Feature Descriptors on a {FPGA}},
journal = {Int. J. Distributed Sens. Networks},
volume = {10},
year = {2014},
url = {https://doi.org/10.1155/2014/815378},
doi = {10.1155/2014/815378},
timestamp = {Thu, 03 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijdsn/MalikTSL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijrc/JaquenodVS14,
author = {Guillermo A. Jaquenod and
Javier Valls and
Javier Siman},
title = {Efficient {FPGA} Hardware Reuse in a Multiplierless Decimation Chain},
journal = {Int. J. Reconfigurable Comput.},
volume = {2014},
pages = {546264:1--546264:5},
year = {2014},
url = {https://doi.org/10.1155/2014/546264},
doi = {10.1155/2014/546264},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijrc/JaquenodVS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijrc/TippettsLLA14,
author = {Beau J. Tippetts and
Dah{-}Jye Lee and
Kirt D. Lillywhite and
James K. Archibald},
title = {Hardware-Efficient Design of Real-Time Profile Shape Matching Stereo
Vision Algorithm on {FPGA}},
journal = {Int. J. Reconfigurable Comput.},
volume = {2014},
pages = {945926:1--945926:12},
year = {2014},
url = {https://doi.org/10.1155/2014/945926},
doi = {10.1155/2014/945926},
timestamp = {Mon, 26 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijrc/TippettsLLA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcp/ShengLLX14,
author = {Yingying Sheng and
Yan Liu and
Renfa Li and
Xiongren Xiao},
title = {A Communication-aware Scheduling Algorithm for Hardware Task Scheduling
Model on FPGA-based Reconfigurable Systems},
journal = {J. Comput.},
volume = {9},
number = {11},
pages = {2552--2558},
year = {2014},
url = {http://www.jcomputers.us/index.php?m=content\&c=index\&a=show\&catid=150\&id=2440},
doi = {10.4304/JCP.9.11.2552-2558},
timestamp = {Thu, 25 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcp/ShengLLX14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/Jain-MendonS14,
author = {Shweta Jain{-}Mendon and
Ron Sass},
title = {A hardware-software co-design approach for implementing sparse matrix
vector multiplication on FPGAs},
journal = {Microprocess. Microsystems},
volume = {38},
number = {8},
pages = {873--888},
year = {2014},
url = {https://doi.org/10.1016/j.micpro.2014.02.004},
doi = {10.1016/J.MICPRO.2014.02.004},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/Jain-MendonS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/KliemV14,
author = {Daniel Kliem and
Sven{-}Ole Voigt},
title = {Scalability evaluation of an FPGA-based multi-core architecture with
hardware-enforced domain partitioning},
journal = {Microprocess. Microsystems},
volume = {38},
number = {8},
pages = {845--859},
year = {2014},
url = {https://doi.org/10.1016/j.micpro.2014.02.006},
doi = {10.1016/J.MICPRO.2014.02.006},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/KliemV14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/GosheblaghM14,
author = {Reza Omidi Gosheblagh and
Karim Mohammadi},
title = {Hybrid time and hardware redundancy to mitigate {SEU} effects on SRAM-FPGAs:
Case study over the MicroLAN protocol},
journal = {Microelectron. J.},
volume = {45},
number = {7},
pages = {870--879},
year = {2014},
url = {https://doi.org/10.1016/j.mejo.2014.04.006},
doi = {10.1016/J.MEJO.2014.04.006},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/GosheblaghM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/AtBOSY14,
author = {Nuray At and
Jean{-}Luc Beuchat and
Eiji Okamoto and
Ismail San and
Teppei Yamazaki},
title = {Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and
Skein on {FPGA}},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {61-I},
number = {2},
pages = {485--498},
year = {2014},
url = {https://doi.org/10.1109/TCSI.2013.2278385},
doi = {10.1109/TCSI.2013.2278385},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/AtBOSY14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tifs/ZhangC14,
author = {Li Zhang and
Chip{-}Hong Chang},
title = {A Pragmatic Per-Device Licensing Scheme for Hardware {IP} Cores on
SRAM-Based FPGAs},
journal = {{IEEE} Trans. Inf. Forensics Secur.},
volume = {9},
number = {11},
pages = {1893--1905},
year = {2014},
url = {https://doi.org/10.1109/TIFS.2014.2355043},
doi = {10.1109/TIFS.2014.2355043},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tifs/ZhangC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tii/WangSD14,
author = {Wentao Wang and
Zhuoxuan Shen and
Venkata Dinavahi},
title = {Physics-Based Device-Level Power Electronic Circuit Hardware Emulation
on {FPGA}},
journal = {{IEEE} Trans. Ind. Informatics},
volume = {10},
number = {4},
pages = {2166--2179},
year = {2014},
url = {https://doi.org/10.1109/TII.2014.2361656},
doi = {10.1109/TII.2014.2361656},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tii/WangSD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/JainPCFM14,
author = {Abhishek Kumar Jain and
Khoa Dang Pham and
Jin Cui and
Suhaib A. Fahmy and
Douglas L. Maskell},
title = {Virtualized Execution and Management of Hardware Tasks on a Hybrid
{ARM-FPGA} Platform},
journal = {J. Signal Process. Syst.},
volume = {77},
number = {1-2},
pages = {61--76},
year = {2014},
url = {https://doi.org/10.1007/s11265-014-0884-1},
doi = {10.1007/S11265-014-0884-1},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/JainPCFM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ahs/DumitriuKK14,
author = {Victor Dumitriu and
Lev Kirischian and
Valeri Kirischian},
title = {Decentralized run-time recovery mechanism for transient and permanent
hardware faults for space-borne FPGA-based computing systems},
booktitle = {2014 {NASA/ESA} Conference on Adaptive Hardware and Systems, {AHS}
2014, Leicester, United Kingdom, July 14-17, 2014},
pages = {47--54},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/AHS.2014.6880157},
doi = {10.1109/AHS.2014.6880157},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/ahs/DumitriuKK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ahs/LopezVTR14,
author = {Blanca L{\'{o}}pez and
Juan Valverde and
Eduardo de la Torre and
Teresa Riesgo},
title = {Power-aware multi-objective evolvable hardware system on an {FPGA}},
booktitle = {2014 {NASA/ESA} Conference on Adaptive Hardware and Systems, {AHS}
2014, Leicester, United Kingdom, July 14-17, 2014},
pages = {61--68},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/AHS.2014.6880159},
doi = {10.1109/AHS.2014.6880159},
timestamp = {Sun, 12 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ahs/LopezVTR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/JohnsonSCMG14,
author = {Anju P. Johnson and
Sayandeep Saha and
Rajat Subhra Chakraborty and
Debdeep Mukhopadhyay and
Sezer G{\"{o}}ren},
editor = {Ting Yu and
Shengqi Yang},
title = {Fault attack on {AES} via hardware Trojan insertion by dynamic partial
reconfiguration of {FPGA} over ethernet},
booktitle = {Proceedings of the 9th Workshop on Embedded Systems Security, {WESS}
'14, New Delhi, India, October 17, 2014},
pages = {1:1--1:8},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2668322.2668323},
doi = {10.1145/2668322.2668323},
timestamp = {Tue, 16 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/JohnsonSCMG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cse/LiFLW14,
author = {Han Li and
Yuzhuo Fu and
Ting Liu and
Jiafang Wang},
editor = {Xingang Liu and
Didier El Baz and
Ching{-}Hsien Hsu and
Kai Kang and
Weifeng Chen},
title = {Fast Protocol Decoding in Parallel with {FPGA} Hardware},
booktitle = {17th {IEEE} International Conference on Computational Science and
Engineering, {CSE} 2014, Chengdu, China, December 19-21, 2014},
pages = {1669--1673},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/CSE.2014.307},
doi = {10.1109/CSE.2014.307},
timestamp = {Thu, 20 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cse/LiFLW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cvpr/EibensteinerKS14,
author = {Florian Eibensteiner and
J{\"{u}}rgen Kogler and
Josef Scharinger},
title = {A High-Performance Hardware Architecture for a Frameless Stereo Vision
Algorithm Implemented on a {FPGA} Platform},
booktitle = {{IEEE} Conference on Computer Vision and Pattern Recognition, {CVPR}
Workshops 2014, Columbus, OH, USA, June 23-28, 2014},
pages = {637--644},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/CVPRW.2014.97},
doi = {10.1109/CVPRW.2014.97},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cvpr/EibensteinerKS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/HindborgSJK14,
author = {Andreas Erik Hindborg and
Pascal Schleuniger and
Nicklas Bo Jensen and
Sven Karlsson},
editor = {Eduardo de la Torre and
S{\'{e}}bastien Pillement},
title = {Hardware realization of an {FPGA} processor - Operating system call
offload and experiences},
booktitle = {Proceedings of the 2014 Conference on Design and Architectures for
Signal and Image Processing, {DASIP} 2014, Madrid, Spain, October
8-10, 2014},
pages = {1--8},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/DASIP.2014.7115604},
doi = {10.1109/DASIP.2014.7115604},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/dasip/HindborgSJK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/Malik14,
author = {Peter Mal{\'{\i}}k},
title = {Dedicated hardware architecture for object tracking preprocessing
implemented in {FPGA}},
booktitle = {17th International Symposium on Design and Diagnostics of Electronic
Circuits {\&} Systems, {DDECS} 2014, Warsaw, Poland, 23-25 April,
2014},
pages = {250--253},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/DDECS.2014.6868801},
doi = {10.1109/DDECS.2014.6868801},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/Malik14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ewdts/YanovskayaYK14,
author = {Olga Yanovskaya and
Max Yanovsky and
Vyacheslav S. Kharchenko},
title = {The concept of green Cloud infrastructure based on distributed computing
and hardware accelerator within {FPGA} as a Service},
booktitle = {2014 East-West Design {\&} Test Symposium, {EWDTS} 2014, Kiev,
Ukraine, September 26-29, 2014},
pages = {1--4},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/EWDTS.2014.7027089},
doi = {10.1109/EWDTS.2014.7027089},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ewdts/YanovskayaYK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/BymaSBLC14,
author = {Stuart Byma and
J. Gregory Steffan and
Hadi Bannazadeh and
Alberto Leon{-}Garcia and
Paul Chow},
title = {FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with
OpenStack},
booktitle = {22nd {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2014, Boston, MA, USA, May 11-13, 2014},
pages = {109--116},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/FCCM.2014.42},
doi = {10.1109/FCCM.2014.42},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/BymaSBLC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/CasperO14,
author = {Jared Casper and
Kunle Olukotun},
editor = {Vaughn Betz and
George A. Constantinides},
title = {Hardware acceleration of database operations},
booktitle = {The 2014 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} '14, Monterey, CA, {USA} - February 26 - 28, 2014},
pages = {151--160},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2554688.2554787},
doi = {10.1145/2554688.2554787},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/CasperO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ShilaV14,
author = {Devu Manikantan Shila and
Vivek Venugopal},
editor = {Vaughn Betz and
George A. Constantinides},
title = {Design, implementation and security analysis of hardware trojan threats
in {FPGA} (abstract only)},
booktitle = {The 2014 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} '14, Monterey, CA, {USA} - February 26 - 28, 2014},
pages = {247},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2554688.2554713},
doi = {10.1145/2554688.2554713},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ShilaV14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/BlanchardonCMA14,
author = {Adrien Blanchardon and
Roselyne Chotin{-}Avot and
Habib Mehrez and
Emna Amouri},
title = {Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster
{FPGA} using hardware redundancy},
booktitle = {24th International Conference on Field Programmable Logic and Applications,
{FPL} 2014, Munich, Germany, 2-4 September, 2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPL.2014.6927389},
doi = {10.1109/FPL.2014.6927389},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/BlanchardonCMA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/BlockM14,
author = {Henry Block and
Tsutomu Maruyama},
title = {An {FPGA} hardware acceleration of the indirect calculation of tree
lengths method for phylogenetic tree reconstruction},
booktitle = {24th International Conference on Field Programmable Logic and Applications,
{FPL} 2014, Munich, Germany, 2-4 September, 2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPL.2014.6927430},
doi = {10.1109/FPL.2014.6927430},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/BlockM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/Pietras14,
author = {Marcin Pietras},
title = {Hardware conversion of neural networks simulation models for neural
processing accelerator implemented as FPGA-based SoC},
booktitle = {24th International Conference on Field Programmable Logic and Applications,
{FPL} 2014, Munich, Germany, 2-4 September, 2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPL.2014.6927383},
doi = {10.1109/FPL.2014.6927383},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/Pietras14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/PohlSK14,
author = {Matthias Pohl and
Michael Schaeferling and
Gundolf Kiefer},
title = {An efficient FPGA-based hardware framework for natural feature extraction
and related Computer Vision tasks},
booktitle = {24th International Conference on Field Programmable Logic and Applications,
{FPL} 2014, Munich, Germany, 2-4 September, 2014},
pages = {1--8},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPL.2014.6927463},
doi = {10.1109/FPL.2014.6927463},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/PohlSK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/Takamaeda-YamazakiK14,
author = {Shinya Takamaeda{-}Yamazaki and
Kenji Kise},
title = {flipSyrup: Cycle-accurate hardware simulation framework on abstract
{FPGA} platforms},
booktitle = {24th International Conference on Field Programmable Logic and Applications,
{FPL} 2014, Munich, Germany, 2-4 September, 2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPL.2014.6927436},
doi = {10.1109/FPL.2014.6927436},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/Takamaeda-YamazakiK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/Kojima14,
author = {Akira Kojima},
editor = {Jialin Chen and
Wenbo Yin and
Yuichiro Shibata and
Lingli Wang and
Hayden Kwok{-}Hay So and
Yuchun Ma},
title = {{FPGA} implementation of Blokus Duo player using hardware/software
co-design},
booktitle = {2014 International Conference on Field-Programmable Technology, {FPT}
2014, Shanghai, China, December 10-12, 2014},
pages = {378--381},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPT.2014.7082825},
doi = {10.1109/FPT.2014.7082825},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/Kojima14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fuzzIEEE/SchrieberB14,
author = {Matthew D. Schrieber and
Mohammad Biglarbegian},
title = {Hardware implementation of a novel inference engine for interval type-2
fuzzy control on {FPGA}},
booktitle = {{IEEE} International Conference on Fuzzy Systems, {FUZZ-IEEE} 2014,
Beijing, China, July 6-11, 2014},
pages = {640--646},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FUZZ-IEEE.2014.6891677},
doi = {10.1109/FUZZ-IEEE.2014.6891677},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fuzzIEEE/SchrieberB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Mal-SarkarKGB14,
author = {Sanchita Mal{-}Sarkar and
Aswin Raghav Krishna and
Anandaroop Ghosh and
Swarup Bhunia},
editor = {Joseph R. Cavallaro and
Tong Zhang and
Alex K. Jones and
Hai (Helen) Li},
title = {Hardware trojan attacks in {FPGA} devices: threat analysis and effective
counter measures},
booktitle = {Great Lakes Symposium on {VLSI} 2014, {GLSVLSI} '14, Houston, TX,
{USA} - May 21 - 23, 2014},
pages = {287--292},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2591513.2591520},
doi = {10.1145/2591513.2591520},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Mal-SarkarKGB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/host/SollKMH14,
author = {Oliver Soll and
Thomas Korak and
Michael Muehlberghuber and
Michael Hutter},
title = {EM-based detection of hardware trojans on FPGAs},
booktitle = {2014 {IEEE} International Symposium on Hardware-Oriented Security
and Trust, {HOST} 2014, Arlington, VA, USA, May 6-7, 2014},
pages = {84--87},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/HST.2014.6855574},
doi = {10.1109/HST.2014.6855574},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/host/SollKMH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpec/HoareS14,
author = {Raymond R. Hoare and
Denis Smetana},
title = {Accelerating {SAR} processing on {COTS} {FPGA} hardware using C-to-gates
design tools},
booktitle = {{IEEE} High Performance Extreme Computing Conference, {HPEC} 2014,
Waltham, MA, USA, September 9-11, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/HPEC.2014.7040995},
doi = {10.1109/HPEC.2014.7040995},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/hpec/HoareS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icacci/Neelam14,
author = {Sapta Girish Neelam},
title = {Hardware-efficient {FPGA} implementation of symbol {\&} carrier
synchronization for 16-QAM},
booktitle = {2014 International Conference on Advances in Computing, Communications
and Informatics, {ICACCI} 2014, Delhi, India, September 24-27, 2014},
pages = {630--634},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICACCI.2014.6968199},
doi = {10.1109/ICACCI.2014.6968199},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icacci/Neelam14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icc/ShilaV14,
author = {Devu Manikantan Shila and
Vivek Venugopal},
title = {Design, implementation and security analysis of Hardware Trojan Threats
in {FPGA}},
booktitle = {{IEEE} International Conference on Communications, {ICC} 2014, Sydney,
Australia, June 10-14, 2014},
pages = {719--724},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICC.2014.6883404},
doi = {10.1109/ICC.2014.6883404},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/icc/ShilaV14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccS/BodiscoDKBH14,
author = {Timothy Bodisco and
Jason D'Netto and
Neil Kelson and
Jasmine Banks and
Ross Hayward},
editor = {David Abramson and
Michael Lees and
Valeria V. Krzhizhanovskaya and
Jack J. Dongarra and
Peter M. A. Sloot},
title = {Computation of {ECG} Signal Features Using {MCMC} Modelling in Software
and {FPGA} Reconfigurable Hardware},
booktitle = {Proceedings of the International Conference on Computational Science,
{ICCS} 2014, Cairns, Queensland, Australia, 10-12 June, 2014},
series = {Procedia Computer Science},
volume = {29},
pages = {2442--2448},
publisher = {Elsevier},
year = {2014},
url = {https://doi.org/10.1016/j.procs.2014.05.228},
doi = {10.1016/J.PROCS.2014.05.228},
timestamp = {Tue, 20 Jun 2023 16:27:45 +0200},
biburl = {https://dblp.org/rec/conf/iccS/BodiscoDKBH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccS/WarneKH14,
author = {David J. Warne and
Neil A. Kelson and
Ross F. Hayward},
editor = {David Abramson and
Michael Lees and
Valeria V. Krzhizhanovskaya and
Jack J. Dongarra and
Peter M. A. Sloot},
title = {Comparison of High Level {FPGA} Hardware Design for Solving Tri-diagonal
Linear Systems},
booktitle = {Proceedings of the International Conference on Computational Science,
{ICCS} 2014, Cairns, Queensland, Australia, 10-12 June, 2014},
series = {Procedia Computer Science},
volume = {29},
pages = {95--101},
publisher = {Elsevier},
year = {2014},
url = {https://doi.org/10.1016/j.procs.2014.05.009},
doi = {10.1016/J.PROCS.2014.05.009},
timestamp = {Sun, 04 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccS/WarneKH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icce-tw/LinF14,
author = {Kuen{-}Chih Lin and
Wai{-}Chi Fang},
title = {A highly integrated hardware design implemented on {FPGA} for a wireless
healthcare monitoring system},
booktitle = {{IEEE} International Conference on Consumer Electronics - Taiwan,
{ICCE-TW} 2014, Taipei, Taiwan, May 26-28, 2014},
pages = {187--188},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICCE-TW.2014.6904051},
doi = {10.1109/ICCE-TW.2014.6904051},
timestamp = {Thu, 25 Nov 2021 16:44:13 +0100},
biburl = {https://dblp.org/rec/conf/icce-tw/LinF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/TarawnehR14,
author = {Ghaith Tarawneh and
Jenny C. A. Read},
title = {An FPGA-based hardware accelerator for simulating spatiotemporal neurons},
booktitle = {21st {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2014, Marseille, France, December 7-10, 2014},
pages = {618--621},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICECS.2014.7050061},
doi = {10.1109/ICECS.2014.7050061},
timestamp = {Thu, 08 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/TarawnehR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icm2/HannachiRJAM14,
author = {Marwa Hannachi and
Hassan Rabah and
Slavisa Jovanovic and
Abdessalem Ben Abdelali and
Abdellatif Mtibaa},
title = {Efficient relocation of variable-sized hardware tasks for FPGA-based
adaptive systems},
booktitle = {26th International Conference on Microelectronics, {ICM} 2014, Doha,
Qatar, December 14-17, 2014},
pages = {224--227},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICM.2014.7071847},
doi = {10.1109/ICM.2014.7071847},
timestamp = {Mon, 09 Aug 2021 14:54:02 +0200},
biburl = {https://dblp.org/rec/conf/icm2/HannachiRJAM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iecon/SchmittRJB14,
author = {Alexander Schmitt and
Jan Richter and
Uli Jurkewitz and
Michael Braun},
title = {FPGA-based real-time simulation of nonlinear permanent magnet synchronous
machines for power hardware-in-the-loop emulation systems},
booktitle = {{IECON} 2014 - 40th Annual Conference of the {IEEE} Industrial Electronics
Society, Dallas, TX, USA, October 29 - November 1, 2014},
pages = {3763--3769},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/IECON.2014.7049060},
doi = {10.1109/IECON.2014.7049060},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iecon/SchmittRJB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ijcnn/RenRCMZ14,
author = {Xiaowei Ren and
Pengju Ren and
Badong Chen and
Tai Min and
Nanning Zheng},
title = {Hardware implementation of {KLMS} algorithm using {FPGA}},
booktitle = {2014 International Joint Conference on Neural Networks, {IJCNN} 2014,
Beijing, China, July 6-11, 2014},
pages = {2276--2281},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/IJCNN.2014.6889689},
doi = {10.1109/IJCNN.2014.6889689},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ijcnn/RenRCMZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iros/HoneggerOP14,
author = {Dominik Honegger and
Helen Oleynikova and
Marc Pollefeys},
title = {Real-time and low latency embedded computer vision hardware based
on a combination of {FPGA} and mobile {CPU}},
booktitle = {2014 {IEEE/RSJ} International Conference on Intelligent Robots and
Systems, {IROS} 2014, Chicago, IL, USA, September 14-18, 2014},
pages = {4930--4935},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/IROS.2014.6943263},
doi = {10.1109/IROS.2014.6943263},
timestamp = {Tue, 05 Sep 2023 15:07:47 +0200},
biburl = {https://dblp.org/rec/conf/iros/HoneggerOP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SirkunanOSHM14,
author = {Jeevan Sirkunan and
Chia Yee Ooi and
Nasir Shaikh{-}Husin and
Yuan Wen Hau and
Muhammad Nadzir Marsono},
title = {Hardware transactional memory on multi-processor {FPGA} platform},
booktitle = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
Melbourne, Victoria, Australia, June 1-5, 2014},
pages = {2744--2747},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISCAS.2014.6865741},
doi = {10.1109/ISCAS.2014.6865741},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SirkunanOSHM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/0001BMR14,
author = {Sudip Ghosh and
Arijit Biswas and
Santi P. Maity and
Hafizur Rahaman},
title = {Design of a Low Complexity and Fast Hardware Architecture for Digital
Image Watermarking in {FWHT} Domain on {FPGA}},
booktitle = {2014 Fifth International Symposium on Electronic System Design, Surathkal,
Mangalore, India, December 15-17, 2014},
pages = {68--72},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ISED.2014.22},
doi = {10.1109/ISED.2014.22},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ised/0001BMR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isie/RajeshRGS14,
author = {P. Rajesh and
S. Rajasekar and
Rajesh Gupta and
Paulson Samuel},
title = {Solar array system simulation using {FPGA} with hardware co-simulation},
booktitle = {23rd {IEEE} International Symposium on Industrial Electronics, {ISIE}
2014, Istanbul, Turkey, June 1-4, 2014},
pages = {2291--2296},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISIE.2014.6864975},
doi = {10.1109/ISIE.2014.6864975},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isie/RajeshRGS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispec/TangLCP14,
author = {Shaohua Tang and
Bo Lv and
Guomin Chen and
Zhiniang Peng},
editor = {Xinyi Huang and
Jianying Zhou},
title = {Efficient Hardware Implementation of {MQ} Asymmetric Cipher {PMI+}
on FPGAs},
booktitle = {Information Security Practice and Experience - 10th International
Conference, {ISPEC} 2014, Fuzhou, China, May 5-8, 2014. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {8434},
pages = {187--201},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-06320-1\_15},
doi = {10.1007/978-3-319-06320-1\_15},
timestamp = {Fri, 09 Apr 2021 18:45:22 +0200},
biburl = {https://dblp.org/rec/conf/ispec/TangLCP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/jckbse/AndreevDEZSA14,
author = {Andrey Andreev and
Evgueni Doukhnitch and
Vitaly Egunov and
Dmitriy Zharikov and
Oleg Shapovalov and
Sergey Artuh},
editor = {Alla G. Kravets and
Maxim Shcherbakov and
Marina V. Kultsova and
Tadashi Iijima},
title = {Evaluation of Hardware Implementations of CORDIC-Like Algorithms in
{FPGA} Using OpenCL Kernels},
booktitle = {Knowledge-Based Software Engineering - 11th Joint Conference, {JCKBSE}
2014, Volgograd, Russia, September 17-20, 2014. Proceedings},
series = {Communications in Computer and Information Science},
volume = {466},
pages = {228--242},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-11854-3\_20},
doi = {10.1007/978-3-319-11854-3\_20},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/jckbse/AndreevDEZSA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nabic/MachadoWM14,
author = {Pedro Machado and
John J. Wade and
T. Martin McGinnity},
title = {Si elegans: {FPGA} hardware emulation of C. elegans nematode nervous
system},
booktitle = {2014 Sixth World Congress on Nature and Biologically Inspired Computing,
NaBIC 2014, Porto, Portugal, July 30 - August 1, 2014},
pages = {65--71},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/NaBIC.2014.6921855},
doi = {10.1109/NABIC.2014.6921855},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/nabic/MachadoWM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/neurotechnix/KrewerCCM14,
author = {Finn Krewer and
Aedan Coffey and
Frank Callaly and
Fearghal Morgan},
editor = {Ana Rita Londral and
Pedro Encarna{\c{c}}{\~{a}}o},
title = {Neuron Models in {FPGA} Hardware - {A} Route from High Level Descriptions
to Hardware Implementations},
booktitle = {Proceedings of the 2nd International Congress on Neurotechnology,
Electronics and Informatics, {NEUROTECHNIX} 2014, Rome, Italy, October
25-26, 2014},
pages = {177--183},
publisher = {SciTePress},
year = {2014},
url = {https://doi.org/10.5220/0005190501770183},
doi = {10.5220/0005190501770183},
timestamp = {Sat, 16 Dec 2017 12:52:01 +0100},
biburl = {https://dblp.org/rec/conf/neurotechnix/KrewerCCM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/norchip/ToftN14,
author = {Jakob Kenn Toft and
Alberto Nannarelli},
title = {Energy efficient {FPGA} based hardware accelerators for financial
applications},
booktitle = {2014 NORCHIP, Tampere, Finland, October 27-28, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/NORCHIP.2014.7004741},
doi = {10.1109/NORCHIP.2014.7004741},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/norchip/ToftN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/HesselbarthBB14,
author = {Sebastian Hesselbarth and
Tim Baumgart and
Holger Blume},
title = {Hardware-assisted power estimation for design-stage processors using
{FPGA} emulation},
booktitle = {24th International Workshop on Power and Timing Modeling, Optimization
and Simulation, PATMOS), Palma de Mallorca, Spain, September 29 -
Oct. 1, 2014},
pages = {1--8},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/PATMOS.2014.6951877},
doi = {10.1109/PATMOS.2014.6951877},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/HesselbarthBB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/DingH14,
author = {Hongyuan Ding and
Miaoqing Huang},
title = {A unified OpenCL-flavor programming model with scalable hybrid hardware
platform on FPGAs},
booktitle = {2014 International Conference on ReConFigurable Computing and FPGAs,
ReConFig14, Cancun, Mexico, December 8-10, 2014},
pages = {1--7},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ReConFig.2014.7032563},
doi = {10.1109/RECONFIG.2014.7032563},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/DingH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/LuoFFDLK14,
author = {Pei Luo and
Yunsi Fei and
Xin Fang and
A. Adam Ding and
Miriam Leeser and
David R. Kaeli},
title = {Power analysis attack on hardware implementation of MAC-Keccak on
FPGAs},
booktitle = {2014 International Conference on ReConFigurable Computing and FPGAs,
ReConFig14, Cancun, Mexico, December 8-10, 2014},
pages = {1--7},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ReConFig.2014.7032549},
doi = {10.1109/RECONFIG.2014.7032549},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/LuoFFDLK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/recosoc/YingHH14,
author = {Haoyuan Ying and
Thomas Hollstein and
Klaus Hofmann},
title = {A hardware/software co-design reconfigurable Network-on-Chip {FPGA}
emulation method},
booktitle = {9th International Symposium on Reconfigurable and Communication-Centric
Systems-on-Chip, ReCoSoC 2014, Montpellier, France, May 26-28, 2014},
pages = {1--8},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ReCoSoC.2014.6861336},
doi = {10.1109/RECOSOC.2014.6861336},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/recosoc/YingHH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbac-pad/SilvaS14,
author = {Antonio Carlos Fernandes da Silva and
Jorge Luiz e Silva},
title = {The ChipCflow: {A} Tool to Generate Hardware Accelerators Using a
Static Dataflow Machine Designed for a {FPGA}},
booktitle = {26th {IEEE} International Symposium on Computer Architecture and High
Performance Computing Workshop, {SBAC-PAD} Workshop 2014, Paris, France,
October 22-24, 2014},
pages = {90--95},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/SBAC-PADW.2014.19},
doi = {10.1109/SBAC-PADW.2014.19},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbac-pad/SilvaS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/KhurshidM14,
author = {Burhan Khurshid and
Roohie Naaz Mir},
title = {A Hardware Intensive Approach for Efficient Implementation of Numerical
Integration for {FPGA} Platforms},
booktitle = {2014 27th International Conference on {VLSI} Design, {VLSID} 2014,
and 2014 13th International Conference on Embedded Systems, Mumbai,
India, January 5-9, 2014},
pages = {312--317},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/VLSID.2014.60},
doi = {10.1109/VLSID.2014.60},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/KhurshidM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/MiyajimaTA14,
author = {Takaaki Miyajima and
David B. Thomas and
Hideharu Amano},
title = {An Automatic Mixed Software Hardware Pipeline Builder for {CPU-FPGA}
Platforms},
journal = {CoRR},
volume = {abs/1408.4969},
year = {2014},
url = {http://arxiv.org/abs/1408.4969},
eprinttype = {arXiv},
eprint = {1408.4969},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/MiyajimaTA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/VidanagamachchiDRN14,
author = {S. M. Vidanagamachchi and
S. D. Dewasurendra and
Roshan G. Ragel and
M. Niranjan},
title = {Tile optimization for area in {FPGA} based hardware acceleration of
peptide identification},
journal = {CoRR},
volume = {abs/1403.7296},
year = {2014},
url = {http://arxiv.org/abs/1403.7296},
eprinttype = {arXiv},
eprint = {1403.7296},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/VidanagamachchiDRN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iacr/LuoFFDLK14,
author = {Pei Luo and
Yunsi Fei and
Xin Fang and
A. Adam Ding and
Miriam Leeser and
David R. Kaeli},
title = {Power Analysis Attack on Hardware Implementation of MAC-Keccak on
FPGAs},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {854},
year = {2014},
url = {http://eprint.iacr.org/2014/854},
timestamp = {Wed, 20 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iacr/LuoFFDLK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/basesearch/Choi13a,
author = {Yuk{-}Ming Choi},
title = {A run-time hardware task execution framework for FPGA-accelerated
heterogeneous cluster},
school = {University of Hong Kong},
year = {2013},
url = {https://hdl.handle.net/10722/206679},
timestamp = {Wed, 04 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/basesearch/Choi13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/dnb/Schmidt13,
author = {Michael Schmidt},
title = {Evaluierung gitterbasierter Pfadplanungs-Algorithmen f{\"{u}}r
die Hardwarebeschleunigung mit FPGAs},
school = {University of Erlangen-Nuremberg},
year = {2013},
url = {http://opus4.kobv.de/opus4-fau/frontdoor/index/index/docId/3873},
urn = {urn:nbn:de:bvb:29-opus4-38734},
timestamp = {Sat, 17 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/dnb/Schmidt13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/hal/Trabelsi13,
author = {Chiraz Trabelsi},
title = {Contr{\^{o}}le mat{\'{e}}riel des syst{\`{e}}mes partiellement
reconfigurables sur {FPGA} : de la mod{\'{e}}lisation {\`{a}}
l'impl{\'{e}}mentation. (Hardware Control of partially reconfigurable
FPGA-systems: from modeling to implementation)},
school = {Lille University of Science and Technology, France},
year = {2013},
url = {https://tel.archives-ouvertes.fr/tel-00852361},
timestamp = {Tue, 21 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/hal/Trabelsi13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/caee/Guzman-RamirezG13,
author = {Enrique Guzm{\'{a}}n{-}Ram{\'{\i}}rez and
Iv{\'{a}}n A. Garc{\'{\i}}a},
title = {Using the project-based learning approach for incorporating an FPGA-based
integrated hardware/software tool for implementing and evaluating
image processing algorithms into graduate level courses},
journal = {Comput. Appl. Eng. Educ.},
volume = {21},
number = {{S1}},
pages = {E73--E88},
year = {2013},
url = {https://doi.org/10.1002/cae.21563},
doi = {10.1002/CAE.21563},
timestamp = {Wed, 09 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/caee/Guzman-RamirezG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/candie/Santiago-PerezORM13,
author = {J. Jesus de Santiago{-}Perez and
Roque Alfredo Osornio{-}Rios and
Ren{\'{e}} de Jes{\'{u}}s Romero{-}Troncoso and
Luis Morales{-}Velazquez},
title = {FPGA-based hardware {CNC} interpolator of Bezier, splines, B-splines
and {NURBS} curves for industrial applications},
journal = {Comput. Ind. Eng.},
volume = {66},
number = {4},
pages = {925--932},
year = {2013},
url = {https://doi.org/10.1016/j.cie.2013.08.024},
doi = {10.1016/J.CIE.2013.08.024},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/candie/Santiago-PerezORM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computing/NambiarBHM13,
author = {Vishnu P. Nambiar and
Sathivellu Balakrishnan and
Mohamed Khalil Hani and
Muhammad N. Marsono},
title = {{HW/SW} co-design of reconfigurable hardware-based genetic algorithm
in FPGAs applicable to a variety of problems},
journal = {Computing},
volume = {95},
number = {9},
pages = {863--896},
year = {2013},
url = {https://doi.org/10.1007/s00607-013-0305-5},
doi = {10.1007/S00607-013-0305-5},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/computing/NambiarBHM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/ChakrabortySPN13,
author = {Rajat Subhra Chakraborty and
Indrasish Saha and
Ayan Palchaudhuri and
Gowtham Kumar Naik},
title = {Hardware Trojan Insertion by Direct Modification of {FPGA} Configuration
Bitstream},
journal = {{IEEE} Des. Test},
volume = {30},
number = {2},
pages = {45--54},
year = {2013},
url = {https://doi.org/10.1109/MDT.2013.2247460},
doi = {10.1109/MDT.2013.2247460},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/ChakrabortySPN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/CristoFGPM13,
author = {Alejandro Cristo and
Kevin Fisher and
J. Anthony Gualtieri and
Rosa M. P{\'{e}}rez and
Pablo Mart{\'{\i}}nez},
title = {Optimization of Processor-to-Hardware Module Communications on Spaceborne
Hybrid FPGA-based Architectures},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {5},
number = {4},
pages = {77--80},
year = {2013},
url = {https://doi.org/10.1109/LES.2013.2286812},
doi = {10.1109/LES.2013.2286812},
timestamp = {Mon, 19 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/CristoFGPM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijrc/IturbeBHEAM13,
author = {Xabier Iturbe and
Khaled Benkrid and
Chuan Hong and
Ali Ebrahim and
Tughrul Arslan and
Imanol Martinez},
title = {Runtime Scheduling, Allocation, and Execution of Real-Time Hardware
Tasks onto Xilinx FPGAs Subject to Fault Occurrence},
journal = {Int. J. Reconfigurable Comput.},
volume = {2013},
pages = {905057:1--905057:32},
year = {2013},
url = {https://doi.org/10.1155/2013/905057},
doi = {10.1155/2013/905057},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijrc/IturbeBHEAM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijrc/JozwikHETT13,
author = {Krzysztof Jozwik and
Shinya Honda and
Masato Edahiro and
Hiroyuki Tomiyama and
Hiroaki Takada},
title = {Rainbow: An Operating System for Software-Hardware Multitasking on
Dynamically Partially Reconfigurable FPGAs},
journal = {Int. J. Reconfigurable Comput.},
volume = {2013},
pages = {789134:1--789134:40},
year = {2013},
url = {https://doi.org/10.1155/2013/789134},
doi = {10.1155/2013/789134},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijrc/JozwikHETT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PapadopoulosKPT13,
author = {Agathoklis Papadopoulos and
Ioannis Kirmitzoglou and
Vasilis J. Promponas and
Theocharis Theocharides},
title = {FPGA-based hardware acceleration for local complexity analysis of
massive genomic data},
journal = {Integr.},
volume = {46},
number = {3},
pages = {230--239},
year = {2013},
url = {https://doi.org/10.1016/j.vlsi.2012.10.003},
doi = {10.1016/J.VLSI.2012.10.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PapadopoulosKPT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/BarkalovTMS13,
author = {Alexander Barkalov and
Larysa Titarenko and
Raisa Malcheva and
Kyryll Soldatov},
title = {Hardware Reduction in FPGA-Based Moore {FSM}},
journal = {J. Circuits Syst. Comput.},
volume = {22},
number = {3},
year = {2013},
url = {https://doi.org/10.1142/S0218126613500060},
doi = {10.1142/S0218126613500060},
timestamp = {Tue, 26 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/BarkalovTMS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jnw/NiuWZGZ13,
author = {Xiaoxia Niu and
Yanxia Wu and
Bowei Zhang and
Guochang Gu and
Guoyin Zhang},
title = {Rapid FPGA-based Delay Estimation for the Hardware/Software Partitioning},
journal = {J. Networks},
volume = {8},
number = {5},
pages = {1183--1190},
year = {2013},
url = {https://doi.org/10.4304/jnw.8.5.1183-1190},
doi = {10.4304/JNW.8.5.1183-1190},
timestamp = {Tue, 15 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jnw/NiuWZGZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/GultekinS13,
author = {Gokhan Koray Gultekin and
Afsar Saranli},
title = {An {FPGA} based high performance optical flow hardware design for
computer vision applications},
journal = {Microprocess. Microsystems},
volume = {37},
number = {3},
pages = {270--286},
year = {2013},
url = {https://doi.org/10.1016/j.micpro.2013.01.001},
doi = {10.1016/J.MICPRO.2013.01.001},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/GultekinS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mcs/BahriIMB13,
author = {Imen Bahri and
Lahoucine Idkhajine and
Eric Monmasson and
Mohamed El Amine Benkhelifa},
title = {Optimal hardware/software partitioning of a system on chip FPGA-based
sensorless {AC} drive current controller},
journal = {Math. Comput. Simul.},
volume = {90},
pages = {145--161},
year = {2013},
url = {https://doi.org/10.1016/j.matcom.2012.06.008},
doi = {10.1016/J.MATCOM.2012.06.008},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mcs/BahriIMB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/BenrekiaAB13,
author = {Fay{\c{c}}al Benrekia and
Mokhtar Attari and
Mounir Bouhedda},
title = {Gas Sensors Characterization and Multilayer Perceptron {(MLP)} Hardware
Implementation for Gas Identification Using a Field Programmable Gate
Array {(FPGA)}},
journal = {Sensors},
volume = {13},
number = {3},
pages = {2967--2985},
year = {2013},
url = {https://doi.org/10.3390/s130302967},
doi = {10.3390/S130302967},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sensors/BenrekiaAB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/BiasizzoN13,
author = {Anton Biasizzo and
Franc Novak},
title = {Hardware Accelerated Compression of {LIDAR} Data Using {FPGA} Devices},
journal = {Sensors},
volume = {13},
number = {5},
pages = {6405--6422},
year = {2013},
url = {https://doi.org/10.3390/s130506405},
doi = {10.3390/S130506405},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sensors/BiasizzoN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tii/BahriIMB13,
author = {Imen Bahri and
Lahoucine Idkhajine and
Eric Monmasson and
Mohamed El Amine Benkhelifa},
title = {Hardware/Software Codesign Guidelines for System on Chip FPGA-Based
Sensorless {AC} Drive Applications},
journal = {{IEEE} Trans. Ind. Informatics},
volume = {9},
number = {4},
pages = {2165--2176},
year = {2013},
url = {https://doi.org/10.1109/TII.2013.2245908},
doi = {10.1109/TII.2013.2245908},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tii/BahriIMB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tii/BroxSTBM13,
author = {Mar{\'{\i}}a Brox and
Santiago S{\'{a}}nchez{-}Solano and
Ernesto del Toro and
Piedad Brox and
Francisco Jose Moreno{-}Velo},
title = {{CAD} Tools for Hardware Implementation of Embedded Fuzzy Systems
on FPGAs},
journal = {{IEEE} Trans. Ind. Informatics},
volume = {9},
number = {3},
pages = {1635--1644},
year = {2013},
url = {https://doi.org/10.1109/TII.2012.2228871},
doi = {10.1109/TII.2012.2228871},
timestamp = {Thu, 21 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tii/BroxSTBM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/WojcikowskiZPKS13,
author = {Marek W{\'{o}}jcikowski and
Robert Zaglewski and
Bogdan Pankiewicz and
Miron Klosowski and
Stanislaw Szczepanski},
title = {Hardware-Software Implementation of a Sensor Network for City Traffic
Monitoring Using the {FPGA-} and ASIC-Based Sensor Nodes},
journal = {J. Signal Process. Syst.},
volume = {71},
number = {1},
pages = {57--73},
year = {2013},
url = {https://doi.org/10.1007/s11265-012-0681-7},
doi = {10.1007/S11265-012-0681-7},
timestamp = {Thu, 16 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsisp/WojcikowskiZPKS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ant/KambaleDK13,
author = {Vianney Kambale and
Karim Djouani and
Anish Mathew Kurien},
editor = {Elhadi M. Shakshuki and
Karim Djouani and
Michael Sheng and
Mohamed F. Younis and
Eduardo Vaz and
Wayne Groszko},
title = {Toward an {FPGA} Hardware Implementation of the Alamouti 4x2 Space-time
Block Coding},
booktitle = {Proceedings of the 4th International Conference on Ambient Systems,
Networks and Technologies {(ANT} 2013), the 3rd International Conference
on Sustainable Energy Information Technology (SEIT-2013), Halifax,
Nova Scotia, Canada, June 25-28, 2013},
series = {Procedia Computer Science},
volume = {19},
pages = {602--608},
publisher = {Elsevier},
year = {2013},
url = {https://doi.org/10.1016/j.procs.2013.06.080},
doi = {10.1016/J.PROCS.2013.06.080},
timestamp = {Fri, 28 Jan 2022 08:58:39 +0100},
biburl = {https://dblp.org/rec/conf/ant/KambaleDK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/Morales-VillanuevaG13,
author = {Aurelio Morales{-}Villanueva and
Ann Gordon{-}Ross},
editor = {Philip Brisk and
Jos{\'{e}} Gabriel F. Coutinho and
Pedro C. Diniz},
title = {{HTR:} On-Chip Hardware Task Relocation for Partially Reconfigurable
FPGAs},
booktitle = {Reconfigurable Computing: Architectures, Tools and Applications -
9th International Symposium, {ARC} 2013, Los Angeles, CA, USA, March
25-27, 2013. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7806},
pages = {185--196},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-642-36812-7\_18},
doi = {10.1007/978-3-642-36812-7\_18},
timestamp = {Fri, 27 Mar 2020 08:54:48 +0100},
biburl = {https://dblp.org/rec/conf/arc/Morales-VillanuevaG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/SchmidtF13,
author = {Andrew G. Schmidt and
Matthew French},
title = {Fast lossless image compression with Radiation Hardening by hardware/software
co-design on platform FPGAs},
booktitle = {24th International Conference on Application-Specific Systems, Architectures
and Processors, {ASAP} 2013, Washington, DC, USA, June 5-7, 2013},
pages = {103--106},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ASAP.2013.6567560},
doi = {10.1109/ASAP.2013.6567560},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/SchmidtF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/WangBP13,
author = {Wei Wang and
Miodrag Bolic and
Jonathan Parri},
title = {pvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized
environment},
booktitle = {Proceedings of the International Conference on Hardware/Software Codesign
and System Synthesis, {CODES+ISSS} 2013, Montreal, QC, Canada, September
29 - October 4, 2013},
pages = {10:1--10:9},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CODES-ISSS.2013.6658997},
doi = {10.1109/CODES-ISSS.2013.6658997},
timestamp = {Wed, 16 Oct 2019 14:14:48 +0200},
biburl = {https://dblp.org/rec/conf/codes/WangBP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/IvanA13,
author = {Teodor Ivan and
El Mostapha Aboulhamid},
title = {An Efficient Hardware Implementation of a {SAT} Problem Solver on
{FPGA}},
booktitle = {2013 Euromicro Conference on Digital System Design, {DSD} 2013, Los
Alamitos, CA, USA, September 4-6, 2013},
pages = {209--216},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/DSD.2013.31},
doi = {10.1109/DSD.2013.31},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/IvanA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/Morales-SandovalD13,
author = {Miguel Morales{-}Sandoval and
Arturo Diaz{-}Perez},
title = {Compact FPGA-Based Hardware Architectures for GF(2m) Multipliers},
booktitle = {2013 Euromicro Conference on Digital System Design, {DSD} 2013, Los
Alamitos, CA, USA, September 4-6, 2013},
pages = {649--652},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/DSD.2013.124},
doi = {10.1109/DSD.2013.124},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/Morales-SandovalD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/VelegalatiSK13,
author = {Rajesh Velegalati and
Kinjal Shah and
Jens{-}Peter Kaps},
title = {Glitch Detection in Hardware Implementations on FPGAs Using Delay
Based Sampling Techniques},
booktitle = {2013 Euromicro Conference on Digital System Design, {DSD} 2013, Los
Alamitos, CA, USA, September 4-6, 2013},
pages = {947--954},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/DSD.2013.107},
doi = {10.1109/DSD.2013.107},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/VelegalatiSK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/Morales-VillanuevaG13,
author = {Aurelio Morales{-}Villanueva and
Ann Gordon{-}Ross},
title = {On-chip Context Save and Restore of Hardware Tasks on Partially Reconfigurable
FPGAs},
booktitle = {21st {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2013, Seattle, WA, USA, April 28-30, 2013},
pages = {61--64},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/FCCM.2013.13},
doi = {10.1109/FCCM.2013.13},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/Morales-VillanuevaG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/ZhangLLCCZB13,
author = {Jiliang Zhang and
Yaping Lin and
Yongqiang Lu and
Ray C. C. Cheung and
Wenjie Che and
Qiang Zhou and
Jinian Bian},
title = {Binding Hardware IPs to Specific {FPGA} Device via Inter-twining the
{PUF} Response with the {FSM} of Sequential Circuits},
booktitle = {21st {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2013, Seattle, WA, USA, April 28-30, 2013},
pages = {227},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/FCCM.2013.12},
doi = {10.1109/FCCM.2013.12},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/ZhangLLCCZB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/BaiFLR13,
author = {Yu Bai and
Abigail Fuentes{-}Rivera and
Mingjie Lin and
Mike Riera},
editor = {Brad L. Hutchings and
Vaughn Betz},
title = {Exploiting algorithmic-level memory parallelism in distributed logic-memory
architecture through hardware-assisted dynamic graph (abstract only)},
booktitle = {The 2013 {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} '13, Monterey, CA, USA, February 11-13, 2013},
pages = {273},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2435264.2435333},
doi = {10.1145/2435264.2435333},
timestamp = {Thu, 02 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/BaiFLR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DaigneaultD13,
author = {Marc{-}Andr{\'{e}} Daigneault and
Jean{-}Pierre David},
editor = {Brad L. Hutchings and
Vaughn Betz},
title = {Hardware description and synthesis of control-intensive reconfigurable
dataflow architectures (abstract only)},
booktitle = {The 2013 {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} '13, Monterey, CA, USA, February 11-13, 2013},
pages = {274--275},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2435264.2435337},
doi = {10.1145/2435264.2435337},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/DaigneaultD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DengZ13,
author = {Wenjuan Deng and
Yiqun Zhu},
editor = {Brad L. Hutchings and
Vaughn Betz},
title = {A memory-efficient hardware architecture for real-time feature detection
of the {SIFT} algorithm (abstract only)},
booktitle = {The 2013 {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} '13, Monterey, CA, USA, February 11-13, 2013},
pages = {273},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2435264.2435332},
doi = {10.1145/2435264.2435332},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/DengZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HariaP13,
author = {Swapnil Haria and
Viktor K. Prasanna},
editor = {Brad L. Hutchings and
Vaughn Betz},
title = {AutoMapper: an automated tool for optimal hardware resource allocation
for networking applications on {FPGA} (abstract only)},
booktitle = {The 2013 {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} '13, Monterey, CA, USA, February 11-13, 2013},
pages = {274},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2435264.2435335},
doi = {10.1145/2435264.2435335},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/HariaP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/OngLA13,
author = {Soon Ee Ong and
Siaw Chen Lee and
Noohul Basheer Zain Ali},
editor = {Brad L. Hutchings and
Vaughn Betz},
title = {Hardware implemented real-time operating system (abstract only)},
booktitle = {The 2013 {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} '13, Monterey, CA, USA, February 11-13, 2013},
pages = {266},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2435264.2435314},
doi = {10.1145/2435264.2435314},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/OngLA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/VenugopalS13,
author = {Vivek Venugopal and
Devu Manikantan Shila},
editor = {Brad L. Hutchings and
Vaughn Betz},
title = {Hardware acceleration of {TEA} and {XTEA} algorithms on FPGA, {GPU}
and multi-core processors (abstract only)},
booktitle = {The 2013 {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} '13, Monterey, CA, USA, February 11-13, 2013},
pages = {270},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2435264.2435326},
doi = {10.1145/2435264.2435326},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/VenugopalS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WangLZMC13,
author = {Chao Wang and
Xi Li and
Xuehai Zhou and
Jim Martin and
Ray C. C. Cheung},
editor = {Brad L. Hutchings and
Vaughn Betz},
title = {Genome sequencing using mapreduce on {FPGA} with multiple hardware
accelerators (abstract only)},
booktitle = {The 2013 {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} '13, Monterey, CA, USA, February 11-13, 2013},
pages = {266},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2435264.2435313},
doi = {10.1145/2435264.2435313},
timestamp = {Wed, 19 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/WangLZMC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ChenZL13,
author = {Yi{-}Chung Chen and
Wei Zhang and
Hai (Helen) Li},
title = {A hardware security scheme for RRAM-based {FPGA}},
booktitle = {23rd International Conference on Field programmable Logic and Applications,
{FPL} 2013, Porto, Portugal, September 2-4, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPL.2013.6645556},
doi = {10.1109/FPL.2013.6645556},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/ChenZL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/YaoLSC13,
author = {Yuan Yao and
Zhongyong Lu and
Qingsong Shi and
Wenzhi Chen},
title = {{FPGA} based hardware-software co-designed dynamic binary translation
system},
booktitle = {23rd International Conference on Field programmable Logic and Applications,
{FPL} 2013, Porto, Portugal, September 2-4, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPL.2013.6645554},
doi = {10.1109/FPL.2013.6645554},
timestamp = {Fri, 10 Nov 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/YaoLSC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ZemcikJMMH13a,
author = {Pavel Zemc{\'{\i}}k and
Roman Jur{\'{a}}nek and
Petr Musil and
Martin Musil and
Michal Hradis},
title = {High performance {FPGA} object detector: Hardware prototype},
booktitle = {23rd International Conference on Field programmable Logic and Applications,
{FPL} 2013, Porto, Portugal, September 2-4, 2013},
pages = {1},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPL.2013.6645622},
doi = {10.1109/FPL.2013.6645622},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/ZemcikJMMH13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/BlockM13,
author = {Henry Block and
Tsutomu Maruyama},
title = {A hardware acceleration of a phylogenetic tree reconstruction with
maximum parsimony algorithm using {FPGA}},
booktitle = {2013 International Conference on Field-Programmable Technology, {FPT}
2013, Kyoto, Japan, December 9-11, 2013},
pages = {318--321},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPT.2013.6718376},
doi = {10.1109/FPT.2013.6718376},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/BlockM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/ChoiBA13,
author = {Jongsok Choi and
Stephen Dean Brown and
Jason Helge Anderson},
title = {From software threads to parallel hardware in high-level synthesis
for FPGAs},
booktitle = {2013 International Conference on Field-Programmable Technology, {FPT}
2013, Kyoto, Japan, December 9-11, 2013},
pages = {270--277},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPT.2013.6718365},
doi = {10.1109/FPT.2013.6718365},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/ChoiBA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/FanWCZWW13,
author = {Xitian Fan and
Chenlu Wu and
Wei Cao and
Xuegong Zhou and
Shengye Wang and
Lingli Wang},
title = {Implementation of high performance hardware architecture of OpenSURF
algorithm on {FPGA}},
booktitle = {2013 International Conference on Field-Programmable Technology, {FPT}
2013, Kyoto, Japan, December 9-11, 2013},
pages = {152--159},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPT.2013.6718346},
doi = {10.1109/FPT.2013.6718346},
timestamp = {Mon, 06 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/FanWCZWW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icaisc/KluskaH13,
author = {Jacek Kluska and
Zbigniew Hajduk},
editor = {Leszek Rutkowski and
Marcin Korytkowski and
Rafal Scherer and
Ryszard Tadeusiewicz and
Lotfi A. Zadeh and
Jacek M. Zurada},
title = {Hardware Implementation of {P1-TS} Fuzzy Rule-Based Systems on {FPGA}},
booktitle = {Artificial Intelligence and Soft Computing - 12th International Conference,
{ICAISC} 2013, Zakopane, Poland, June 9-13, 2013, Proceedings, Part
{I}},
series = {Lecture Notes in Computer Science},
volume = {7894},
pages = {282--293},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-642-38658-9\_26},
doi = {10.1007/978-3-642-38658-9\_26},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icaisc/KluskaH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/OhataSOMOCIIAMK13,
author = {Katsuki Ohata and
Yukitoshi Sanada and
Tetsuro Ogaki and
Kento Matsuyama and
Takanori Ohira and
Satoshi Chikuda and
Masaki Igarashi and
Masayuki Ikebe and
Tetsuya Asai and
Masato Motomura and
Tadahiro Kuroda},
title = {Hardware-oriented stereo vision algorithm based on 1-D guided filtering
and its {FPGA} implementation},
booktitle = {20th {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2013, Abu Dhabi, UAE, December 8-11, 2013},
pages = {169--172},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ICECS.2013.6815381},
doi = {10.1109/ICECS.2013.6815381},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/OhataSOMOCIIAMK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpads/IbrahimTIBY13,
author = {Muhammad Nasir Ibrahim and
Chen Kean Tack and
Mariani Idroas and
Siti Noormaya Bilmas and
Zuraimi Yahya},
title = {Hardware Implementation of Math Module Based on {CORDIC} Algorithm
Using {FPGA}},
booktitle = {19th {IEEE} International Conference on Parallel and Distributed Systems,
{ICPADS} 2013, Seoul, Korea, December 15-18, 2013},
pages = {628--632},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ICPADS.2013.112},
doi = {10.1109/ICPADS.2013.112},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpads/IbrahimTIBY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/KnodelGLNS13,
author = {Oliver Knodel and
Andy Georgi and
Patrick Lehmann and
Wolfgang E. Nagel and
Rainer G. Spallek},
title = {Integration of a Highly Scalable, Multi-FPGA-Based Hardware Accelerator
in Common Cluster Infrastructures},
booktitle = {42nd International Conference on Parallel Processing, {ICPP} 2013,
Lyon, France, October 1-4, 2013},
pages = {893--900},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ICPP.2013.106},
doi = {10.1109/ICPP.2013.106},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpp/KnodelGLNS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iecon/AraujoLAMG13,
author = {Jos{\'{e}} {\'{A}}ngel Araujo and
Jes{\'{u}}s L{\'{a}}zaro and
Armando Astarloa and
Naiara Moreira and
Alain Garc{\'{\i}}a},
title = {Memory requirements analysis for {PRP} and {HSR} hardware implementations
on FPGAs},
booktitle = {{IECON} 2013 - 39th Annual Conference of the {IEEE} Industrial Electronics
Society, Vienna, Austria, November 10-13, 2013},
pages = {2297--2302},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/IECON.2013.6699489},
doi = {10.1109/IECON.2013.6699489},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/iecon/AraujoLAMG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iecon/DagbagiHINMS13,
author = {Mohamed Dagbagi and
Asma Hemdani and
Lahoucine Idkhajine and
Mohamed Wissem Naouar and
Eric Monmasson and
Ilhem Slama{-}Belkhodja},
title = {FPGA-based Real-Time Hardware-In-the-Loop validation of a 3-phase
{PWM} rectifier controller},
booktitle = {{IECON} 2013 - 39th Annual Conference of the {IEEE} Industrial Electronics
Society, Vienna, Austria, November 10-13, 2013},
pages = {5374--5379},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/IECON.2013.6700010},
doi = {10.1109/IECON.2013.6700010},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iecon/DagbagiHINMS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iecon/Khalil-HaniL13,
author = {Mohamed Khalil Hani and
Yee Hui Lee},
title = {{FPGA} embedded hardware system for finger vein biometric recognition},
booktitle = {{IECON} 2013 - 39th Annual Conference of the {IEEE} Industrial Electronics
Society, Vienna, Austria, November 10-13, 2013},
pages = {2273--2278},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/IECON.2013.6699485},
doi = {10.1109/IECON.2013.6699485},
timestamp = {Wed, 19 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iecon/Khalil-HaniL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ieeehpcs/WernerGLP13,
author = {Stefan Werner and
Sven Groppe and
Volker Linnemann and
Thilo Pionteck},
title = {Hardware-accelerated join processing in large Semantic Web databases
with FPGAs},
booktitle = {International Conference on High Performance Computing {\&} Simulation,
{HPCS} 2013, Helsinki, Finland, July 1-5, 2013},
pages = {131--138},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/HPCSim.2013.6641403},
doi = {10.1109/HPCSIM.2013.6641403},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ieeehpcs/WernerGLP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/YangHH0GLL13,
author = {Enshan Yang and
Keheng Huang and
Yu Hu and
Xiaowei Li and
Jian Gong and
Hongjin Liu and
Bo Liu},
title = {{HHC:} Hierarchical hardware checkpointing to accelerate fault recovery
for SRAM-based FPGAs},
booktitle = {2013 {IEEE} 19th International On-Line Testing Symposium (IOLTS),
Chania, Crete, Greece, July 8-10, 2013},
pages = {193--198},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/IOLTS.2013.6604078},
doi = {10.1109/IOLTS.2013.6604078},
timestamp = {Fri, 25 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iolts/YangHH0GLL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/GallegoMOSTR13,
author = {Angel Gallego and
Javier Mora and
Andr{\'{e}}s Otero and
Rub{\'{e}}n Salvador and
Eduardo de la Torre and
Teresa Riesgo},
title = {A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing
Arrays},
booktitle = {2013 {IEEE} International Symposium on Parallel {\&} Distributed
Processing, Workshops and Phd Forum, Cambridge, MA, USA, May 20-24,
2013},
pages = {182--191},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/IPDPSW.2013.56},
doi = {10.1109/IPDPSW.2013.56},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/GallegoMOSTR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isie/GomesGPSCMT13,
author = {Tiago Gomes and
Paulo Garcia and
Sandro Pinto and
Filipe Salgado and
Jorge Cabral and
Jo{\~{a}}o Monteiro and
Adriano Tavares},
title = {Hardware-software extensions to a softcore processor for FPGA-based
adaptive {PID} control},
booktitle = {22nd {IEEE} International Symposium on Industrial Electronics, {ISIE}
2013, Taipei, Taiwan, May 28-31, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISIE.2013.6563670},
doi = {10.1109/ISIE.2013.6563670},
timestamp = {Thu, 10 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isie/GomesGPSCMT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispacs/ZhangJ13,
author = {Lijun Zhang and
Ying Jiang},
title = {A low-hardware consumption {FPGA} based configurable {LDPC} decoder},
booktitle = {International Symposium on Intelligent Signal Processing and Communication
Systems, {ISPACS} 2013, Naha-shi, Japan, November 12-15, 2013},
pages = {221--224},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISPACS.2013.6704550},
doi = {10.1109/ISPACS.2013.6704550},
timestamp = {Wed, 16 Oct 2019 14:14:51 +0200},
biburl = {https://dblp.org/rec/conf/ispacs/ZhangJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mixdes/KryjakKG13,
author = {Tomasz Kryjak and
Mateusz Komorkiewicz and
Marek Gorgon},
title = {Hardware implementation of the {PBAS} foreground detection method
in {FPGA}},
booktitle = {Proceedings of the 20th International Conference Mixed Design of Integrated
Circuits and Systems - {MIXDES} 2013, Gdynia, Poland, June 20-22,
2013},
pages = {479--484},
publisher = {{IEEE}},
year = {2013},
url = {https://ieeexplore.ieee.org/xpl/freeabs\_all.jsp?arnumber=6613400},
timestamp = {Wed, 11 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mixdes/KryjakKG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mse/SchmadeckeLBB13,
author = {Ingo Schm{\"{a}}decke and
Christian Leibold and
Hans{-}Peter Br{\"{u}}ckner and
Holger Blume},
title = {Project-organized education: From {FPGA} prototyping to {ASIC} design:
Consecutive microelectronic education in designing application-specific
hardware},
booktitle = {2013 {IEEE} International Conference on Microelectronic Systems Education,
{MSE} 2013, Austin, TX, USA, June 2-3, 2013},
pages = {9--12},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/MSE.2013.6566691},
doi = {10.1109/MSE.2013.6566691},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mse/SchmadeckeLBB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/npc/ZhangQQWZ13,
author = {Youhui Zhang and
Peng Qu and
Ziqiang Qian and
Hongwei Wang and
Weimin Zheng},
editor = {Ching{-}Hsien Hsu and
Xiaoming Li and
Xuanhua Shi and
Ran Zheng},
title = {Software/Hardware Hybrid Network-on-Chip Simulation on {FPGA}},
booktitle = {Network and Parallel Computing - 10th {IFIP} International Conference,
{NPC} 2013, Guiyang, China, September 19-21, 2013. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {8147},
pages = {167--178},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-642-40820-5\_15},
doi = {10.1007/978-3-642-40820-5\_15},
timestamp = {Tue, 14 May 2019 10:00:51 +0200},
biburl = {https://dblp.org/rec/conf/npc/ZhangQQWZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/recosoc/HempelHPH13,
author = {Gerald Hempel and
Jan Hoyer and
Thilo Pionteck and
Christian Hochberger},
title = {Register allocation for high-level synthesis of hardware accelerators
targeting FPGAs},
booktitle = {2013 8th International Workshop on Reconfigurable and Communication-Centric
Systems-on-Chip (ReCoSoC), Darmstadt, Germany, July 10-12, 2013},
pages = {1--6},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ReCoSoC.2013.6581522},
doi = {10.1109/RECOSOC.2013.6581522},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/recosoc/HempelHPH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/DiasMP13,
author = {Wanderson Roger Azevedo Dias and
Edward David Moreno and
Isaac Nattan Palmeira},
title = {A new code compression algorithm and its decompressor in FPGA-based
hardware},
booktitle = {26th Symposium on Integrated Circuits and Systems Design, {SBCCI}
2013, Curitiba, Brazil, September 2-6, 2013},
pages = {1--6},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/SBCCI.2013.6644870},
doi = {10.1109/SBCCI.2013.6644870},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/DiasMP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/siu/Aykenar13,
author = {Mehmet Burak Aykenar},
title = {Analysis of {FPGA} based recursive and non-recursive digital filters
according to hardware cost and performance},
booktitle = {21st Signal Processing and Communications Applications Conference,
{SIU} 2013, Haspolat, Turkey, April 24-26, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/SIU.2013.6531474},
doi = {10.1109/SIU.2013.6531474},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/siu/Aykenar13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/tsp/BeleanBB13,
author = {Bogdan Belean and
Monica Borda and
Adrian Bot},
title = {{FPGA} based hardware architectures for iterative algorithms implementations},
booktitle = {36th International Conference on Telecommunications and Signal Processing,
{TSP} 2013, Rome, Italy, 2-4 July, 2013},
pages = {751--754},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/TSP.2013.6614038},
doi = {10.1109/TSP.2013.6614038},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/tsp/BeleanBB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iacr/AtBOSY13,
author = {Nuray At and
Jean{-}Luc Beuchat and
Eiji Okamoto and
Ismail San and
Teppei Yamazaki},
title = {Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and
Skein on {FPGA}},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {113},
year = {2013},
url = {http://eprint.iacr.org/2013/113},
timestamp = {Mon, 11 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iacr/AtBOSY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iacr/TangLCP13,
author = {Shaohua Tang and
Bo Lv and
Guomin Chen and
Zhiniang Peng},
title = {Efficient Hardware Implementation of {MQ} Asymmetric Cipher {PMI+}
on FPGAs},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {878},
year = {2013},
url = {http://eprint.iacr.org/2013/878},
timestamp = {Mon, 11 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iacr/TangLCP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/basesearch/Matei12,
author = {Elena Matei},
title = {Hardware accelerated {H.264} blocks for processing multiple high definition
streams in real-time: novel architecture and realization on {FPGA}
platform},
school = {Ghent University, Belgium},
year = {2012},
url = {https://biblio.ugent.be/publication/3093901},
timestamp = {Mon, 02 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/phd/basesearch/Matei12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cai/SakellariouB12,
author = {Christos Sakellariou and
Peter J. Bentley},
title = {Describing the FPGA-Based Hardware Architecture of Systemic Computation
(HAoS)},
journal = {Comput. Informatics},
volume = {31},
number = {3},
pages = {485},
year = {2012},
url = {http://www.cai.sk/ojs/index.php/cai/article/view/1005},
timestamp = {Mon, 14 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cai/SakellariouB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dafes/HentatiEANA12,
author = {Manel Hentati and
Samya Elaoud and
Yassine Aoudni and
Jean{-}Fran{\c{c}}ois Nezan and
Mohamed Abid},
title = {An efficient Resource Management to optimize the placement of hardware
task on {FPGA} in the {RVC} framework},
journal = {Des. Autom. Embed. Syst.},
volume = {16},
number = {4},
pages = {363--380},
year = {2012},
url = {https://doi.org/10.1007/s10617-013-9115-4},
doi = {10.1007/S10617-013-9115-4},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dafes/HentatiEANA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/JozwikTHT12,
author = {Krzysztof Jozwik and
Hiroyuki Tomiyama and
Shinya Honda and
Hiroaki Takada},
title = {A Novel Framework for Effective Preemptive Hardware Multitasking on
FPGAs},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {95-D},
number = {2},
pages = {345--353},
year = {2012},
url = {https://doi.org/10.1587/transinf.E95.D.345},
doi = {10.1587/TRANSINF.E95.D.345},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/JozwikTHT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KanetaYMAM12,
author = {Yusaku Kaneta and
Shingo Yoshizawa and
Shin{-}ichi Minato and
Hiroki Arimura and
Yoshikazu Miyanaga},
title = {A Dynamically Reconfigurable FPGA-Based Pattern Matching Hardware
for Subclasses of Regular Expressions},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {95-D},
number = {7},
pages = {1847--1857},
year = {2012},
url = {https://doi.org/10.1587/transinf.E95.D.1847},
doi = {10.1587/TRANSINF.E95.D.1847},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KanetaYMAM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/LeISP12,
author = {Duc{-}Hung Le and
Katsumi Inoue and
Masahiro Sowa and
Cong{-}Kha Pham},
title = {An FPGA-Based Information Detection Hardware System Employing Multi-Match
Content Addressable Memory},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {95-A},
number = {10},
pages = {1708--1717},
year = {2012},
url = {https://doi.org/10.1587/transfun.E95.A.1708},
doi = {10.1587/TRANSFUN.E95.A.1708},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/LeISP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijrc/SchaeferlingHK12,
author = {Michael Schaeferling and
Ulrich Hornung and
Gundolf Kiefer},
title = {Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based
System Designs Accelerated by {FPGA} Logic},
journal = {Int. J. Reconfigurable Comput.},
volume = {2012},
pages = {368351:1--368351:16},
year = {2012},
url = {https://doi.org/10.1155/2012/368351},
doi = {10.1155/2012/368351},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijrc/SchaeferlingHK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijrc/SchmidtSFS12,
author = {Andrew G. Schmidt and
Neil Steiner and
Matthew French and
Ron Sass},
title = {HwPMI: An Extensible Performance Monitoring Infrastructure for Improving
Hardware Design and Productivity on FPGAs},
journal = {Int. J. Reconfigurable Comput.},
volume = {2012},
pages = {162404:1--162404:12},
year = {2012},
url = {https://doi.org/10.1155/2012/162404},
doi = {10.1155/2012/162404},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijrc/SchmidtSFS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/isjgp/SanA12,
author = {Ismail San and
Nuray At},
title = {Compact Keccak Hardware Architecture for Data Integrity and Authentication
on FPGAs},
journal = {Inf. Secur. J. {A} Glob. Perspect.},
volume = {21},
number = {5},
pages = {231--242},
year = {2012},
url = {https://doi.org/10.1080/19393555.2012.660678},
doi = {10.1080/19393555.2012.660678},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/isjgp/SanA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/SanoK12,
author = {Kentaro Sano and
Yoshiaki Kono},
title = {FPGA-based Connect6 solver with hardware-accelerated move refinement},
journal = {{SIGARCH} Comput. Archit. News},
volume = {40},
number = {5},
pages = {4--9},
year = {2012},
url = {https://doi.org/10.1145/2460216.2460218},
doi = {10.1145/2460216.2460218},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigarch/SanoK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/BrucknerLZBMO12,
author = {Timon Br{\"{u}}ckner and
Matthias Lorenz and
Christoph Zorn and
Joachim Becker and
Wolfgang Mathis and
Maurits Ortmanns},
title = {Hardware-Accelerated Simulation Environment for {CT} Sigma-Delta Modulators
Using an {FPGA}},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {59-II},
number = {8},
pages = {471--475},
year = {2012},
url = {https://doi.org/10.1109/TCSII.2012.2204120},
doi = {10.1109/TCSII.2012.2204120},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/BrucknerLZBMO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tgrs/BesirisTFT12,
author = {Dimitrios Besiris and
Vassilis Tsagaris and
Nikolaos Fragoulis and
Christos Theoharatos},
title = {An FPGA-Based Hardware Implementation of Configurable Pixel-Level
Color Image Fusion},
journal = {{IEEE} Trans. Geosci. Remote. Sens.},
volume = {50},
number = {2},
pages = {362--373},
year = {2012},
url = {https://doi.org/10.1109/TGRS.2011.2163723},
doi = {10.1109/TGRS.2011.2163723},
timestamp = {Tue, 12 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tgrs/BesirisTFT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tifs/MaesSV12,
author = {Roel Maes and
Dries Schellekens and
Ingrid Verbauwhede},
title = {A Pay-per-Use Licensing Scheme for Hardware {IP} Cores in Recent SRAM-Based
FPGAs},
journal = {{IEEE} Trans. Inf. Forensics Secur.},
volume = {7},
number = {1},
pages = {98--108},
year = {2012},
url = {https://doi.org/10.1109/TIFS.2011.2169667},
doi = {10.1109/TIFS.2011.2169667},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tifs/MaesSV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tii/AlecsaCO12,
author = {Bogdan Alecsa and
Marcian N. Cirstea and
Alexandru Onea},
title = {Simulink Modeling and Design of an Efficient Hardware-Constrained
FPGA-Based {PMSM} Speed Controller},
journal = {{IEEE} Trans. Ind. Informatics},
volume = {8},
number = {3},
pages = {554--562},
year = {2012},
url = {https://doi.org/10.1109/TII.2012.2193891},
doi = {10.1109/TII.2012.2193891},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tii/AlecsaCO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tits/McDonaldEPP12,
author = {Gregor J. McDonald and
Jonathan S. Ellis and
Richard W. Penney and
Richard W. Price},
title = {Real-Time Vehicle Identification Performance Using {FPGA} Correlator
Hardware},
journal = {{IEEE} Trans. Intell. Transp. Syst.},
volume = {13},
number = {4},
pages = {1891--1895},
year = {2012},
url = {https://doi.org/10.1109/TITS.2012.2189881},
doi = {10.1109/TITS.2012.2189881},
timestamp = {Tue, 24 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tits/McDonaldEPP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aciids/KasikPNPK12,
author = {Vladimir Kasik and
Marek Penhaker and
Vil{\'{e}}m Nov{\'{a}}k and
Radka Pustkova and
Frantisek Kutalek},
editor = {Jeng{-}Shyang Pan and
Shyi{-}Ming Chen and
Ngoc Thanh Nguyen},
title = {Bio-inspired Genetic Algorithms on {FPGA} Evolvable Hardware},
booktitle = {Intelligent Information and Database Systems - 4th Asian Conference,
{ACIIDS} 2012, Kaohsiung, Taiwan, March 19-21, 2012, Proceedings,
Part {II}},
series = {Lecture Notes in Computer Science},
volume = {7197},
pages = {439--447},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-28490-8\_46},
doi = {10.1007/978-3-642-28490-8\_46},
timestamp = {Thu, 16 Mar 2023 20:00:29 +0100},
biburl = {https://dblp.org/rec/conf/aciids/KasikPNPK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csndsp/NekoueiTKM12,
author = {Farzad Nekouei and
Neda Zargar Talebi and
Yousef Seifi Kavian and
Ali Mahani},
title = {{FPGA} implementation of {LMS} self correcting adaptive filter {(SCAF)}
and hardware analysis},
booktitle = {8th International Symposium on Communication Systems, Networks {\&}
Digital Signal Processing, {CSNDSP} 2012, Poznan, Poland, July 18-20,
2012},
pages = {1--5},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/CSNDSP.2012.6292753},
doi = {10.1109/CSNDSP.2012.6292753},
timestamp = {Tue, 20 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/csndsp/NekoueiTKM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/CorreHDHL12,
author = {Youenn Corre and
Van{-}Trinh Hoang and
Jean{-}Philippe Diguet and
Dominique Heller and
Lo{\"{\i}}c Lagadec},
title = {HLS-based fast design space exploration of ad hoc hardware accelerators:
{A} key tool for MPSoC synthesis on {FPGA}},
booktitle = {Proceedings of the 2012 Conference on Design and Architectures for
Signal and Image Processing, {DASIP} 2012, Karlsruhe, Germany, October
23-25, 2012},
pages = {1--8},
publisher = {{IEEE}},
year = {2012},
url = {https://ieeexplore.ieee.org/document/6385368/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/CorreHDHL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/TtofisT12,
author = {Christos Ttofis and
Theocharis Theocharides},
editor = {Wolfgang Rosenstiel and
Lothar Thiele},
title = {Towards accurate hardware stereo correspondence: {A} real-time {FPGA}
implementation of a segmentation-based adaptive support weight algorithm},
booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012},
pages = {703--708},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/DATE.2012.6176561},
doi = {10.1109/DATE.2012.6176561},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/TtofisT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/MavroidisMPLLTS12,
author = {Iakovos Mavroidis and
Ioannis Mavroidis and
Ioannis Papaefstathiou and
Luciano Lavagno and
Mihai T. Lazarescu and
Eduardo de la Torre and
Florian Sch{\"{a}}fer},
title = {{FASTCUDA:} Open Source {FPGA} Accelerator {\&} Hardware-Software
Codesign Toolset for {CUDA} Kernels},
booktitle = {15th Euromicro Conference on Digital System Design, {DSD} 2012, Cesme,
Izmir, Turkey, September 5-8, 2012},
pages = {343--348},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/DSD.2012.58},
doi = {10.1109/DSD.2012.58},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/MavroidisMPLLTS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/etfa/GacKP12,
author = {Konrad Gac and
Grzegorz Karpiel and
Maciej Petko},
title = {{FPGA} based hardware accelerator for calculations of the parallel
robot inverse kinematics},
booktitle = {Proceedings of 2012 {IEEE} 17th International Conference on Emerging
Technologies {\&} Factory Automation, {ETFA} 2012, Krakow, Poland,
September 17-21, 2012},
pages = {1--4},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ETFA.2012.6489717},
doi = {10.1109/ETFA.2012.6489717},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/etfa/GacKP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ChoiR12,
author = {Jungwook Choi and
Rob A. Rutenbar},
editor = {Dirk Koch and
Satnam Singh and
Jim T{\o}rresen},
title = {Hardware implementation of {MRF} map inference on an {FPGA} platform},
booktitle = {22nd International Conference on Field Programmable Logic and Applications
(FPL), Oslo, Norway, August 29-31, 2012},
pages = {209--216},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPL.2012.6339183},
doi = {10.1109/FPL.2012.6339183},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/ChoiR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/CzajkowskiADFKNWYS12,
author = {Tomasz S. Czajkowski and
Utku Aydonat and
Dmitry Denisenko and
John Freeman and
Michael Kinsner and
David Neto and
Jason Wong and
Peter Yiannacouras and
Deshanand P. Singh},
editor = {Dirk Koch and
Satnam Singh and
Jim T{\o}rresen},
title = {From opencl to high-performance hardware on {FPGAS}},
booktitle = {22nd International Conference on Field Programmable Logic and Applications
(FPL), Oslo, Norway, August 29-31, 2012},
pages = {531--534},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPL.2012.6339272},
doi = {10.1109/FPL.2012.6339272},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/CzajkowskiADFKNWYS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/PilatoCDOSS12,
author = {Christian Pilato and
Andrea Cazzaniga and
Gianluca Durelli and
Andr{\'{e}}s Otero and
Donatella Sciuto and
Marco D. Santambrogio},
editor = {Dirk Koch and
Satnam Singh and
Jim T{\o}rresen},
title = {On the automatic integration of hardware accelerators into FPGA-based
embedded systems},
booktitle = {22nd International Conference on Field Programmable Logic and Applications
(FPL), Oslo, Norway, August 29-31, 2012},
pages = {607--610},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPL.2012.6339218},
doi = {10.1109/FPL.2012.6339218},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/PilatoCDOSS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ZhengCP12,
author = {Jason Xin Zheng and
Ethan Chen and
Miodrag Potkonjak},
editor = {Dirk Koch and
Satnam Singh and
Jim T{\o}rresen},
title = {A Benign Hardware Trojan on FPGA-based embedded systems},
booktitle = {22nd International Conference on Field Programmable Logic and Applications
(FPL), Oslo, Norway, August 29-31, 2012},
pages = {464--470},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPL.2012.6339145},
doi = {10.1109/FPL.2012.6339145},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/ZhengCP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/BrousseauR12,
author = {Braiden Brousseau and
Jonathan Rose},
title = {An energy-efficient, fast {FPGA} hardware architecture for OpenCV-Compatible
object detection},
booktitle = {2012 International Conference on Field-Programmable Technology, {FPT}
2012, Seoul, Korea (South), December 10-12, 2012},
pages = {166--173},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPT.2012.6412130},
doi = {10.1109/FPT.2012.6412130},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/BrousseauR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/healthcom/SchwarzGPS12,
author = {Leandro Schwarz and
Humberto Remigio Gamba and
Fabio Cabral Pacheco and
Miguel Antonio Sovierzoski},
title = {Pupil detection in hardware using {FPGA}},
booktitle = {{IEEE} 14th International Conference on e-Health Networking, Applications
and Services, Healthcom 2012, Beijing, China, October 10-13, 2012},
pages = {361--364},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/HealthCom.2012.6379437},
doi = {10.1109/HEALTHCOM.2012.6379437},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/healthcom/SchwarzGPS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hoti/LockwoodGMBEV12,
author = {John W. Lockwood and
Adwait Gupte and
Nishit Mehta and
Michaela Blott and
Tom English and
Kees A. Vissers},
title = {A Low-Latency Library in {FPGA} Hardware for High-Frequency Trading
{(HFT)}},
booktitle = {{IEEE} 20th Annual Symposium on High-Performance Interconnects, {HOTI}
2012, Santa Clara, CA, USA, August 22-24, 2012},
pages = {9--16},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/HOTI.2012.15},
doi = {10.1109/HOTI.2012.15},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hoti/LockwoodGMBEV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpcc/WangFCH12,
author = {Xun Wang and
Degui Feng and
Tianzhou Chen and
Tongsen Hu},
editor = {Geyong Min and
Jia Hu and
Lei (Chris) Liu and
Laurence Tianruo Yang and
Seetharami Seelam and
Laurent Lef{\`{e}}vre},
title = {Migration between Software and Hardware Task on Preemptive Multitasking
{CPU/FPGA} Hybrid Architecture},
booktitle = {14th {IEEE} International Conference on High Performance Computing
and Communication {\&} 9th {IEEE} International Conference on
Embedded Software and Systems, {HPCC-ICESS} 2012, Liverpool, United
Kingdom, June 25-27, 2012},
pages = {1329--1336},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/HPCC.2012.196},
doi = {10.1109/HPCC.2012.196},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hpcc/WangFCH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icacci/BaskaranR12,
author = {Saambhavi Baskaran and
Pachamuthu Rajalakshmi},
editor = {Kaliappan Gopalan and
Sabu M. Thampi},
title = {Hardware-software co-design of {AES} on {FPGA}},
booktitle = {2012 International Conference on Advances in Computing, Communications
and Informatics, {ICACCI} '12, Chennai, India, August 3-5, 2012},
pages = {1118--1122},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2345396.2345575},
doi = {10.1145/2345396.2345575},
timestamp = {Sun, 29 Aug 2021 01:08:46 +0200},
biburl = {https://dblp.org/rec/conf/icacci/BaskaranR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icann/BeulerTBPB12,
author = {Marcel Beuler and
Aubin Tchaptchet and
Werner Bonath and
Svetlana Postnova and
Hans Albert Braun},
editor = {Alessandro E. P. Villa and
Wlodzislaw Duch and
P{\'{e}}ter {\'{E}}rdi and
Francesco Masulli and
G{\"{u}}nther Palm},
title = {Real-Time Simulations of Synchronization in a Conductance-Based Neuronal
Network with a Digital {FPGA} Hardware-Core},
booktitle = {Artificial Neural Networks and Machine Learning - {ICANN} 2012 - 22nd
International Conference on Artificial Neural Networks, Lausanne,
Switzerland, September 11-14, 2012, Proceedings, Part {I}},
series = {Lecture Notes in Computer Science},
volume = {7552},
pages = {97--104},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-33269-2\_13},
doi = {10.1007/978-3-642-33269-2\_13},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icann/BeulerTBPB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/BucekKLZ12,
author = {Jir{\'{\i}} Bucek and
Pavel Kubal{\'{\i}}k and
R{\'{o}}bert L{\'{o}}rencz and
Tom{\'{a}}s Zahradnick{\'{y}}},
title = {Dedicated hardware implementation of a linear congruence solver in
{FPGA}},
booktitle = {19th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2012, Seville, Spain, December 9-12, 2012},
pages = {689--692},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ICECS.2012.6463632},
doi = {10.1109/ICECS.2012.6463632},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/BucekKLZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/MahdiSKTP12,
author = {Ahmed Mahdi and
Panagiotis Sakellariou and
Nikos Kanistras and
Ioannis Tsatsaragkos and
Vassilis Paliouras},
title = {Hardware design and verification techniques for Giga-bit Forward-Error
Correction systems on FPGAs},
booktitle = {19th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2012, Seville, Spain, December 9-12, 2012},
pages = {89--92},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ICECS.2012.6463792},
doi = {10.1109/ICECS.2012.6463792},
timestamp = {Sun, 04 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/MahdiSKTP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icics/MaXLJLY12,
author = {Yuan Ma and
Luning Xia and
Jingqiang Lin and
Jiwu Jing and
Zongbin Liu and
Xingjie Yu},
editor = {Tat Wing Chim and
Tsz Hon Yuen},
title = {Hardware Performance Optimization and Evaluation of {SM3} Hash Algorithm
on {FPGA}},
booktitle = {Information and Communications Security - 14th International Conference,
{ICICS} 2012, Hong Kong, China, October 29-31, 2012. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7618},
pages = {105--118},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-34129-8\_10},
doi = {10.1007/978-3-642-34129-8\_10},
timestamp = {Thu, 31 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icics/MaXLJLY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwcmc/GroleatAV12,
author = {Tristan Groleat and
Matthieu Arzel and
Sandrine Vaton},
title = {Hardware acceleration of SVM-based traffic classification on {FPGA}},
booktitle = {8th International Wireless Communications and Mobile Computing Conference,
{IWCMC} 2012, Limassol, Cyprus, August 27-31, 2012},
pages = {443--449},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/IWCMC.2012.6314245},
doi = {10.1109/IWCMC.2012.6314245},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/iwcmc/GroleatAV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/new2an/YinLH12,
author = {Dong Yin and
Ge Li and
Kedi Huang},
editor = {Sergey D. Andreev and
Sergey I. Balandin and
Yevgeni Koucheryavy},
title = {Scalable MapReduce Framework on {FPGA} Accelerated Commodity Hardware},
booktitle = {Internet of Things, Smart Spaces, and Next Generation Networking -
12th International Conference, {NEW2AN} 2012, and 5th Conference,
ruSMART 2012, St. Petersburg, Russia, August 27-29, 2012. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7469},
pages = {280--294},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-32686-8\_26},
doi = {10.1007/978-3-642-32686-8\_26},
timestamp = {Tue, 14 May 2019 10:00:43 +0200},
biburl = {https://dblp.org/rec/conf/new2an/YinLH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nips/NiuNSS12,
author = {Chuanxin Minos Niu and
Sirish K. Nandyala and
Won Joon Sohn and
Terence D. Sanger},
editor = {Peter L. Bartlett and
Fernando C. N. Pereira and
Christopher J. C. Burges and
L{\'{e}}on Bottou and
Kilian Q. Weinberger},
title = {Multi-scale Hyper-time Hardware Emulation of Human Motor Nervous System
Based on Spiking Neurons using {FPGA}},
booktitle = {Advances in Neural Information Processing Systems 25: 26th Annual
Conference on Neural Information Processing Systems 2012. Proceedings
of a meeting held December 3-6, 2012, Lake Tahoe, Nevada, United States},
pages = {37--45},
year = {2012},
url = {https://proceedings.neurips.cc/paper/2012/hash/33e75ff09dd601bbe69f351039152189-Abstract.html},
timestamp = {Mon, 16 May 2022 15:41:51 +0200},
biburl = {https://dblp.org/rec/conf/nips/NiuNSS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/norchip/HegnerSN12,
author = {Jonas Stenbaek Hegner and
Joakim Sindholt and
Alberto Nannarelli},
title = {Design of power efficient {FPGA} based hardware accelerators for financial
applications},
booktitle = {{NORCHIP} 2012, Copenhagen, Denmark, November 12-13, 2012},
pages = {1--4},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/NORCHP.2012.6403096},
doi = {10.1109/NORCHP.2012.6403096},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/norchip/HegnerSN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdes/PopescuGB12,
author = {Silvana Oana Popescu and
Aurel Gontean and
Georgeta Budura},
editor = {Zdenek Brad{\'{a}}c and
Frantisek Zezulka},
title = {Hardware Co-simulation of the {BPSK} and {QPSK} systems on {FPGA}},
booktitle = {11th {IFAC} Conference on Programmable Devices and Embedded Systems,
PDeS 2012, Brno, Czech Republic, May 23-25, 2012},
pages = {299--304},
publisher = {International Federation of Automatic Control},
year = {2012},
url = {https://doi.org/10.3182/20120523-3-CZ-3015.00057},
doi = {10.3182/20120523-3-CZ-3015.00057},
timestamp = {Tue, 09 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/pdes/PopescuGB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/peccs/AmaricaiB12,
author = {Alexandru Amaricai and
Oana Boncalo},
editor = {C{\'{e}}sar Benavente{-}Peces and
Falah H. Ali and
Joaquim Filipe},
title = {Automatic Generation of {FPGA} Hardware Accelerators for Graphics
Applications},
booktitle = {{PECCS} 2012 - Proceedings of the 2nd International Conference on
Pervasive Embedded Computing and Communication Systems, Rome, Italy,
24-26 February, 2012},
pages = {383--386},
publisher = {SciTePress},
year = {2012},
timestamp = {Sun, 06 May 2012 14:26:10 +0200},
biburl = {https://dblp.org/rec/conf/peccs/AmaricaiB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/peccs/FischerR12,
author = {Bennet Fischer and
Ra{\'{u}}l Rojas},
editor = {C{\'{e}}sar Benavente{-}Peces and
Falah H. Ali and
Joaquim Filipe},
title = {Image Processing Framework for FPGAs - Introducing a Plug-and-play
Computer Vision Framework for Fast Integration of Algorithms in Reconfigurable
Hardware},
booktitle = {{PECCS} 2012 - Proceedings of the 2nd International Conference on
Pervasive Embedded Computing and Communication Systems, Rome, Italy,
24-26 February, 2012},
pages = {295--300},
publisher = {SciTePress},
year = {2012},
timestamp = {Mon, 23 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/peccs/FischerR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/Blume12,
author = {Holger Blume},
title = {Special session on "FPGA-based emulation of hardware architectures"},
booktitle = {2012 International Conference on Embedded Computer Systems: Architectures,
Modeling, and Simulation, {SAMOS} XII, Samos, Greece, July 16-19,
2012},
pages = {276},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/SAMOS.2012.6404185},
doi = {10.1109/SAMOS.2012.6404185},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/samos/Blume12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/BorlenghiAWKALM12,
author = {Filippo Borlenghi and
Dominik Auras and
Ernst Martin Witte and
Torsten Kempf and
Gerd Ascheid and
Rainer Leupers and
Heinrich Meyr},
title = {An FPGA-accelerated testbed for hardware component development in
{MIMO} wireless communication systems},
booktitle = {2012 International Conference on Embedded Computer Systems: Architectures,
Modeling, and Simulation, {SAMOS} XII, Samos, Greece, July 16-19,
2012},
pages = {278--285},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/SAMOS.2012.6404187},
doi = {10.1109/SAMOS.2012.6404187},
timestamp = {Thu, 25 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/samos/BorlenghiAWKALM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/secrypt/AthanasiouCBMTG12,
author = {George Athanasiou and
Chara I. Chalkou and
D. Bardis and
Harris E. Michail and
George Theodoridis and
Costas E. Goutis},
editor = {Pierangela Samarati and
Wenjing Lou and
Jianying Zhou},
title = {High-throughput Hardware Architectures of the {JH} Round-three {SHA-3}
Candidate - An {FPGA} Design and Implementation Approach},
booktitle = {{SECRYPT} 2012 - Proceedings of the International Conference on Security
and Cryptography, Rome, Italy, 24-27 July, 2012, {SECRYPT} is part
of {ICETE} - The International Joint Conference on e-Business and
Telecommunications},
pages = {126--135},
publisher = {SciTePress},
year = {2012},
timestamp = {Tue, 07 Nov 2017 12:02:58 +0100},
biburl = {https://dblp.org/rec/conf/secrypt/AthanasiouCBMTG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/LiangHPR12,
author = {Guixuan Liang and
Danping He and
Jorge Portilla and
Teresa Riesgo},
title = {A hardware in the loop design methodology for {FPGA} system and its
application to complex functions},
booktitle = {Proceedings of Technical Program of 2012 {VLSI} Design, Automation
and Test, {VLSI-DAT} 2012, Hsinchu, Taiwan, April 23-25, 2012},
pages = {1--4},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-DAT.2012.6212666},
doi = {10.1109/VLSI-DAT.2012.6212666},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/LiangHPR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/ethos/Hashmi11,
author = {Adeel Hashmi},
title = {Hardware Acceleration of Network Intrusion Detection System Using
{FPGA}},
school = {Manchester Metropolitan University, {UK}},
year = {2011},
url = {https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.526973},
timestamp = {Tue, 05 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/ethos/Hashmi11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cj/LiuCMC11,
author = {Qiang Liu and
George A. Constantinides and
Konstantinos Masselos and
Peter Y. K. Cheung},
title = {Compiling C-like Languages to {FPGA} Hardware: Some Novel Approaches
Targeting Data Memory Organization},
journal = {Comput. J.},
volume = {54},
number = {1},
pages = {1--10},
year = {2011},
url = {https://doi.org/10.1093/comjnl/bxp020},
doi = {10.1093/COMJNL/BXP020},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cj/LiuCMC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/eswa/AhmadiMASK11,
author = {Ali Ahmadi and
Hans J{\"{u}}rgen Mattausch and
Md. Anwarul Abedin and
Mahmoud Saeidi and
Tetsushi Koide},
title = {An associative memory-based learning model with an efficient hardware
implementation in {FPGA}},
journal = {Expert Syst. Appl.},
volume = {38},
number = {4},
pages = {3499--3513},
year = {2011},
url = {https://doi.org/10.1016/j.eswa.2010.08.138},
doi = {10.1016/J.ESWA.2010.08.138},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/eswa/AhmadiMASK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijnc/BoKNI11,
author = {Bo Song and
Kensuke Kawakami and
Koji Nakano and
Yasuaki Ito},
title = {An {RSA} Encryption Hardware Algorithm using a Single {DSP} Block
and a Single Block {RAM} on the {FPGA}},
journal = {Int. J. Netw. Comput.},
volume = {1},
number = {2},
pages = {277--289},
year = {2011},
url = {http://www.ijnc.org/index.php/ijnc/article/view/29},
timestamp = {Tue, 16 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijnc/BoKNI11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/HuongNK11,
author = {Giang Nguyen Huong and
Yeoul Na and
Seon Wook Kim},
title = {Applying frame layout to hardware design in {FPGA} for seamless support
of cross calls in {CPU-FPGA} coupling architecture},
journal = {Microprocess. Microsystems},
volume = {35},
number = {5},
pages = {462--472},
year = {2011},
url = {https://doi.org/10.1016/j.micpro.2011.03.005},
doi = {10.1016/J.MICPRO.2011.03.005},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/HuongNK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/LegatBN11,
author = {Uros Legat and
Anton Biasizzo and
Franc Novak},
title = {A compact {AES} core with on-line error-detection for {FPGA} applications
with modest hardware resources},
journal = {Microprocess. Microsystems},
volume = {35},
number = {4},
pages = {405--416},
year = {2011},
url = {https://doi.org/10.1016/j.micpro.2011.03.001},
doi = {10.1016/J.MICPRO.2011.03.001},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/LegatBN11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tie/LeeSLHC11,
author = {Ming{-}Huan Lee and
Kuo{-}Kai Shyu and
Po{-}Lei Lee and
Chien{-}Ming Huang and
Yun{-}Jen Chiu},
title = {Hardware Implementation of {EMD} Using {DSP} and {FPGA} for Online
Signal Processing},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {58},
number = {6},
pages = {2473--2481},
year = {2011},
url = {https://doi.org/10.1109/TIE.2010.2060454},
doi = {10.1109/TIE.2010.2060454},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tie/LeeSLHC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tie/SudhaM11,
author = {N. Sudha and
A. R. Mohan},
title = {Hardware-Efficient Image-Based Robotic Path Planning in a Dynamic
Environment and Its {FPGA} Implementation},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {58},
number = {5},
pages = {1907--1920},
year = {2011},
url = {https://doi.org/10.1109/TIE.2010.2054051},
doi = {10.1109/TIE.2010.2054051},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tie/SudhaM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BergeronPFD11,
author = {Etienne Bergeron and
Louis{-}David Perron and
Marc Feeley and
Jean{-}Pierre David},
title = {Logarithmic-Time {FPGA} Bitstream Analysis: {A} Step Towards {JIT}
Hardware Compilation},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {2},
pages = {12:1--12:27},
year = {2011},
url = {https://doi.org/10.1145/1968502.1968503},
doi = {10.1145/1968502.1968503},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BergeronPFD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/3pgcic/PereraL11,
author = {Darshika G. Perera and
Kin Fun Li},
editor = {Fatos Xhafa and
Leonard Barolli and
Joanna Kolodziej and
Samee Ullah Khan},
title = {FPGA-Based Reconfigurable Hardware for Compute Intensive Data Mining
Applications},
booktitle = {2011 International Conference on P2P, Parallel, Grid, Cloud and Internet
Computing, 3PGCIC 2011, Barcelona, Catalonia, Spain, October 26-28,
2011},
pages = {100--108},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/3PGCIC.2011.25},
doi = {10.1109/3PGCIC.2011.25},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/3pgcic/PereraL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ahs/CancareBBCS11,
author = {Fabio Cancare and
Sheetal Bhandari and
Davide B. Bartolini and
Matteo Carminati and
Marco D. Santambrogio},
editor = {David Merodio and
Tughrul Arslan and
Umeshkumar D. Patel and
Didier Keymeulen and
Khaled Benkrid and
Ahmet T. Erdogan and
Michael Newell and
Luca Fossati and
Duane Armstrong},
title = {A bird's eye view of FPGA-based Evolvable Hardware},
booktitle = {2011 {NASA/ESA} Conference on Adaptive Hardware and Systems, {AHS}
2011, San Diego, California, USA, June 6-9, 2011},
pages = {169--175},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/AHS.2011.5963932},
doi = {10.1109/AHS.2011.5963932},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/ahs/CancareBBCS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/AldhamABC11,
author = {Mark Aldham and
Jason Helge Anderson and
Stephen Dean Brown and
Andrew Canis},
editor = {Joseph R. Cavallaro and
Milos D. Ercegovac and
Frank Hannig and
Paolo Ienne and
Earl E. Swartzlander Jr. and
Alexandre F. Tenca},
title = {Low-cost hardware profiling of run-time and energy in {FPGA} embedded
processors},
booktitle = {22nd {IEEE} International Conference on Application-specific Systems,
Architectures and Processors, {ASAP} 2011, Santa Monica, CA, USA,
Sept. 11-14, 2011},
pages = {61--68},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ASAP.2011.6043237},
doi = {10.1109/ASAP.2011.6043237},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/AldhamABC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ccece/AjamiD11,
author = {Raouf Ajami and
Anh Dinh},
title = {Design a hardware network firewall on {FPGA}},
booktitle = {Proceedings of the 24th Canadian Conference on Electrical and Computer
Engineering, {CCECE} 2011, Niagara Falls, Ontario, Canada, 8-11 May,
2011},
pages = {674--678},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/CCECE.2011.6030538},
doi = {10.1109/CCECE.2011.6030538},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/ccece/AjamiD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/KermaniR11,
author = {Mehran Mozaffari Kermani and
Arash Reyhani{-}Masoleh},
title = {Reliable Hardware Architectures for the Third-Round {SHA-3} Finalist
Grostl Benchmarked on {FPGA} Platform},
booktitle = {2011 {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} and Nanotechnology Systems, {DFT} 2011, Vancouver, BC, Canada,
October 3-5, 2011},
pages = {325--331},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/DFT.2011.60},
doi = {10.1109/DFT.2011.60},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/KermaniR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/embc/MountneyOS11,
author = {John Mountney and
Iyad Obeid and
Dennis Silage},
title = {Modular particle filtering {FPGA} hardware architecture for brain
machine interfaces},
booktitle = {33rd Annual International Conference of the {IEEE} Engineering in
Medicine and Biology Society, {EMBC} 2011, Boston, MA, USA, August
30 - Sept. 3, 2011},
pages = {4617--4620},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/IEMBS.2011.6091143},
doi = {10.1109/IEMBS.2011.6091143},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/embc/MountneyOS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/embc/WangHZZ0CCZ11,
author = {Dong Wang and
Yaoyao Hao and
Xiaoping Zhu and
Ting Zhao and
Yiwen Wang and
Yaowu Chen and
Weidong Chen and
Xiaoxiang Zheng},
title = {{FPGA} implementation of hardware processing modules as coprocessors
in brain-machine interfaces},
booktitle = {33rd Annual International Conference of the {IEEE} Engineering in
Medicine and Biology Society, {EMBC} 2011, Boston, MA, USA, August
30 - Sept. 3, 2011},
pages = {4613--4616},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/IEMBS.2011.6091142},
doi = {10.1109/IEMBS.2011.6091142},
timestamp = {Tue, 31 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/embc/WangHZZ0CCZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/emeit/ShiJG11,
author = {Yunfeng Shi and
Chuan Jin and
Feng Gao},
title = {The solution of ethernet based on hardware protocol stack {W5300}
and {FPGA}},
booktitle = {International Conference on Electronic and Mechanical Engineering
and Information Technology, {EMEIT} 2011, Harbin, Heilongjiang, China,
12-14 August, 2011},
pages = {1328--1331},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/EMEIT.2011.6023339},
doi = {10.1109/EMEIT.2011.6023339},
timestamp = {Mon, 09 Aug 2021 14:53:48 +0200},
biburl = {https://dblp.org/rec/conf/emeit/ShiJG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/LegatBN11,
author = {Uros Legat and
Anton Biasizzo and
Franc Novak},
title = {{FPGA} Soft Error Recovery Mechanism with Small Hardware Overhead},
booktitle = {16th European Test Symposium, {ETS} 2011, Trondheim, Norway, May 23-27,
2011},
pages = {207},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ETS.2011.36},
doi = {10.1109/ETS.2011.36},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/LegatBN11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurocon/PohronskaK11,
author = {Maria Pohronska and
Tibor Krajcovic},
title = {{FPGA} implementation of multiple hardware watchdog timers for enhancing
real-time systems security},
booktitle = {Proceedings of {EUROCON} 2011, International Conference on Computer
as a Tool, 27-29 April 2011, Lisbon, Portugal},
pages = {1--4},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/EUROCON.2011.5929215},
doi = {10.1109/EUROCON.2011.5929215},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/eurocon/PohronskaK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LiuMHGH11,
author = {Ling Liu and
Oleksii Morozov and
Yuxing Han and
J{\"{u}}rg Gutknecht and
Patrick R. Hunziker},
editor = {John Wawrzynek and
Katherine Compton},
title = {Automatic SoC design flow on many-core processors: a software hardware
co-design approach for FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 19th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2011, Monterey, California, USA,
February 27, March 1, 2011},
pages = {37--40},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1950413.1950424},
doi = {10.1145/1950413.1950424},
timestamp = {Fri, 20 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/LiuMHGH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/IturbeBATM11,
author = {Xabier Iturbe and
Khaled Benkrid and
Tughrul Arslan and
Raul Torrego and
Imanol Martinez},
title = {Methods and Mechanisms for Hardware Multitasking: Executing and Synchronizing
Fully Relocatable Hardware Tasks in Xilinx FPGAs},
booktitle = {International Conference on Field Programmable Logic and Applications,
{FPL} 2011, September 5-7, Chania, Crete, Greece},
pages = {295--300},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/FPL.2011.60},
doi = {10.1109/FPL.2011.60},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/IturbeBATM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/MarconiM11,
author = {Thomas Marconi and
Tulika Mitra},
editor = {Russell Tessier},
title = {A novel online hardware task scheduling and placement algorithm for
3D partially reconfigurable FPGAs},
booktitle = {2011 International Conference on Field-Programmable Technology, {FPT}
2011, New Delhi, India, December 12-14, 2011},
pages = {1--6},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/FPT.2011.6132700},
doi = {10.1109/FPT.2011.6132700},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/MarconiM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gecco/BarenoBNT11,
author = {Carlos Iv{\'{a}}n Camargo Bare{\~{n}}o and
Cesar Augusto Pedraza Bonilla and
Luis Fernado Ni{\~{n}}o and
Jos{\'{e}} Ignacio Martinez Torre},
editor = {Natalio Krasnogor and
Pier Luca Lanzi},
title = {Intrinsic evolvable hardware for combinatorial synthesis based on
SoC+FPGA and {GPU} platforms},
booktitle = {13th Annual Genetic and Evolutionary Computation Conference, {GECCO}
2011, Companion Material Proceedings, Dublin, Ireland, July 12-16,
2011},
pages = {189--190},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/2001858.2001964},
doi = {10.1145/2001858.2001964},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/gecco/BarenoBNT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hvc/SimkovaLK11,
author = {Marcela Simkov{\'{a}} and
Ondrej Leng{\'{a}}l and
Michal Kajan},
editor = {Kerstin Eder and
Jo{\~{a}}o Louren{\c{c}}o and
Onn Shehory},
title = {{HAVEN:} An Open Framework for FPGA-Accelerated Functional Verification
of Hardware},
booktitle = {Hardware and Software: Verification and Testing - 7th International
Haifa Verification Conference, {HVC} 2011, Haifa, Israel, December
6-8, 2011, Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {7261},
pages = {247--253},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-34188-5\_22},
doi = {10.1007/978-3-642-34188-5\_22},
timestamp = {Fri, 27 Mar 2020 08:58:09 +0100},
biburl = {https://dblp.org/rec/conf/hvc/SimkovaLK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/RillingGHMWJZ11,
author = {Justin Rilling and
David Graziano and
Jamin Hitchcock and
Tim Meyer and
Xinying Wang and
Phillip H. Jones and
Joseph Zambreno},
title = {Circumventing a ring oscillator approach to FPGA-based hardware Trojan
detection},
booktitle = {{IEEE} 29th International Conference on Computer Design, {ICCD} 2011,
Amherst, MA, USA, October 9-12, 2011},
pages = {289--292},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ICCD.2011.6081411},
doi = {10.1109/ICCD.2011.6081411},
timestamp = {Wed, 31 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/RillingGHMWJZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icdsp/AbbaszadehAD11,
author = {Asgar Abbaszadeh and
Anasystem Azerbaijan and
Khosrov Dabbagh{-}Sadeghipour},
title = {A new hardware efficient reconfigurable fir filter architecture suitable
for {FPGA} applications},
booktitle = {17th International Conference on Digital Signal Processing, {DSP}
2011, Corfu, Greece, July 6-8, 2011},
pages = {1--4},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ICDSP.2011.6004958},
doi = {10.1109/ICDSP.2011.6004958},
timestamp = {Thu, 04 Feb 2021 10:37:05 +0100},
biburl = {https://dblp.org/rec/conf/icdsp/AbbaszadehAD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/PossaSV11,
author = {Paulo Da Cunha Possa and
David Schaillie and
Carlos Valderrama},
title = {FPGA-based hardware acceleration: {A} CPU/accelerator interface exploration},
booktitle = {18th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2011, Beirut, Lebanon, December 11-14, 2011},
pages = {374--377},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ICECS.2011.6122291},
doi = {10.1109/ICECS.2011.6122291},
timestamp = {Sun, 03 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/PossaSV11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icumt/GomesMP11a,
author = {Otavio de Souza Martins Gomes and
Robson L. Moreno and
Tales Cleber Pimenta},
title = {A fast cryptography pipelined hardware developed in {FPGA} with {VHDL}},
booktitle = {3rd International Congress on Ultra Modern Telecommunications and
Control Systems and Workshops, {ICUMT} 2011, Budapest, Hungary, October
5-7, 2011},
pages = {1--6},
publisher = {{IEEE}},
year = {2011},
url = {https://ieeexplore.ieee.org/document/6078888/},
timestamp = {Fri, 11 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icumt/GomesMP11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/JozwikTEHT11,
author = {Krzysztof Jozwik and
Hiroyuki Tomiyama and
Masato Edahiro and
Shinya Honda and
Hiroaki Takada},
title = {Hardware multitasking in dynamically partially reconfigurable FPGA-based
embedded systems},
booktitle = {International SoC Design Conference, {ISOCC} 2011, Jeju, South Korea,
November 17-18, 2011},
pages = {183--186},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISOCC.2011.6138678},
doi = {10.1109/ISOCC.2011.6138678},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isocc/JozwikTEHT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispacs/YamamotoORH11,
author = {Kota Yamamoto and
Yoshiro Oba and
Zuiko Rikuhashi and
Hiroomi Hikawa},
title = {Automatic generation of hardware self-organizing map for {FPGA} implementation},
booktitle = {International Symposium on Intelligent Signal Processing and Communications
Systems, {ISPACS} 2011, Chiang Mai, Thailand, December 7-9, 2011},
pages = {1--6},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISPACS.2011.6146080},
doi = {10.1109/ISPACS.2011.6146080},
timestamp = {Wed, 16 Oct 2019 14:14:51 +0200},
biburl = {https://dblp.org/rec/conf/ispacs/YamamotoORH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/KubaM11,
author = {Matthias Kuba and
Zekeriya Mansuroglu},
editor = {Frank Oppenheimer},
title = {Untersuchung von Methoden zur Hardwarebeschleunigung eines FPGA-basierten
Java-Systems mit Soft-IP Prozessor},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Oldenburg, Germany, February
21-23, 2011},
pages = {155--162},
publisher = {OFFIS-Institut f{\"{u}}r Informatik},
year = {2011},
timestamp = {Wed, 27 Jun 2012 22:40:36 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/KubaM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memics/SakellariouB11,
author = {Christos Sakellariou and
Peter J. Bentley},
editor = {Zdenek Kot{\'{a}}sek and
Jan Bouda and
Ivana Cern{\'{a}} and
Luk{\'{a}}s Sekanina and
Tom{\'{a}}s Vojnar and
David Antos},
title = {Introducing the FPGA-Based Hardware Architecture of Systemic Computation
(HAoS)},
booktitle = {Mathematical and Engineering Methods in Computer Science - 7th International
Doctoral Workshop, {MEMICS} 2011, Lednice, Czech Republic, October
14-16, 2011, Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {7119},
pages = {179--190},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-25929-6\_17},
doi = {10.1007/978-3-642-25929-6\_17},
timestamp = {Tue, 14 May 2019 10:00:46 +0200},
biburl = {https://dblp.org/rec/conf/memics/SakellariouB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mse/Wang11,
author = {Xiaofang (Maggie) Wang},
title = {Using FPGA-based configurable processors in teaching hardware/software
co-design of embedded multiprocessor systems},
booktitle = {2011 {IEEE} International Conference on Microelectronic Systems Education,
{MSE} 2011, San Diego, CA, USA, June 5-6, 2011},
pages = {114--117},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/MSE.2011.5937108},
doi = {10.1109/MSE.2011.5937108},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mse/Wang11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/networking/PloszMKT11,
author = {S{\'{a}}ndor Pl{\'{o}}sz and
Istv{\'{a}}n Moldov{\'{a}}n and
L{\'{a}}szl{\'{o}} K{\'{a}}ntor and
Tuan Anh Trinh},
editor = {Vicente Casares Giner and
Pietro Manzoni and
Ana Pont},
title = {Characterization of Power-Aware Reconfiguration in FPGA-Based Networking
Hardware},
booktitle = {{NETWORKING} 2011 Workshops - International {IFIP} {TC} 6 Workshops,
PE-CRN, NC-Pro, WCNS, and {SUNSET} 2011, Held at {NETWORKING} 2011,
Valencia, Spain, May 13, 2011, Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {6827},
pages = {281--290},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-23041-7\_27},
doi = {10.1007/978-3-642-23041-7\_27},
timestamp = {Mon, 16 Sep 2019 15:26:11 +0200},
biburl = {https://dblp.org/rec/conf/networking/PloszMKT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/norchip/BorupDN11,
author = {Nicolas Borup and
Jonas Dindorp and
Alberto Nannarelli},
title = {{FPGA} implementation of decimal processors for hardware acceleration},
booktitle = {2011 NORCHIP, Lund, Sweden, November 14-15, 2011},
pages = {1--4},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/NORCHP.2011.6126729},
doi = {10.1109/NORCHP.2011.6126729},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/norchip/BorupDN11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/paap/ChuongALSL11,
author = {Lieu My Chuong and
Yan Lin Aung and
Siew Kei Lam and
Thambipillai Srikanthan and
Chai{-}Soon Lim},
editor = {Jigang Wu and
Guozhi Song and
Hong Shen and
Guoliang Chen},
title = {Automatic Compilation of {C} Applications for FPGA-Based Hardware
Acceleration},
booktitle = {Fourth International Symposium on Parallel Architectures, Algorithms
and Programming, {PAAP} 2011, Tianjin, China, December 9-11, 2011},
pages = {223--227},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/PAAP.2011.70},
doi = {10.1109/PAAP.2011.70},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/paap/ChuongALSL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/peccs/OuniBMM11,
author = {Bassem Ouni and
Ikbel Belaid and
Fabrice Muller and
Maher Benjemaa},
editor = {C{\'{e}}sar Benavente{-}Peces and
Joaquim Filipe},
title = {Placement of Hardware Tasks on {FPGA} using the Bees Algorithm},
booktitle = {{PECCS} 2011 - Proceedings of the 1st International Conference on
Pervasive and Embedded Computing and Communication Systems, Vilamoura,
Algarve, Portugal, 5-7 March, 2011},
pages = {498--505},
publisher = {SciTePress},
year = {2011},
timestamp = {Wed, 28 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/peccs/OuniBMM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pqcrypto/TangYDCC11,
author = {Shaohua Tang and
Haibo Yi and
Jintai Ding and
Huan Chen and
Guomin Chen},
editor = {Bo{-}Yin Yang},
title = {High-Speed Hardware Implementation of Rainbow Signature on FPGAs},
booktitle = {Post-Quantum Cryptography - 4th International Workshop, PQCrypto 2011,
Taipei, Taiwan, November 29 - December 2, 2011. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7071},
pages = {228--243},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-25405-5\_15},
doi = {10.1007/978-3-642-25405-5\_15},
timestamp = {Tue, 14 May 2019 10:00:42 +0200},
biburl = {https://dblp.org/rec/conf/pqcrypto/TangYDCC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/IturbeBAHM11,
author = {Xabier Iturbe and
Khaled Benkrid and
Tughrul Arslan and
Chuan Hong and
Imanol Martinez},
editor = {Peter M. Athanas and
J{\"{u}}rgen Becker and
Ren{\'{e}} Cumplido},
title = {Empty Resource Compaction Algorithms for Real-Time Hardware Tasks
Placement on Partially Reconfigurable FPGAs Subject to Fault Ocurrence},
booktitle = {2011 International Conference on Reconfigurable Computing and FPGAs,
ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011},
pages = {27--34},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ReConFig.2011.34},
doi = {10.1109/RECONFIG.2011.34},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/reconfig/IturbeBAHM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/JozwikTEHT11,
author = {Krzysztof Jozwik and
Hiroyuki Tomiyama and
Masato Edahiro and
Shinya Honda and
Hiroaki Takada},
editor = {Peter M. Athanas and
J{\"{u}}rgen Becker and
Ren{\'{e}} Cumplido},
title = {Rainbow: An {OS} Extension for Hardware Multitasking on Dynamically
Partially Reconfigurable FPGAs},
booktitle = {2011 International Conference on Reconfigurable Computing and FPGAs,
ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011},
pages = {416--421},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ReConFig.2011.73},
doi = {10.1109/RECONFIG.2011.73},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/reconfig/JozwikTEHT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/SalmanRK11,
author = {Ahmad Salman and
Marcin Rogawski and
Jens{-}Peter Kaps},
editor = {Peter M. Athanas and
J{\"{u}}rgen Becker and
Ren{\'{e}} Cumplido},
title = {Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration
on Xilinx FPGAs},
booktitle = {2011 International Conference on Reconfigurable Computing and FPGAs,
ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011},
pages = {242--248},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ReConFig.2011.33},
doi = {10.1109/RECONFIG.2011.33},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/reconfig/SalmanRK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/SchmidtS11,
author = {Andrew G. Schmidt and
Ron Sass},
editor = {Peter M. Athanas and
J{\"{u}}rgen Becker and
Ren{\'{e}} Cumplido},
title = {Improving {FPGA} Design and Evaluation Productivity with a Hardware
Performance Monitoring Infrastructure},
booktitle = {2011 International Conference on Reconfigurable Computing and FPGAs,
ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011},
pages = {422--427},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ReConFig.2011.53},
doi = {10.1109/RECONFIG.2011.53},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/reconfig/SchmidtS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/retis/BasuRDS11,
author = {Abhishek Basu and
Abhik Roy and
Tirtha Shankar Das and
Subir Kumar Sarkar},
editor = {Mita Nasipuri and
Sarmistha Neogy and
Jamuna Kanta Sing and
Amit Konar and
Ujjwal Maulik and
Subhadip Basu and
Debasish Jana},
title = {On the implementation of {QIM} {FPGA} hardware},
booktitle = {International Conference on Recent Trends in Information Systems,
ReTIS 2011, December 21-23, 2011, Jadavpur University, Kolkata, India,
Proceedings},
pages = {287--292},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ReTIS.2011.6146883},
doi = {10.1109/RETIS.2011.6146883},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/retis/BasuRDS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iacr/TangYCCD11,
title = {High-speed Hardware Implementation of Rainbow Signatures on FPGAs},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {155},
year = {2011},
note = {Withdrawn.},
url = {http://eprint.iacr.org/2011/155},
timestamp = {Mon, 11 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iacr/TangYCCD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/ethos/McKechnie10,
author = {Paul Edward McKechnie},
title = {Validation and verification of the interconnection of hardware intellectual
property blocks for FPGA-based packet processing systems},
school = {University of Glasgow, {UK}},
year = {2010},
url = {http://theses.gla.ac.uk/1879/},
timestamp = {Tue, 05 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/ethos/McKechnie10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijmssc/KhoaPBN10,
author = {Dang Le Khoa and
Nguyen Huu Phuong and
Le Nguyen Binh and
Duc Nhan Nguyen},
title = {Simulink Model and FPGA-based {OFDM} Communication System: a simulation
and Hardware Integrated Platform},
journal = {Int. J. Model. Simul. Sci. Comput.},
volume = {1},
number = {3},
year = {2010},
url = {https://doi.org/10.1142/S1793962310000250},
doi = {10.1142/S1793962310000250},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijmssc/KhoaPBN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijns/JohnstonPMM10,
author = {Simon Johnston and
Girijesh Prasad and
Liam P. Maguire and
T. Martin McGinnity},
title = {An {FPGA} Hardware/Software Co-Design towards Evolvable Spiking Neural
Networks for Robotics Application},
journal = {Int. J. Neural Syst.},
volume = {20},
number = {6},
pages = {447--461},
year = {2010},
url = {https://doi.org/10.1142/S0129065710002541},
doi = {10.1142/S0129065710002541},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijns/JohnstonPMM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijrc/BelaidMM10,
author = {Ikbel Belaid and
Fabrice Muller and
Maher Benjemaa},
title = {New Three-Level Resource Management Enhancing Quality of Offline Hardware
Task Placement on {FPGA}},
journal = {Int. J. Reconfigurable Comput.},
volume = {2010},
pages = {980762:1--980762:20},
year = {2010},
url = {https://doi.org/10.1155/2010/980762},
doi = {10.1155/2010/980762},
timestamp = {Wed, 28 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijrc/BelaidMM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jbcb/XiaDL10,
author = {Fei Xia and
Yong Dou and
Guo{-}Qing Lei},
title = {Fpqrna: Hardware-Accelerated Qrna Package for noncoding {RNA} Gene
Detecting on {FPGA}},
journal = {J. Bioinform. Comput. Biol.},
volume = {8},
number = {4},
pages = {743--761},
year = {2010},
url = {https://doi.org/10.1142/S0219720010004902},
doi = {10.1142/S0219720010004902},
timestamp = {Thu, 04 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jbcb/XiaDL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mva/JinCKJ10,
author = {Seunghun Jin and
Jung Uk Cho and
Key Ho Kwon and
Jae Wook Jeon},
title = {A dedicated hardware architecture for real-time auto-focusing using
an {FPGA}},
journal = {Mach. Vis. Appl.},
volume = {21},
number = {5},
pages = {727--734},
year = {2010},
url = {https://doi.org/10.1007/s00138-009-0190-2},
doi = {10.1007/S00138-009-0190-2},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mva/JinCKJ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/YuanGHLJ10,
author = {Mingxuan Yuan and
Zonghua Gu and
Xiuqiang He and
Xue Liu and
Lei Jiang},
title = {Hardware/software partitioning and pipelined scheduling on runtime
reconfigurable FPGAs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {15},
number = {2},
pages = {13:1--13:41},
year = {2010},
url = {https://doi.org/10.1145/1698759.1698763},
doi = {10.1145/1698759.1698763},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/YuanGHLJ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/DerrienQ10,
author = {Steven Derrien and
Patrice Quinton},
title = {Hardware Acceleration of {HMMER} on FPGAs},
journal = {J. Signal Process. Syst.},
volume = {58},
number = {1},
pages = {53--67},
year = {2010},
url = {https://doi.org/10.1007/s11265-008-0262-y},
doi = {10.1007/S11265-008-0262-Y},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/DerrienQ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ches/GajHR10,
author = {Kris Gaj and
Ekawat Homsirikamol and
Marcin Rogawski},
editor = {Stefan Mangard and
Fran{\c{c}}ois{-}Xavier Standaert},
title = {Fair and Comprehensive Methodology for Comparing Hardware Performance
of Fourteen Round Two {SHA-3} Candidates Using FPGAs},
booktitle = {Cryptographic Hardware and Embedded Systems, {CHES} 2010, 12th International
Workshop, Santa Barbara, CA, USA, August 17-20, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {6225},
pages = {264--278},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-15031-9\_18},
doi = {10.1007/978-3-642-15031-9\_18},
timestamp = {Tue, 14 May 2019 10:00:47 +0200},
biburl = {https://dblp.org/rec/conf/ches/GajHR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csndsp/NumanIM10,
author = {Mostafa Wasiuddin Numan and
Mohammad Tariqul Islam and
Norbahiah Misran},
editor = {Zabih Ghassemlooy and
Wai Pang Ng},
title = {An efficient FPGA-based hardware implementation of {MIMO} wireless
systems},
booktitle = {Proceedings of the 7th International Symposium on Communication Systems
Networks and Digital Signal Processing, {CSNDSP} 2010, University
of Northumbria at Newcastle, UK, 21-23 July 2010},
pages = {152--156},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/CSNDSP16145.2010.5580442},
doi = {10.1109/CSNDSP16145.2010.5580442},
timestamp = {Thu, 12 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/csndsp/NumanIM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csreaESA/HannaH10,
author = {Darrin M. Hanna and
Richard E. Haskell},
editor = {Hamid R. Arabnia and
Ashu M. G. Solo},
title = {FPGA-based Hybrid Systems in Forth: a Forth Core and Reconfigurable
Hardware from Forth},
booktitle = {Proceedings of the 2010 International Conference on Embedded Systems
{\&} Applications, {ESA} 2010, July 12-15, 2010, Las Vegas Nevada,
{USA}},
pages = {168--171},
publisher = {{CSREA} Press},
year = {2010},
timestamp = {Wed, 08 Dec 2010 07:49:29 +0100},
biburl = {https://dblp.org/rec/conf/csreaESA/HannaH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HadjitheophanousTGT10,
author = {Stavros Hadjitheophanous and
Christos Ttofis and
Athinodoros S. Georghiades and
Theocharis Theocharides},
editor = {Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller and
Enrico Macii},
title = {Towards hardware stereoscopic 3D reconstruction a real-time {FPGA}
computation of the disparity map},
booktitle = {Design, Automation and Test in Europe, {DATE} 2010, Dresden, Germany,
March 8-12, 2010},
pages = {1743--1748},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DATE.2010.5457096},
doi = {10.1109/DATE.2010.5457096},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/HadjitheophanousTGT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dcc/SanoKY10,
author = {Kentaro Sano and
Kazuya Katahira and
Satoru Yamamoto},
editor = {James A. Storer and
Michael W. Marcellin},
title = {Segment-Parallel Predictor for FPGA-Based Hardware Compressor and
Decompressor of Floating-Point Data Streams to Enhance Memory {I/O}
Bandwidth},
booktitle = {2010 Data Compression Conference {(DCC} 2010), 24-26 March 2010, Snowbird,
UT, {USA}},
pages = {416--425},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DCC.2010.44},
doi = {10.1109/DCC.2010.44},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dcc/SanoKY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/KloubHD10,
author = {Jan Kloub and
Petr Honz{\'{\i}}k and
Martin Danek},
editor = {Elena Gramatov{\'{a}} and
Zdenek Kot{\'{a}}sek and
Andreas Steininger and
Heinrich Theodor Vierhaus and
Horst Zimmermann},
title = {Reconfigurable hardware objects for image processing on FPGAs},
booktitle = {13th {IEEE} International Symposium on Design and Diagnostics of Electronic
Circuits and Systems, {DDECS} 2010, Vienna, Austria, April 14-16,
2010},
pages = {121--122},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DDECS.2010.5491805},
doi = {10.1109/DDECS.2010.5491805},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/KloubHD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/MorenoLS10,
author = {F{\'{e}}lix Moreno and
Ignacio L{\'{o}}pez and
Ricardo Sanz},
editor = {Sebasti{\'{a}}n L{\'{o}}pez},
title = {A Design Process for Hardware/Software System Co-design and its Application
to Designing a Reconfigurable {FPGA}},
booktitle = {13th Euromicro Conference on Digital System Design, Architectures,
Methods and Tools, {DSD} 2010, 1-3 September 2010, Lille, France},
pages = {556--562},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DSD.2010.43},
doi = {10.1109/DSD.2010.43},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/MorenoLS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/JinKNJ10,
author = {Seunghun Jin and
Dongkyun Kim and
Duc Dung Nguyen and
Jae Wook Jeon},
editor = {Ron Sass and
Russell Tessier},
title = {Pipelined Hardware Architecture for High-Speed Optical Flow Estimation
Using {FPGA}},
booktitle = {18th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2010, Charlotte, North Carolina, USA, 2-4
May 2010},
pages = {33--36},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/FCCM.2010.14},
doi = {10.1109/FCCM.2010.14},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/JinKNJ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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