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@article{DBLP:journals/access/MahmoudSLHS24,
author = {Dina G. Mahmoud and
Beatrice Shokry and
Vincent Lenders and
Wei Hu and
Mirjana Stojilovic},
title = {X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don't-Care
Hardware Trojans to Shared Cloud FPGAs},
journal = {{IEEE} Access},
volume = {12},
pages = {8983--9011},
year = {2024}
}
@article{DBLP:journals/access/SaglamB24,
author = {Serkan Saglam and
Salih Bayar},
title = {Hardware Design of Lightweight Binary Classification Algorithms for
Small-Size Images on {FPGA}},
journal = {{IEEE} Access},
volume = {12},
pages = {57225--57235},
year = {2024}
}
@article{DBLP:journals/concurrency/ShangZZLQL24,
author = {Jiangwei Shang and
Zhan Zhang and
Kun Zhang and
Chuanyou Li and
Lei Qian and
Hong{-}Wei Liu},
title = {An algorithm/hardware co-optimized method to accelerate CNNs with
compressed convolutional weights on {FPGA}},
journal = {Concurr. Comput. Pract. Exp.},
volume = {36},
number = {11},
year = {2024}
}
@article{DBLP:journals/ijpp/OttavianoBBVCRBB24,
author = {Alessandro Ottaviano and
Robert Balas and
Giovanni Bambini and
Antonio del Vecchio and
Maicol Ciani and
Davide Rossi and
Luca Benini and
Andrea Bartolini},
title = {ControlPULP: {A} {RISC-V} On-Chip Parallel Power Controller for Many-Core
{HPC} Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal
Emulation},
journal = {Int. J. Parallel Program.},
volume = {52},
number = {1},
pages = {93--123},
year = {2024}
}
@article{DBLP:journals/jrtip/HoshinoSRD24,
author = {Yukinobu Hoshino and
Masahiro Shimasaki and
Namal Rathnayake and
Tuan Linh Dang},
title = {Performance verification and latency time evaluation of hardware image
processing module for appearance inspection systems using {FPGA}},
journal = {J. Real Time Image Process.},
volume = {21},
number = {1},
pages = {20},
year = {2024}
}
@article{DBLP:journals/mam/MartinsVSBZ24,
author = {Lucas Amilton Martins and
Felipe Viel and
Laio Oriel Seman and
Eduardo Augusto Bezerra and
C{\'{e}}sar Albenes Zeferino},
title = {A real-time SVM-based hardware accelerator for hyperspectral images
classification in {FPGA}},
journal = {Microprocess. Microsystems},
volume = {104},
pages = {104998},
year = {2024}
}
@article{DBLP:journals/remotesensing/ZhengZHX24,
author = {Shujian Zheng and
Chudi Zhang and
Jun Hu and
Shiyou Xu},
title = {Radar-Jamming Decision-Making Based on Improved Q-Learning and {FPGA}
Hardware Implementation},
journal = {Remote. Sens.},
volume = {16},
number = {7},
pages = {1190},
year = {2024}
}
@article{DBLP:journals/tcad/KaurCKA24,
author = {Jasmin Kaur and
Alvaro Cintas Canto and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {Hardware Constructions for Error Detection in {WG-29} Stream Cipher
Benchmarked on {FPGA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {43},
number = {4},
pages = {1307--1311},
year = {2024}
}
@article{DBLP:journals/tim/FalahatiSA24,
author = {Ali Falahati and
Mahdieh Shamirzaee and
Bijan Alizadeh},
title = {An FPGA-Based Hardware Architecture for {P} + {M} Class {PMU} Using
Accuracy-Aware O-Spline Filter Selection and Modulation Detection},
journal = {{IEEE} Trans. Instrum. Meas.},
volume = {73},
pages = {1--8},
year = {2024}
}
@article{DBLP:journals/trets/AnupreethamIHBKMNBCS24,
author = {Anupreetham Anupreetham and
Mohamed Ibrahim and
Mathew Hall and
Andrew Boutros and
Ajay Kuzhively and
Abinash Mohanty and
Eriko Nurvitadhi and
Vaughn Betz and
Yu Cao and
Jae{-}Sun Seo},
title = {High Throughput FPGA-Based Object Detection via Algorithm-Hardware
Co-Design},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {1:1--1:20},
year = {2024}
}
@article{DBLP:journals/trets/KalomirosVV24,
author = {John A. Kalomiros and
John V. Vourvoulakis and
Stavros Vologiannidis},
title = {A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm:
An Efficient Implementation for the Stratix {V} and Zynq UltraScale+
{FPGA} Technology},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {5:1--5:25},
year = {2024}
}
@article{DBLP:journals/trets/LiuLYC24,
author = {Zhengyan Liu and
Qiang Liu and
Shun Yan and
Ray C. C. Cheung},
title = {An Efficient FPGA-based Depthwise Separable Convolutional Neural Network
Accelerator with Hardware Pruning},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {15:1--15:20},
year = {2024}
}
@article{DBLP:journals/vlsisp/YuanVO24,
author = {Yu Yuan and
Kushal Virupakshappa and
Erdal Oruklu},
title = {Accelerating a Meta Learning Model for Ultrasonic Non-Destructive
Testing Applications Using Model Compression and {FPGA} Hardware},
journal = {J. Signal Process. Syst.},
volume = {96},
number = {1},
pages = {15--29},
year = {2024}
}
@inproceedings{DBLP:conf/arc/MpakosTAMMTGPK24,
author = {Panagiotis Mpakos and
Ioanna Tasou and
Chloe Alverti and
Panagiotis Miliadis and
Pavlos Malakonakis and
Dimitris Theodoropoulos and
Georgios I. Goumas and
Dionisios N. Pnevmatikatos and
Nectarios Koziris},
title = {Open-Source SpMV Multiplication Hardware Accelerator for FPGA-Based
{HPC} Systems},
booktitle = {{ARC}},
series = {Lecture Notes in Computer Science},
volume = {14553},
pages = {19--32},
publisher = {Springer},
year = {2024}
}
@inproceedings{DBLP:conf/fpga/AhmedB24,
author = {Muhammed Kawser Ahmed and
Christophe Bobda},
title = {{ISO-TENANT:} Rethinking {FPGA} Power Distribution Network {(PDN):}
{A} Hardware Based Solution for Remote Power Side Channel Attacks
in {FPGA}},
booktitle = {{FPGA}},
pages = {42},
publisher = {{ACM}},
year = {2024}
}
@inproceedings{DBLP:conf/fpga/PougetPC24,
author = {St{\'{e}}phane Pouget and
Louis{-}No{\"{e}}l Pouchet and
Jason Cong},
title = {Automatic Hardware Pragma Insertion in High-Level Synthesis: {A} Non-Linear
Programming Approach},
booktitle = {{FPGA}},
pages = {184},
publisher = {{ACM}},
year = {2024}
}
@inproceedings{DBLP:conf/fpga/RayDQY24a,
author = {Andy Ray and
Benjamin Devlin and
Fu Yong Quah and
Rahul Yesantharao},
title = {Hardcaml: An OCaml Hardware Domain-Specific Language for Efficient
and Robust Design},
booktitle = {{FPGA}},
pages = {41},
publisher = {{ACM}},
year = {2024}
}
@inproceedings{DBLP:conf/fpga/XiaoLZ024,
author = {Youwei Xiao and
Zizhang Luo and
Kexing Zhou and
Yun Liang},
title = {Cement: Streamlining {FPGA} Hardware Design with Cycle-Deterministic
eHDL and Synthesis},
booktitle = {{FPGA}},
pages = {211--222},
publisher = {{ACM}},
year = {2024}
}
@inproceedings{DBLP:conf/icissp/RibesMGP24,
author = {Stefano Ribes and
Fabio Malatesta and
Grazia Garzo and
Alessandro Palumbo},
title = {Machine Learning-Based Classification of Hardware Trojans in FPGAs
Implementing {RISC-V} Cores},
booktitle = {{ICISSP}},
pages = {717--724},
publisher = {{SCITEPRESS}},
year = {2024}
}
@inproceedings{DBLP:conf/vlsid/MandalR24,
author = {Suraj Mandal and
Debapriya Basu Roy},
title = {KiD: {A} Hardware Design Framework Targeting Unified {NTT} Multiplication
for CRYSTALS-Kyber and CRYSTALS-Dilithium on {FPGA}},
booktitle = {{VLSID}},
pages = {455--460},
publisher = {{IEEE}},
year = {2024}
}
@article{DBLP:journals/corr/abs-2404-03714,
author = {Dario Padovano and
Alessio Carpegna and
Alessandro Savino and
Stefano Di Carlo},
title = {SpikeExplorer: hardware-oriented Design Space Exploration for Spiking
Neural Networks on {FPGA}},
journal = {CoRR},
volume = {abs/2404.03714},
year = {2024}
}
@book{DBLP:books/sp/Snider23,
author = {Ross Snider},
title = {Advanced Digital System Design using SoC FPGAs - An Integrated Hardware/Software
Approach},
publisher = {Springer},
year = {2023}
}
@article{DBLP:journals/access/LiG23b,
author = {Tengfei Li and
Shenshen Gu},
title = {{FPGA} Hardware Implementation of Efficient Long Short-Term Memory
Network Based on Construction Vector Method},
journal = {{IEEE} Access},
volume = {11},
pages = {122357--122367},
year = {2023}
}
@article{DBLP:journals/access/MadsenP23,
author = {Anne K. Madsen and
Darshika G. Perera},
title = {Toward Composing Efficient FPGA-Based Hardware Accelerators for Physics-Based
Model Predictive Control Smart Sensor for {HEV} Battery Cell Management},
journal = {{IEEE} Access},
volume = {11},
pages = {106141--106171},
year = {2023}
}
@article{DBLP:journals/access/MatteoGS23,
author = {Stefano Di Matteo and
Matteo Lo Gerfo and
Sergio Saponara},
title = {{VLSI} Design and {FPGA} Implementation of an {NTT} Hardware Accelerator
for Homomorphic SEAL-Embedded Library},
journal = {{IEEE} Access},
volume = {11},
pages = {72498--72508},
year = {2023}
}
@article{DBLP:journals/access/TsaiHC23,
author = {Tsung{-}Han Tsai and
Yuan{-}Chen Ho and
Po{-}Ting Chi},
title = {Hardware Architecture Design for Hand Gesture Recognition System on
{FPGA}},
journal = {{IEEE} Access},
volume = {11},
pages = {51767--51776},
year = {2023}
}
@article{DBLP:journals/access/ZhaoDDZZQ23,
author = {Fuhai Zhao and
Jiang Du and
Yunkai Deng and
Jialin Zheng and
Yangbin Zeng and
Chunhui Qu},
title = {An Adaptive Word-Length Selection Method to Optimize Hardware Resources
for FPGA-Based Real-Time Simulation of Power Converters},
journal = {{IEEE} Access},
volume = {11},
pages = {122980--122990},
year = {2023}
}
@article{DBLP:journals/cea/GuptaK23,
author = {Namit Gupta and
Adesh Kumar},
title = {Study on the wireless sensor networks routing for Low-Power {FPGA}
hardware in field applications},
journal = {Comput. Electron. Agric.},
volume = {212},
pages = {108145},
year = {2023}
}
@article{DBLP:journals/computation/SiderisD23,
author = {Argyrios Sideris and
Minas Dasygenis},
title = {Enhancing the Hardware Pipelining Optimization Technique of the {SHA-3}
via {FPGA}},
journal = {Comput.},
volume = {11},
number = {8},
pages = {152},
year = {2023}
}
@article{DBLP:journals/esl/LaraNinoDM23,
author = {Carlos Andres Lara{-}Nino and
Arturo Diaz{-}Perez and
Miguel Morales{-}Sandoval},
title = {Hardware Acceleration of {SIKE} on Low-End FPGAs},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {15},
number = {2},
pages = {73--76},
year = {2023}
}
@article{DBLP:journals/ewc/AsghariH0R023,
author = {Mohsen Asghari and
Amir Hosein Hadian{-}Rasanan and
Saeid Gorgin and
Dara Rahmati and
K. Parand},
title = {FPGA-orthopoly: a hardware implementation of orthogonal polynomials},
journal = {Eng. Comput.},
volume = {39},
number = {3},
pages = {2257--2276},
year = {2023}
}
@article{DBLP:journals/fgcs/SotoHF23,
author = {Javier E. Soto and
Cecilia Hern{\'{a}}ndez and
Miguel E. Figueroa},
title = {{JACC-FPGA:} {A} hardware accelerator for Jaccard similarity estimation
using FPGAs in the cloud},
journal = {Future Gener. Comput. Syst.},
volume = {138},
pages = {26--42},
year = {2023}
}
@article{DBLP:journals/icl/AlmeidaPDOC23,
author = {Lu{\'{\i}}s Filipe Almeida and
Samuel Santos Pereira and
Jos{\'{e}} D. Domingues and
Arnaldo S. R. Oliveira and
Nuno Borges Carvalho},
title = {Moving {NFV} Toward the Antenna Through FPGA-Based Hardware Reconfiguration},
journal = {{IEEE} Commun. Lett.},
volume = {27},
number = {1},
pages = {342--346},
year = {2023}
}
@article{DBLP:journals/ieicetd/TiempoJ23a,
author = {Ann Jelyn Tiempo and
Yong{-}Jin Jeong},
title = {Implementing Region-Based Segmentation for Hardware Trojan Detection
in FPGAs Cell-Level Netlist},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {106},
number = {11},
pages = {1926--1929},
year = {2023}
}
@article{DBLP:journals/ijcat/VaidyanathanSCMKMSS23,
author = {Sundarapandian Vaidyanathan and
Aceng Sambas and
Daniel Clemente{-}L{\'{o}}pez and
Jes{\'{u}}s M. Mu{\~{n}}oz{-}Pacheco and
Alain Soup Tewa Kammogne and
Vannick Fopa Mawamba and
Martin Siewe Siewe and
Samy Abdelwahab Safaan},
title = {Electronic circuit design and FPGA-based hardware implementation of
a new multistable 4-D hyperchaotic four-leaf system},
journal = {Int. J. Comput. Appl. Technol.},
volume = {72},
number = {1},
pages = {13--28},
year = {2023}
}
@article{DBLP:journals/ijon/RanZDCZ23,
author = {Shaolin Ran and
Beizhen Zhao and
Xing Dai and
Cheng Cheng and
Yong Zhang},
title = {Software-hardware co-design for accelerating large-scale graph convolutional
network inference on {FPGA}},
journal = {Neurocomputing},
volume = {532},
pages = {129--140},
year = {2023}
}
@article{DBLP:journals/information/SiderisSD23,
author = {Argyrios Sideris and
Theodora Sanida and
Minas Dasygenis},
title = {A Novel Hardware Architecture for Enhancing the Keccak Hash Function
in {FPGA} Devices},
journal = {Inf.},
volume = {14},
number = {9},
pages = {475},
year = {2023}
}
@article{DBLP:journals/jaihc/GafsiHMM23,
author = {Mohamed Gafsi and
Mohamed Ali Hajjaji and
Jihene Malek and
Abdellatif Mtibaa},
title = {{FPGA} hardware acceleration of an improved chaos-based cryptosystem
for real-time image encryption and decryption},
journal = {J. Ambient Intell. Humaniz. Comput.},
volume = {14},
number = {6},
pages = {7001--7022},
year = {2023}
}
@article{DBLP:journals/mam/MarchisioTRS23,
author = {Alberto Marchisio and
Federico Teodonio and
Antonello Rizzi and
Muhammad Shafique},
title = {ISMatch: {A} real-time hardware accelerator for inexact string matching
of {DNA} sequences on {FPGA}},
journal = {Microprocess. Microsystems},
volume = {97},
pages = {104763},
year = {2023}
}
@article{DBLP:journals/mta/ZhangSZ23,
author = {Jun Zhang and
Wenchen Shi and
Hao Zhang},
title = {Study on versatile video coding multiple transform selection of hardware
architecture based on {FPGA}},
journal = {Multim. Tools Appl.},
volume = {82},
number = {10},
pages = {14929--14944},
year = {2023}
}
@article{DBLP:journals/sap/RenugadeviJVBT23,
author = {N. Renugadevi and
Stheya Julakanti and
Sai Charan Vemula and
Somya Bhatnagar and
Shirisha Thangallapally},
title = {Low area and high throughput implementation of advanced encryption
standard hardware accelerator on {FPGA} using Mux-Demux pair},
journal = {Secur. Priv.},
volume = {6},
number = {4},
year = {2023}
}
@article{DBLP:journals/sensors/BashaKCLSJKD23,
author = {Mudasar Basha and
Munuswamy Siva Kumar and
Mangali Chinna Chinnaiah and
Siew{-}Kei Lam and
Thambipillai Srikanthan and
Narambhatla Janardhan and
Dodde Hari Krishna and
Sanjay Dubey},
title = {A Versatile Approach to Polygonal Object Avoidance in Indoor Environments
with Hardware Schemes Using an FPGA-Based Multi-Robot},
journal = {Sensors},
volume = {23},
number = {23},
pages = {9480},
year = {2023}
}
@article{DBLP:journals/sensors/SuSAS23,
author = {Yuanxin Su and
Kah Phooi Seng and
Li{-}Minn Ang and
Jeremy Smith},
title = {Binary Neural Networks in FPGAs: Architectures, Tool Flows and Hardware
Comparisons},
journal = {Sensors},
volume = {23},
number = {22},
pages = {9254},
year = {2023}
}
@article{DBLP:journals/sensors/SuiLZZYZT23,
author = {Xuefu Sui and
Qunbo Lv and
Liangjie Zhi and
Baoyu Zhu and
Yuanbo Yang and
Yu Zhang and
Zheng Tan},
title = {A Hardware-Friendly High-Precision {CNN} Pruning Method and Its {FPGA}
Implementation},
journal = {Sensors},
volume = {23},
number = {2},
pages = {824},
year = {2023}
}
@article{DBLP:journals/sncs/KokkiligaddaNPSP23,
author = {Venkata Siva Kumar Kokkiligadda and
Vijitha Naikoti and
Gaurao Sunil Patkotwar and
Samrat L. Sabat and
Rangababu Peesapati},
title = {FPGA-Based Hardware Accelerator for Matrix Inversion},
journal = {{SN} Comput. Sci.},
volume = {4},
number = {2},
pages = {147},
year = {2023}
}
@article{DBLP:journals/tc/DangMG23,
author = {Viet Ba Dang and
Kamyar Mohajerani and
Kris Gaj},
title = {High-Speed Hardware Architectures and {FPGA} Benchmarking of CRYSTALS-Kyber,
NTRU, and Saber},
journal = {{IEEE} Trans. Computers},
volume = {72},
number = {2},
pages = {306--320},
year = {2023}
}
@article{DBLP:journals/tc/PaulYSKT23,
author = {Bikram Paul and
Tarun Kumar Yadav and
Balbir Singh and
Srinivasan Krishnaswamy and
Gaurav Trivedi},
title = {A Resource Efficient Software-Hardware Co-Design of Lattice-Based
Homomorphic Encryption Scheme on the {FPGA}},
journal = {{IEEE} Trans. Computers},
volume = {72},
number = {5},
pages = {1247--1260},
year = {2023}
}
@article{DBLP:journals/tcasI/SongHTW23,
author = {Yifeng Song and
Xiao Hu and
Jing Tian and
Zhongfeng Wang},
title = {A High-Speed FPGA-Based Hardware Implementation for Leighton-Micali
Signature},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {70},
number = {1},
pages = {241--252},
year = {2023}
}
@article{DBLP:journals/tie/WangXCL23,
author = {Yu Wang and
Wujun Xie and
Haochang Chen and
David Day{-}Uei Li},
title = {Low-Hardware Consumption, Resolution-Configurable Gray Code Oscillator
Time-to-Digital Converters Implemented in 16 nm, 20 nm, and 28 nm
FPGAs},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {70},
number = {4},
pages = {4256--4266},
year = {2023}
}
@article{DBLP:journals/tjs/ZaganG23,
author = {Ionel Zagan and
Vasile Gheorghita Gaitan},
title = {{FPGA} implementation of hardware accelerated {RTOS} based on real-time
event handling},
journal = {J. Supercomput.},
volume = {79},
number = {11},
pages = {12441--12471},
year = {2023}
}
@article{DBLP:journals/tjs/ZaganG23a,
author = {Ionel Zagan and
Vasile Gheorghita Gaitan},
title = {Correction to: {FPGA} implementation of hardware accelerated {RTOS}
based on real-time event handling},
journal = {J. Supercomput.},
volume = {79},
number = {13},
pages = {15213},
year = {2023}
}
@article{DBLP:journals/trets/HeBXA23,
author = {Pengzhou He and
Tianyou Bao and
Jiafeng Xie and
Moeness G. Amin},
title = {{FPGA} Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based
Post-quantum Cryptography},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {45:1--45:23},
year = {2023}
}
@article{DBLP:journals/trets/SuhMNKCS23,
author = {Han{-}Sok Suh and
Jian Meng and
Ty Nguyen and
Vijay Kumar and
Yu Cao and
Jae{-}Sun Seo},
title = {Algorithm-hardware Co-optimization for Energy-efficient Drone Detection
on Resource-constrained {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {33:1--33:25},
year = {2023}
}
@article{DBLP:journals/tvlsi/LingLCQLZW23,
author = {Ming Ling and
Qingde Lin and
Ruiqi Chen and
Haimeng Qi and
Mengru Lin and
Yanxiang Zhu and
Jiansheng Wu},
title = {Vina-FPGA: {A} Hardware-Accelerated Molecular Docking Tool With Fixed-Point
Quantization and Low-Level Parallelism},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {484--497},
year = {2023}
}
@inproceedings{DBLP:conf/aisd/PandeySRAKTMS23,
author = {Sandeep Kumar Pandey and
Geetika Srivastava and
Mamun Bin Ibne Reaz and
Sawal Hamid Md. Ali and
Edi Kurniawan and
Rabindra Gandhi Thangarajoo and
Ganga Ram Mishra and
Sacchidanand Shukla},
title = {FPGA-based Hardware Classifier for Diabetic Sensorimotor Polyneuropathy
Severity Assessment},
booktitle = {{AISD}},
series = {{CEUR} Workshop Proceedings},
volume = {3619},
pages = {33--41},
publisher = {CEUR-WS.org},
year = {2023}
}
@inproceedings{DBLP:conf/applepies/JamiliMCBMAO23,
author = {Saeid Jamili and
Antonio Mastrandrea and
Abdallah Cheikh and
Marcello Barbirotta and
Francesco Menichelli and
Marco Angioli and
Mauro Olivieri},
title = {A Universal Hardware Emulator for Verification IPs on {FPGA:} {A}
Novel and Low-Cost Approach},
booktitle = {ApplePies},
series = {Lecture Notes in Electrical Engineering},
volume = {1110},
pages = {36--41},
publisher = {Springer},
year = {2023}
}
@inproceedings{DBLP:conf/apweb/HuLLZ23,
author = {Wei Hu and
Heyuan Li and
Fang Liu and
Zhiyv Zhong},
title = {Hardware and Software Co-optimization of Convolutional and Self-attention
Combined Model Based on {FPGA}},
booktitle = {APWeb/WAIM {(3)}},
series = {Lecture Notes in Computer Science},
volume = {14333},
pages = {328--342},
publisher = {Springer},
year = {2023}
}
@inproceedings{DBLP:conf/asicon/ShiZZY23,
author = {Rui Shi and
Yunfan Zuo and
Kelong Zhang and
Hao Yan},
title = {Hardware Acceleration Linear Matrix Solvor Based on {FPGA}},
booktitle = {{ASICON}},
pages = {1--4},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/ats/ChenHXSXGZ23,
author = {Xin Chen and
Liangzhou Huo and
Yudong Xie and
Zhihao Shen and
Zhiqiang Xiang and
Changhao Gao and
Ying Zhang},
title = {FPGA-Based Cross-Hardware {MBU} Emulation Platform for Layout-Level
Digital {VLSI}},
booktitle = {{ATS}},
pages = {1--6},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/cbms/StanchieriMFPFGP23,
author = {Guido Di Patrizio Stanchieri and
Andrea De Marcellis and
Marco Faccio and
Elia Palange and
Mario Di Ferdinando and
Stefano Di Gennaro and
Pierdomenico Pepe},
title = {On the FPGA-Based Hardware Implementation of Digital Glucose Regulators
for Type 2 Diabetic Patients},
booktitle = {{CBMS}},
pages = {802--805},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/cipae/LinCW23,
author = {Yuxuan Lin and
Huangxu Chen and
Zhaohui Wu},
title = {A hardware architecture design for interference rejection of ultrasound
signals based on {FPGA}},
booktitle = {{CIPAE}},
pages = {492--496},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/cscwd/LiuGTZS23,
author = {Jihong Liu and
Neng Gao and
Chenyang Tu and
Yifei Zhang and
Yongjuan Sun},
title = {A Pure Hardware Design and Implementation on {FPGA} of WireGuard-based
{VPN} Gateway},
booktitle = {{CSCWD}},
pages = {1220--1225},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/cvpr/PlochaetG23,
author = {Jef Plochaet and
Toon Goedem{\'{e}}},
title = {Hardware-Aware Pruning for {FPGA} Deep Learning Accelerators},
booktitle = {{CVPR} Workshops},
pages = {4482--4490},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/date/CuiLCZZYLC23,
author = {Hongwei Cui and
Shuhao Liang and
Yujie Cui and
Weiqi Zhang and
Honglan Zhan and
Chun Yang and
Xianhua Liu and
Xu Cheng},
title = {A Hardware-Software Cooperative Interval-Replaying for FPGA-based
Architecture Evaluation},
booktitle = {{DATE}},
pages = {1--2},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/eit/JohnsonZS23,
author = {Hans Johnson and
Silvia Zorzetti and
Jafar Saniie},
title = {Exploration of Optimizing FPGA-based Qubit Controller for Experiments
on Superconducting Quantum Computing Hardware},
booktitle = {eIT},
pages = {406--411},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/ewdts/MelikyanGAK23,
author = {Vazgen Melikyan and
Mushegh T. Grigoryan and
Ashot Avetisyan and
Tigran Khachatryan},
title = {Accelerating {CNN} Models for Visual Odometry: Design and {FPGA} Implementation
for Efficient Hardware Acceleration},
booktitle = {{EWDTS}},
pages = {1--5},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/fccm/0007ZGDWS23,
author = {Jiajun Wu and
Jiajun Zhou and
Yizhao Gao and
Yuhao Ding and
Ngai Wong and
Hayden Kwok{-}Hay So},
title = {{MSD:} Mixing Signed Digit Representations for Hardware-efficient
{DNN} Acceleration on {FPGA} with Heterogeneous Resources},
booktitle = {{FCCM}},
pages = {94--104},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/fccm/AizazKT23,
author = {Zainab Aizaz and
Kavita Khare and
Aizaz Tirmizi},
title = {{FASBM:} FPGA-specific Approximate Sum-based Booth multipliers for
energy efficient Hardware Acceleration of Image Processing and Machine
Learning Applications},
booktitle = {{FCCM}},
pages = {210},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/fccm/WangLZYW23,
author = {Yuanfang Wang and
Yu Li and
Haoyang Zhang and
Jun Yu and
Kun Wang},
title = {Moth: {A} Hardware Accelerator for Neural Radiance Field Inference
on {FPGA}},
booktitle = {{FCCM}},
pages = {227},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/ficloud/AllamASE23,
author = {Oussama El Allam and
Abdelhakim Alali and
Mohamed Sadik and
Hasna Elmaaradi},
title = {Open-source Hardware {FPGA} Platforms for IoT: Paradigms, opportunities
and open issues},
booktitle = {FiCloud},
pages = {292--297},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/fie/LiLJLHYL23,
author = {Ying Li and
Jingzhuo Liang and
Gui Shi Jie and
Yangdong Liu and
Wei Huang and
Yue Yan and
Xianglong Liu},
title = {An innovative experimental teaching method of hardware-software co-design-Taking
a hardware accelerator of neural network using {FPGA}},
booktitle = {{FIE}},
pages = {1--5},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/fpga/HowABLSG23,
author = {Dana How and
Tim Ansell and
Vaughn Betz and
Chris Lavin and
Ted Speers and
Pierre{-}Emmanuel Gaillardon},
title = {Open-source and FPGAs: Hardware, Software, Both or None?},
booktitle = {{FPGA}},
pages = {149},
publisher = {{ACM}},
year = {2023}
}
@inproceedings{DBLP:conf/fpga/ShadabZGL23,
author = {Rakin Muhammad Shadab and
Yu Zou and
Sanjay Gandham and
Mingjie Lin},
title = {{OMT:} {A} Demand-Adaptive, Hardware-Targeted Bonsai Merkle Tree Framework
for Embedded Heterogeneous Memory Platform},
booktitle = {{FPGA}},
pages = {47},
publisher = {{ACM}},
year = {2023}
}
@inproceedings{DBLP:conf/fpl/Jentzsch23,
author = {Felix Jentzsch},
title = {Hardware-Aware AutoML for Exploration of Custom {FPGA} Accelerators
for RadioML},
booktitle = {{FPL}},
pages = {359--360},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/fpl/ZhaoHH23,
author = {Baoze Zhao and
Wenjin Huang and
Yihua Huang},
title = {A Novel Hardware Accelerator of NeRF Based on Xilinx UltraScale and
UltraScale+ {FPGA}},
booktitle = {{FPL}},
pages = {197--203},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/fpt/ZhaoHLH23,
author = {Baoze Zhao and
Wenjin Huang and
Tianrui Li and
Yihua Huang},
title = {{BSTMSM:} {A} High-Performance FPGA-based Multi-Scalar Multiplication
Hardware Accelerator},
booktitle = {{ICFPT}},
pages = {35--43},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/iait/SahaGPR23,
author = {Piyali Saha and
Sudip Ghosh and
Debajyoti Pal and
Hafizur Rahaman},
title = {Hardware Performance Analysis of N-bit {CLA} on {FPGA} and Programmable
SoC},
booktitle = {{IAIT}},
pages = {1:1--1:7},
publisher = {{ACM}},
year = {2023}
}
@inproceedings{DBLP:conf/ic3i/ShrivastavaK23,
author = {Shishir Shrivastava and
Amanpreet Kaur},
title = {Comparative Energy {\&} Hardware Analysis on Implementation of
8-Bit {ALU} Using Different FPGAs Families},
booktitle = {{IC3I}},
pages = {193--197},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/ic3i/ShrivastavaK23a,
author = {Shishir Shrivastava and
Amanpreet Kaur},
title = {Comparative Energy {\&} Hardware Analysis on Implementation of
Full Subtractor Using Different FPGAs Families},
booktitle = {{IC3I}},
pages = {198--202},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/icc/BaiZCZCZCYW23,
author = {Yueyin Bai and
Hao Zhou and
Ruiqi Chen and
Kuangjie Zou and
Jialin Cao and
Haoyang Zhang and
Jianli Chen and
Jun Yu and
Kun Wang},
title = {g-BERT: Enabling Green {BERT} Deployment on {FPGA} via Hardware-Aware
Hybrid Pruning},
booktitle = {{ICC}},
pages = {1706--1711},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/iccad/PuSHYSZ23,
author = {Ruiyao Pu and
Yiwei Sun and
Pei{-}Hsin Ho and
Fan Yang and
Li Shang and
Xuan Zeng},
title = {Sphinx: {A} Hybrid Boolean Processor-FPGA Hardware Emulation System},
booktitle = {{ICCAD}},
pages = {1--9},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/iccel/CruzGMAJSD23,
author = {Thiago S. Cruz and
Jo{\~{a}}o P. M. Gomes and
Lucas F. Martins and
Danyllo W. Albuquerque and
Gutemberg G. dos Santos J{\'{u}}nior and
Danilo F. S. Santos and
Jemerson Dam{\'{a}}sio},
title = {Extensible Hardware Inference Accelerator for {FPGA} using Models
from TensorFlow Lite},
booktitle = {{ICCE}},
pages = {1--5},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/iccsa/PhamQuoc23,
author = {Cuong Pham{-}Quoc},
title = {FPGA-Based Hardware/Software Codesign for Video Encoder on IoT Edge
Platforms},
booktitle = {{ICCSA} (Workshops 5)},
series = {Lecture Notes in Computer Science},
volume = {14108},
pages = {82--96},
publisher = {Springer},
year = {2023}
}
@inproceedings{DBLP:conf/icecsys/MurtazaPMQB23,
author = {Ali Murtaza and
Muhammad Adeel Pasha and
Shahid Masud and
Muhammad Yasir Qadri and
Abdul Basit},
title = {{FPGA} Based Intelligent Hardware Trojan Design and its SoC Implementation},
booktitle = {{ICECS}},
pages = {1--4},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/icecsys/OztasODA23,
author = {Ali Emre Oztas and
Ege Ozteke and
Mahir Demir and
Tankut Akgul},
title = {Implementation of a Hardware Accelerated {VVC} Decoder on {ARM} and
{FPGA}},
booktitle = {{ICECS}},
pages = {1--4},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/icspcc/LuoHWC23,
author = {Wenqin Luo and
Patrick Hung and
Shiqi Wang and
Ray C. C. Cheung},
title = {Image Super-Resolution and {FPGA} Hardware Design},
booktitle = {{ICSPCC}},
pages = {1--5},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/ijcnn/YemmeG23,
author = {Anil Yemme and
Shayan Srinivasa Garani},
title = {A Scalable {GPT-2} Inference Hardware Architecture on {FPGA}},
booktitle = {{IJCNN}},
pages = {1--8},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/isaims/Kang23,
author = {Zhengdong Kang},
title = {Hardware acceleration of the {SED} algorithm for Biomolecular activity
predictionBiomolecular activity algorithm {(SED)} uses {FPGA} parallel
programmability to achieve hardware acceleration},
booktitle = {{ISAIMS}},
pages = {1136--1140},
publisher = {{ACM}},
year = {2023}
}
@inproceedings{DBLP:conf/iscas/ChenZMCY023,
author = {Ruiqi Chen and
Haoyang Zhang and
Yuhanxiao Ma and
Jianli Chen and
Jun Yu and
Kun Wang},
title = {eSSpMV: An Embedded-FPGA-based Hardware Accelerator for Symmetric
Sparse Matrix-Vector Multiplication},
booktitle = {{ISCAS}},
pages = {1--5},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/iscas/GrafP23,
author = {Jeremy R. Graf and
Darshika G. Perera},
title = {Optimizing Density-Based Ant Colony Stream Clustering Using FPGA-Based
Hardware Accelerator},
booktitle = {{ISCAS}},
pages = {1--5},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/isocc/KishimotoT23,
author = {Yui Kishimoto and
Hiroyuki Torikai},
title = {A hardware-efficient {FPGA} cochlear model for next generation nonlinear
cochlear implant},
booktitle = {{ISOCC}},
pages = {253--255},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/isqed/GuerrieriM0U23,
author = {Andrea Guerrieri and
Gabriel Da Silva Marques and
Francesco Regazzoni and
Andres Upegui},
title = {H-Saber: An FPGA-Optimized Version for Designing Fast and Efficient
Post-Quantum Cryptography Hardware Accelerators},
booktitle = {{ISQED}},
pages = {1--6},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/isqed/RajputDD23,
author = {Shailesh Rajput and
Jaya Dofe and
Wafi Danesh},
title = {Automating Hardware Trojan Detection Using Unsupervised Learning:
{A} Case Study of {FPGA}},
booktitle = {{ISQED}},
pages = {1--6},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/meco/TanDJM23,
author = {Yiming Tan and
Aditya Diwakar and
Jason Jagielo and
Vincent John Mooney},
title = {Software Compilation Using {FPGA} Hardware: Register Allocation},
booktitle = {{MECO}},
pages = {1--6},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/mwscas/KordiBFM23,
author = {Farshideh Kordi and
Christian Barnard and
Paul Fortier and
Amine Miled},
title = {FPGA-Based Hardware-in-the-Loop Real-Time Simulation Implementation},
booktitle = {{MWSCAS}},
pages = {232--235},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/mwscas/NguyenZVP23,
author = {Dyk Chung Nguyen and
Yuan{-}Hang Zhang and
Massimiliano Di Ventra and
Yuriy V. Pershin},
title = {Hardware Implementation of Digital Memcomputing on Small-Size FPGAs},
booktitle = {{MWSCAS}},
pages = {346--350},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/mwscas/WangCYWL23,
author = {Haonan Wang and
Ke Chen and
Chenggang Yan and
Bi Wu and
Weiqiang Liu},
title = {Hardware-Efficient Accurate and Approximate {FPGA} Multipliers for
Error-Tolerant Applications},
booktitle = {{MWSCAS}},
pages = {977--981},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/niles/ElgoharyN23,
author = {Ahmed Elgohary and
Omar A. Nasr},
title = {An Efficient Hardware Implementation of {CNN} Generic Processor for
{FPGA}},
booktitle = {{NILES}},
pages = {217--221},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/tencon/RaoP23,
author = {Prajwal S. Rao and
Aparna Pulikala},
title = {Hardware-Optimized Deep Learning Model for FPGA-Based Character Recognition},
booktitle = {{TENCON}},
pages = {238--242},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/uemcom/RexW23,
author = {Eric Rex and
Xiaofang Wang},
title = {Efficient Quantization and Hardware Implementation of AlexNet on Resource-limited
FPGAs},
booktitle = {{UEMCON}},
pages = {399--406},
publisher = {{IEEE}},
year = {2023}
}
@inproceedings{DBLP:conf/vlsid/PathakS23,
author = {Meghvern Pathak and
Rahul Shrestha},
title = {Hardware Architecture and {FPGA} Implementation of Low Latency Turbo
Encoder for Deep-Space Communication Systems},
booktitle = {{VLSID}},
pages = {1--6},
publisher = {{IEEE}},
year = {2023}
}
@article{DBLP:journals/corr/abs-2302-02959,
author = {Stefan Bosse},
title = {Rule-based High-level Hardware-RTL Synthesis of Algorithms, Virtualizing
Machines, and Communication Protocols with FPGAs based on Concurrent
Communicating Sequential Processes and the ConPro Synthesis Framework},
journal = {CoRR},
volume = {abs/2302.02959},
year = {2023}
}
@article{DBLP:journals/corr/abs-2305-01061,
author = {Dyk Chung Nguyen and
Yuan{-}Hang Zhang and
Massimiliano Di Ventra and
Yuriy V. Pershin},
title = {Hardware implementation of digital memcomputing on small-size FPGAs},
journal = {CoRR},
volume = {abs/2305.01061},
year = {2023}
}
@article{DBLP:journals/corr/abs-2306-09501,
author = {Alessandro Ottaviano and
Robert Balas and
Giovanni Bambini and
Antonio del Vecchio and
Maicol Ciani and
Davide Rossi and
Luca Benini and
Andrea Bartolini},
title = {ControlPULP: {A} {RISC-V} On-Chip Parallel Power Controller for Many-Core
{HPC} Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal
Emulation},
journal = {CoRR},
volume = {abs/2306.09501},
year = {2023}
}
@article{DBLP:journals/corr/abs-2307-09371,
author = {Manolis Ploumidis and
Fabien Chaix and
Nikolaos Chrysos and
Marios Asiminakis and
Vassilis Flouris and
Nikolaos D. Kallimanis and
Nikolaos Kossifidis and
Michael Nikoloudakis and
Polydoros Petrakis and
Nikolaos Dimou and
Michalis Gianioudis and
Georgios Ieronymakis and
Aggelos Ioannou and
George Kalokerinos and
Pantelis Xirouchakis and
Georgios Ailamakis and
Astrinos Damianakis and
Michael Ligerakis and
Ioannis Makris and
Theocharis Vavouris and
Manolis Katevenis and
Vassilis Papaefstathiou and
Manolis Marazakis and
Iakovos Mavroidis},
title = {The ExaNeSt Prototype: Evaluation of Efficient {HPC} Communication
Hardware in an ARM-based Multi-FPGA Rack},
journal = {CoRR},
volume = {abs/2307.09371},
year = {2023}
}
@article{DBLP:journals/corr/abs-2309-13321,
author = {Federico Manca and
Francesco Ratto},
title = {ONNX-to-Hardware Design Flow for the Generation of Adaptive Neural-Network
Accelerators on FPGAs},
journal = {CoRR},
volume = {abs/2309.13321},
year = {2023}
}
@article{DBLP:journals/corr/abs-2309-16158,
author = {Jindong Li and
Guobin Shen and
Dongcheng Zhao and
Qian Zhang and
Yi Zeng},
title = {FireFly v2: Advancing Hardware Support for High-Performance Spiking
Neural Network with a Spatiotemporal {FPGA} Accelerator},
journal = {CoRR},
volume = {abs/2309.16158},
year = {2023}
}
@article{DBLP:journals/corr/abs-2311-04581,
author = {Suraj Mandal and
Debapriya Basu Roy},
title = {KiD: {A} Hardware Design Framework Targeting Unified {NTT} Multiplication
for CRYSTALS-Kyber and CRYSTALS-Dilithium on {FPGA}},
journal = {CoRR},
volume = {abs/2311.04581},
year = {2023}
}
@article{DBLP:journals/access/BeheraR22,
author = {Sagarika Behera and
Prathuri Jhansi Rani},
title = {Design of Novel Hardware Architecture for Fully Homomorphic Encryption
Algorithms in {FPGA} for Real-Time Data in Cloud Computing},
journal = {{IEEE} Access},
volume = {10},
pages = {131406--131418},
year = {2022}
}
@article{DBLP:journals/access/MolinaGCR22,
author = {Romina Soledad Molina and
Veronica Gil{-}Costa and
Maria Liz Crespo and
Giovanni Ramponi},
title = {High-Level Synthesis Hardware Design for FPGA-Based Accelerators:
Models, Methodologies, and Frameworks},
journal = {{IEEE} Access},
volume = {10},
pages = {90429--90455},
year = {2022}
}
@article{DBLP:journals/access/WangCGDCZH22,
author = {Zixiao Wang and
Biyao Che and
Liang Guo and
Yang Du and
Ying Chen and
Jizhuang Zhao and
Wei He},
title = {PipeFL: Hardware/Software co-Design of an {FPGA} Accelerator for Federated
Learning},
journal = {{IEEE} Access},
volume = {10},
pages = {98649--98661},
year = {2022}
}
@article{DBLP:journals/access/YuZWY22,
author = {Le Yu and
Shiwei Zhang and
Nansong Wu and
Chongchong Yu},
title = {FPGA-Based Hardware-in-the-Loop Simulation of User Selection Algorithms
for Cooperative Transmission Technology Over {LOS} Channel on Geosynchronous
Satellites},
journal = {{IEEE} Access},
volume = {10},
pages = {6071--6083},
year = {2022}
}
@article{DBLP:journals/cacm/Mattioli22,
author = {Michael Mattioli},
title = {FPGAs in client compute hardware},
journal = {Commun. {ACM}},
volume = {65},
number = {8},
pages = {36--42},
year = {2022}
}
@article{DBLP:journals/cem/ZhangLWLWJ22,
author = {Zhendong Zhang and
Peng Liu and
Weidong Wang and
Shunbin Li and
Peng Wang and
Yingtao Jiang},
title = {High-Performance Password Recovery Hardware Going From {GPU} to Hybrid
{CPU-FPGA} Platform},
journal = {{IEEE} Consumer Electron. Mag.},
volume = {11},
number = {1},
pages = {80--87},
year = {2022}
}
@article{DBLP:journals/computers/Adam22,
author = {George K. Adam},
title = {Co-Design of Multicore Hardware and Multithreaded Software for Thread
Performance Assessment on an {FPGA}},
journal = {Comput.},
volume = {11},
number = {5},
pages = {76},
year = {2022}
}
@article{DBLP:journals/csse/GuptaVJKK22,
author = {Namit Gupta and
Kunwar Singh Vaisla and
Arpit Jain and
Adesh Kumar and
Rajeev Kumar},
title = {Performance Analysis of {AODV} Routing for Wireless Sensor Network
in {FPGA} Hardware},
journal = {Comput. Syst. Sci. Eng.},
volume = {40},
number = {3},
pages = {1073--1084},
year = {2022}
}
@article{DBLP:journals/esl/MukherjeeC22,
author = {Rijoy Mukherjee and
Rajat Subhra Chakraborty},
title = {Novel Hardware Trojan Attack on Activation Parameters of FPGA-Based
{DNN} Accelerators},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {14},
number = {3},
pages = {131--134},
year = {2022}
}
@article{DBLP:journals/et/RSAP22,
author = {Naveenkumar R and
N. M. Sivamangai and
Napolean A and
S. Sridevi Sathya Priya},
title = {Design and Evaluation of {XOR} Arbiter Physical Unclonable Function
and its Implementation on {FPGA} in Hardware Security Applications},
journal = {J. Electron. Test.},
volume = {38},
number = {6},
pages = {653--666},
year = {2022}
}
@article{DBLP:journals/ieiceee/ZhangGHZCY22,
author = {Fei Zhang and
Ziyang Gao and
Jiaming Huang and
Peining Zhen and
Hai{-}Bao Chen and
Jie Yan},
title = {{HFOD:} {A} hardware-friendly quantization method for object detection
on embedded FPGAs},
journal = {{IEICE} Electron. Express},
volume = {19},
number = {8},
pages = {20220067},
year = {2022}
}
@article{DBLP:journals/ieiceee/ZufengG22,
author = {Luo Zufeng and
Yuan Guo{-}shun},
title = {{LDCPUF:} {A} novel FPGA-based physical unclonable function with ultra-low
hardware cost},
journal = {{IEICE} Electron. Express},
volume = {19},
number = {16},
pages = {20220246},
year = {2022}
}
@article{DBLP:journals/ieiceta/ManabeKS22,
author = {Taito Manabe and
Taichi Katayama and
Yuichiro Shibata},
title = {{FPGA} Implementation of a Stream-Based Real-Time Hardware Line Segment
Detector},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {105-A},
number = {3},
pages = {468--477},
year = {2022}
}
@article{DBLP:journals/ieiceta/MoriMS22,
author = {Tatsuma Mori and
Taito Manabe and
Yuichiro Shibata},
title = {A Hardware Oriented Approximate Convex Hull Algorithm and its {FPGA}
Implementation},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {105-A},
number = {3},
pages = {459--467},
year = {2022}
}
@article{DBLP:journals/ijcomsys/VenkataramananL22,
author = {V. Venkataramanan and
S. Lakshmi},
title = {Performance analysis of {LTE} physical layer using hardware cosimulation
techniques and implementation on {FPGA} for communication systems},
journal = {Int. J. Commun. Syst.},
volume = {35},
number = {2},
year = {2022}
}
@article{DBLP:journals/ijnm/HuangGS22,
author = {Xiaoying Huang and
Zhichuan Guo and
Mangu Song},
title = {{FGLB:} {A} fine-grained hardware intra-server load balancer based
on 100 {G} {FPGA} SmartNIC},
journal = {Int. J. Netw. Manag.},
volume = {32},
number = {6},
year = {2022}
}
@article{DBLP:journals/jce/GrossJZS22,
author = {Mathieu Gross and
Nisha Jacob and
Andreas Zankl and
Georg Sigl},
title = {Breaking TrustZone memory isolation and secure boot through malicious
hardware on a modern FPGA-SoC},
journal = {J. Cryptogr. Eng.},
volume = {12},
number = {2},
pages = {181--196},
year = {2022}
}
@article{DBLP:journals/jcsc/GuptaC22,
author = {Mangal Deep Gupta and
Rajeev K. Chauhan},
title = {Hardware Efficient Pseudo-Random Number Generator Using Chen Chaotic
System on {FPGA}},
journal = {J. Circuits Syst. Comput.},
volume = {31},
number = {3},
pages = {2250043:1--2250043:14},
year = {2022}
}
@article{DBLP:journals/jetc/AnandakumarHS22,
author = {N. Nalla Anandakumar and
Mohammad S. Hashmi and
Somitra Kumar Sanadhya},
title = {Design and Analysis of FPGA-based PUFs with Enhanced Performance for
Hardware-oriented Security},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {18},
number = {4},
pages = {72:1--72:26},
year = {2022}
}
@article{DBLP:journals/jsa/PalumboCLHRBO22,
author = {Alessandro Palumbo and
Luca Cassano and
Bruno Luzzi and
Jos{\'{e}} Alberto Hern{\'{a}}ndez and
Pedro Reviriego and
Giuseppe Bianchi and
Marco Ottavi},
title = {Is your {FPGA} bitstream Hardware Trojan-free? Machine learning can
provide an answer},
journal = {J. Syst. Archit.},
volume = {128},
pages = {102543},
year = {2022}
}
@article{DBLP:journals/lgrs/MaciasBBG22,
author = {Rub{\'{e}}n Macias and
Sergio Bernab{\'{e}} and
Daniel B{\'{a}}scones and
Carlos Gonz{\'{a}}lez},
title = {{FPGA} Implementation of a Hardware Optimized Automatic Target Detection
and Classification Algorithm for Hyperspectral Image Analysis},
journal = {{IEEE} Geosci. Remote. Sens. Lett.},
volume = {19},
pages = {1--5},
year = {2022}
}
@article{DBLP:journals/mam/FariasNC22,
author = {Marcos Santana Farias and
Nadia Nedjah and
Paulo Victor R. de Carvalho},
title = {Active redundant hardware architecture for increased reliability in
FPGA-based nuclear reactors critical systems},
journal = {Microprocess. Microsystems},
volume = {90},
pages = {104495},
year = {2022}
}
@article{DBLP:journals/mam/HamdaouiBM22,
author = {Fay{\c{c}}al Hamdaoui and
Sana Bougharriou and
Abdellatif Mtibaa},
title = {Optimized Hardware Vision System for Vehicle Detection based on {FPGA}
and Combining Machine Learning and {PSO}},
journal = {Microprocess. Microsystems},
volume = {90},
pages = {104469},
year = {2022}
}
@article{DBLP:journals/mam/WulfWG22,
author = {Cornelia Wulf and
Michael Willig and
Diana Goehringer},
title = {RTOS-supported low power scheduling of periodic hardware tasks in
flash-based FPGAs},
journal = {Microprocess. Microsystems},
volume = {92},
pages = {104566},
year = {2022}
}
@article{DBLP:journals/mj/LiHCGHX22,
author = {Xueming Li and
Hongmin Huang and
Taosheng Chen and
Huaien Gao and
Xianghong Hu and
Xiaoming Xiong},
title = {A hardware-efficient computing engine for FPGA-based deep convolutional
neural network accelerator},
journal = {Microelectron. J.},
volume = {128},
pages = {105547},
year = {2022}
}
@article{DBLP:journals/monet/Pham-QuocNT22,
author = {Cuong Pham{-}Quoc and
Xuan Quang Nguyen and
Tran Ngoc Thinh},
title = {Towards An FPGA-targeted Hardware/Software Co-design Framework for
CNN-based Edge Computing},
journal = {Mob. Networks Appl.},
volume = {27},
number = {5},
pages = {2024--2035},
year = {2022}
}
@article{DBLP:journals/ojcands/GoldsmithCS22,
author = {Josh Goldsmith and
Louise H. Crockett and
Robert W. Stewart},
title = {A Natively Fixed-Point Run-Time Reconfigurable {FIR} Filter Design
Method for {FPGA} Hardware},
journal = {{IEEE} Open J. Circuits Syst.},
volume = {3},
pages = {25--37},
year = {2022}
}
@article{DBLP:journals/remotesensing/PitonakMDJM22,
author = {Radoslav Pitonak and
Jan Mucha and
Lukas Dobis and
Martin Javorka and
Marek Marusin},
title = {CloudSatNet-1: FPGA-Based Hardware-Accelerated Quantized {CNN} for
Satellite On-Board Cloud Coverage Classification},
journal = {Remote. Sens.},
volume = {14},
number = {13},
pages = {3180},
year = {2022}
}
@article{DBLP:journals/sensors/SilvaPMNMF22,
author = {Jo{\~{a}}o Silva and
Pedro Pereira and
Rui Machado and
Rafael N{\'{e}}voa and
Pedro Melo{-}Pinto and
Duarte Fernandes},
title = {Customizable FPGA-Based Hardware Accelerator for Standard Convolution
Processes Empowered with Quantization Applied to LiDAR Data},
journal = {Sensors},
volume = {22},
number = {6},
pages = {2184},
year = {2022}
}
@article{DBLP:journals/sensors/SuiLBZZYT22,
author = {Xuefu Sui and
Qunbo Lv and
Yang Bai and
Baoyu Zhu and
Liangjie Zhi and
Yuanbo Yang and
Zheng Tan},
title = {A Hardware-Friendly Low-Bit Power-of-Two Quantization Method for CNNs
and Its {FPGA} Implementation},
journal = {Sensors},
volume = {22},
number = {17},
pages = {6618},
year = {2022}
}
@article{DBLP:journals/sncs/OdetolaGYKH22,
author = {Tolulope A. Odetola and
Katie M. Groves and
Muhammed Yousufuddin and
Faiq Khalid and
Syed Rafay Hasan},
title = {2L-3W: 2-Level 3-Way Hardware-Software Co-verification for the Mapping
of Convolutional Neural Network {(CNN)} onto {FPGA} Boards},
journal = {{SN} Comput. Sci.},
volume = {3},
number = {1},
pages = {60},
year = {2022}
}
@article{DBLP:journals/symmetry/SongHLXXHR22,
author = {Qi Song and
Yourui Huang and
Wenhao Lai and
Jiachang Xu and
Shanyong Xu and
Tao Han and
Xue Rong},
title = {{FPGA} Hardware Realization of Membrane Calculation Optimization Algorithm
with Great Parallelism},
journal = {Symmetry},
volume = {14},
number = {10},
pages = {2199},
year = {2022}
}
@article{DBLP:journals/tc/RodriguezOPT22,
author = {Alfonso Rodr{\'{\i}}guez and
Andr{\'{e}}s Otero and
Marco Platzner and
Eduardo de la Torre},
title = {Exploiting Hardware-Based Data-Parallel and Multithreading Models
for Smart Edge Computing in Reconfigurable FPGAs},
journal = {{IEEE} Trans. Computers},
volume = {71},
number = {11},
pages = {2903--2914},
year = {2022}
}
@article{DBLP:journals/tcad/UllahRSK22,
author = {Salim Ullah and
Semeen Rehman and
Muhammad Shafique and
Akash Kumar},
title = {High-Performance Accurate and Approximate Multipliers for FPGA-Based
Hardware Accelerators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {2},
pages = {211--224},
year = {2022}
}
@article{DBLP:journals/tcasI/LiuCYG22,
author = {Yijun Liu and
Yuehai Chen and
Wujian Ye and
Yu Gui},
title = {{FPGA-NHAP:} {A} General FPGA-Based Neuromorphic Hardware Acceleration
Platform With High Speed and Low Power},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {69},
number = {6},
pages = {2553--2566},
year = {2022}
}
@article{DBLP:journals/tcasI/LiuLHLQCLZ22,
author = {Ye Liu and
Jingyuan Li and
Kun Huang and
Xiangting Li and
Xiuyuan Qi and
Liang Chang and
Yu Long and
Jun Zhou},
title = {MobileSP: An FPGA-Based Real-Time Keypoint Extraction Hardware Accelerator
for Mobile {VSLAM}},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {69},
number = {12},
pages = {4919--4929},
year = {2022}
}
@article{DBLP:journals/tcasII/KaurKA22,
author = {Jasmin Kaur and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {Hardware Constructions for Error Detection in Lightweight Authenticated
Cipher {ASCON} Benchmarked on {FPGA}},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {69},
number = {4},
pages = {2276--2280},
year = {2022}
}
@article{DBLP:journals/tetc/KaurSKA22,
author = {Jasmin Kaur and
Ausmita Sarker and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {Hardware Constructions for Error Detection in Lightweight Welch-Gong
(WG)-Oriented Streamcipher {WAGE} Benchmarked on {FPGA}},
journal = {{IEEE} Trans. Emerg. Top. Comput.},
volume = {10},
number = {2},
pages = {1208--1215},
year = {2022}
}
@article{DBLP:journals/tie/XuGCJQ22,
author = {Fang Xu and
Zhongyi Guo and
Hong Chen and
Dongdong Ji and
Ting Qu},
title = {A Custom Parallel Hardware Architecture of Nonlinear Model-Predictive
Control on {FPGA}},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {69},
number = {11},
pages = {11569--11579},
year = {2022}
}
@article{DBLP:journals/tnn/HuangWCLZLH22,
author = {Wenjin Huang and
Huangtao Wu and
Qingkun Chen and
Conghui Luo and
Shihao Zeng and
Tianrui Li and
Yihua Huang},
title = {FPGA-Based High-Throughput {CNN} Hardware Accelerator With High Computing
Resource Utilization Ratio},
journal = {{IEEE} Trans. Neural Networks Learn. Syst.},
volume = {33},
number = {8},
pages = {4069--4083},
year = {2022}
}
@article{DBLP:journals/trets/DamianiFBBS22,
author = {Andrea Damiani and
Giorgia Fiscaletti and
Marco Bacis and
Rolando Brondolin and
Marco D. Santambrogio},
title = {BlastFunction: {A} Full-stack Framework Bringing {FPGA} Hardware Acceleration
to Cloud-native Applications},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {2},
pages = {17:1--17:27},
year = {2022}
}
@article{DBLP:journals/tvlsi/GhaffariCL22,
author = {Sina Ghaffari and
David W. Capson and
Kin Fun Li},
title = {A Fully Pipelined {FPGA} Architecture for Multiscale {BRISK} Descriptors
With a Novel Hardware-Aware Sampling Pattern},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {826--839},
year = {2022}
}
@inproceedings{DBLP:conf/IEEEssd/AouissaouiBS22,
author = {Ichraf Aouissaoui and
Toufik Bakir and
Anis Sakly},
title = {{FPGA} Hardware Co-Simulation of a Stream Cipher Image Cryptosystem
based on Fixed-Point Chaotic Map},
booktitle = {{SSD}},
pages = {1764--1769},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/acssc/MohamedC22,
author = {Nadya A. Mohamed and
Joseph R. Cavallaro},
title = {FPGA-based {DNN} Hardware Accelerator for Sensor Network Aggregation
Node},
booktitle = {{IEEECONF}},
pages = {322--327},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/aii2/BorelliSGF22,
author = {Antonio Borelli and
Fanny Spagnolo and
Raffaele Gravina and
Fabio Frustaci},
title = {An FPGA-Based Hardware Accelerator for the k-Nearest Neighbor Algorithm
Implementation in Wearable Embedded Systems},
booktitle = {{AII}},
pages = {44--56},
year = {2022}
}
@inproceedings{DBLP:conf/aii2/HuzyukSF22,
author = {Roman Huzyuk and
Fanny Spagnolo and
Fabio Frustaci},
title = {Designing Low-Power and High-Speed FPGA-Based Binary Decision Tree
Hardware Accelerators},
booktitle = {{AII}},
pages = {57--72},
year = {2022}
}
@inproceedings{DBLP:conf/aiml2/VR22,
author = {Sanjaya M. V and
Madhav Rao},
title = {An hardware accelerator design of Mobile-Net model on {FPGA}},
booktitle = {AIMLSystems},
pages = {2:1--2:9},
publisher = {{ACM}},
year = {2022}
}
@inproceedings{DBLP:conf/applepies/CaneseCNFRS22,
author = {Lorenzo Canese and
Gian Carlo Cardarilli and
Luca Di Nunzio and
Rocco Fazzolari and
Marco Re and
Sergio Span{\`{o}}},
title = {Automatic {IP} Core Generator for FPGA-Based Q-Learning Hardware Accelerators},
booktitle = {ApplePies},
series = {Lecture Notes in Electrical Engineering},
volume = {1036},
pages = {242--247},
publisher = {Springer},
year = {2022}
}
@inproceedings{DBLP:conf/applepies/DonisiBLLR22,
author = {Andrea Donisi and
Luigi Di Benedetto and
Rosalba Liguori and
Gian Domenico Licciardo and
Alfredo Rubino},
title = {A {FPGA} HardWare Architecture for {AZSPWM} Based on a Taylor Series
Decomposition},
booktitle = {ApplePies},
series = {Lecture Notes in Electrical Engineering},
volume = {1036},
pages = {73--81},
publisher = {Springer},
year = {2022}
}
@inproceedings{DBLP:conf/applepies/MansooriC22,
author = {Mohammad Amir Mansoori and
Mario R. Casu},
title = {Multi-objective Framework for Training and Hardware Co-optimization
in FPGAs},
booktitle = {ApplePies},
series = {Lecture Notes in Electrical Engineering},
volume = {1036},
pages = {273--278},
publisher = {Springer},
year = {2022}
}
@inproceedings{DBLP:conf/arcs/PassarettiBWP22,
author = {Daniele Passaretti and
Felix Boehm and
Martin Wilhelm and
Thilo Pionteck},
title = {Hardware Isolation Support for Low-Cost SoC-FPGAs},
booktitle = {{ARCS}},
series = {Lecture Notes in Computer Science},
volume = {13642},
pages = {148--163},
publisher = {Springer},
year = {2022}
}
@inproceedings{DBLP:conf/asap/EjjehMCNSANNR22,
author = {Adel Ejjeh and
Leon Medvinsky and
Aaron Councilman and
Hemang Nehra and
Suraj Sharma and
Vikram S. Adve and
Luigi Nardi and
Eriko Nurvitadhi and
Rob A. Rutenbar},
title = {{HPVM2FPGA:} Enabling True Hardware-Agnostic {FPGA} Programming},
booktitle = {{ASAP}},
pages = {1--10},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/asiasim/ZhaoZL22,
author = {Yu Zhao and
Chun Zhao and
Yue Liu},
title = {FPGA-Based Hardware Modeling on Pigeon-Inspired Optimization Algorithm},
booktitle = {AsiaSim {(1)}},
series = {Communications in Computer and Information Science},
volume = {1712},
pages = {407--423},
publisher = {Springer},
year = {2022}
}
@inproceedings{DBLP:conf/asse/HuangRY22,
author = {Hui Huang and
Hai{-}Jun Rong and
Zhao{-}Xu Yang},
title = {A Task-Parallel and Reconfigurable FPGA-Based Hardware Implementation
of Extreme Learning Machine},
booktitle = {{ASSE}},
pages = {194--202},
publisher = {{ACM}},
year = {2022}
}
@inproceedings{DBLP:conf/cec/FritzschHB22,
author = {Clemens Fritzsch and
J{\"{o}}rn Hoffmann and
Martin Bogdan},
title = {Evolving Hardware by Direct Bitstream Manipulation of a Modern {FPGA}},
booktitle = {{CEC}},
pages = {1--8},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/codit/ElloumiSR22,
author = {Hejer Elloumi and
Dorra Sellami and
Hassan Rabah},
title = {A Flexible Hardware Accelerator for Morphological Filters on {FPGA}},
booktitle = {CoDIT},
pages = {550--555},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/dac/PengHCLGLJWBLD22,
author = {Hongwu Peng and
Shaoyi Huang and
Shiyang Chen and
Bingbing Li and
Tong Geng and
Ang Li and
Weiwen Jiang and
Wujie Wen and
Jinbo Bi and
Hang Liu and
Caiwen Ding},
title = {A length adaptive algorithm-hardware co-design of transformer on {FPGA}
through sparse attention and dynamic pipelining},
booktitle = {{DAC}},
pages = {1135--1140},
publisher = {{ACM}},
year = {2022}
}
@inproceedings{DBLP:conf/date/HanZLZGJ22,
author = {Mingqin Han and
Yilan Zhu and
Qian Lou and
Zimeng Zhou and
Shanqing Guo and
Lei Ju},
title = {coxHE: {A} software-hardware co-design framework for {FPGA} acceleration
of homomorphic computation},
booktitle = {{DATE}},
pages = {1353--1358},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/dsd/Awan22,
author = {Ahsan Javed Awan},
title = {Towards Hardware Support for {FPGA} Resource Elasticity},
booktitle = {{DSD}},
pages = {9--15},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/dsd/HerrmannKSS22,
author = {Viktor Herrmann and
Justin Knapheide and
Fritjof Steinert and
Benno Stabernack},
title = {A {YOLO} v3-tiny {FPGA} Architecture using a Reconfigurable Hardware
Accelerator for Real-time Region of Interest Detection},
booktitle = {{DSD}},
pages = {84--92},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/dsd/SciangulaRBB22,
author = {Gerlando Sciangula and
Francesco Restuccia and
Alessandro Biondi and
Giorgio C. Buttazzo},
title = {Hardware Acceleration of Deep Neural Networks for Autonomous Driving
on FPGA-based SoC},
booktitle = {{DSD}},
pages = {406--414},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/embc/GudurMBAS22,
author = {Venkateshwarlu Yellaswamy Gudur and
Sidharth Maheshwari and
Swati Bhardwaj and
Amit Acharyya and
Rishad A. Shafik},
title = {Hardware-Algorithm Codesign for Fast and Energy Efficient Approximate
String Matching on {FPGA} for Computational Biology},
booktitle = {{EMBC}},
pages = {87--90},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/epia/PereiraSMSDMNMM22,
author = {Pedro Pereira and
Ant{\'{o}}nio Silva and
Rui Machado and
Jo{\~{a}}o Silva and
Dalila Dur{\~{a}}es and
Jos{\'{e}} Machado and
Paulo Novais and
Jo{\~{a}}o Monteiro and
Pedro Melo{-}Pinto and
Duarte Fernandes},
title = {Comparison of Different Deployment Approaches of FPGA-Based Hardware
Accelerator for 3D Object Detection Models},
booktitle = {{EPIA}},
series = {Lecture Notes in Computer Science},
volume = {13566},
pages = {285--296},
publisher = {Springer},
year = {2022}
}
@inproceedings{DBLP:conf/fpga/GaoWS22,
author = {Yizhao Gao and
Song Wang and
Hayden Kwok{-}Hay So},
title = {{REMOT:} {A} Hardware-Software Architecture for Attention-Guided Multi-Object
Tracking with Dynamic Vision Sensors on FPGAs},
booktitle = {{FPGA}},
pages = {158--168},
publisher = {{ACM}},
year = {2022}
}
@inproceedings{DBLP:conf/fpga/LiuOGB22,
author = {Yanqi Liu and
Anthony Opipari and
Th{\'{e}}o Gu{\'{e}}rin and
Ruth Iris Bahar},
title = {Hardware Acceleration of Nonparametric Belief Propagation for Efficient
Robot Manipulation},
booktitle = {{FPGA}},
pages = {51},
publisher = {{ACM}},
year = {2022}
}
@inproceedings{DBLP:conf/fpga/ShadabZGAL22,
author = {Rakin Muhammad Shadab and
Yu Zou and
Sanjay Gandham and
Amro Awad and
Mingjie Lin},
title = {{HMT:} {A} Hardware-Centric Hybrid Bonsai Merkle Tree Algorithm for
High-Performance Authentication},
booktitle = {{FPGA}},
pages = {52},
publisher = {{ACM}},
year = {2022}
}
@inproceedings{DBLP:conf/fpl/ArthantoO022,
author = {Yashael Faith Arthanto and
David Ojika and
Joo{-}Young Kim},
title = {{FSHMEM:} Supporting Partitioned Global Address Space on FPGAs for
Large-Scale Hardware Acceleration Infrastructure},
booktitle = {{FPL}},
pages = {218--224},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/fpl/WangZCYCZWCB22,
author = {Zelin Wang and
Ke Zhang and
Yisong Chang and
Yanlong Yin and
Yuxiao Chen and
Ran Zhao and
Songyue Wang and
Mingyu Chen and
Yungang Bao},
title = {{FPL} Demo: {SERVE:} Agile Hardware Development Platform with Cloud
{IDE} and Cloud FPGAs},
booktitle = {{FPL}},
pages = {471},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/fpt/SouvatzoglouAAV22,
author = {Ioanna Souvatzoglou and
Dimitris Agiakatsikas and
George Antonopoulos and
Vasileios Vlagkoulis and
Aitzan Sari and
Athanasios Papadimitriou and
Mihalis Psarakis},
title = {The Impact of Hardware Folding on Dependability in Spaceborne FPGA-based
Neural Networks},
booktitle = {{FPT}},
pages = {1},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/fpt/YaoZ22,
author = {Shangshang Yao and
Liang Zhang},
title = {Hardware-Efficient FPGA-Based Approximate Multipliers for Error-Tolerant
Computing},
booktitle = {{FPT}},
pages = {1--8},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/gecco/0001FB22,
author = {J{\"{o}}rn Hoffmann and
Clemens Fritzsch and
Martin Bogdan},
title = {CoBEA: framework for evolving hardware by direct manipulation of {FPGA}
bitstreams},
booktitle = {{GECCO} Companion},
pages = {112--115},
publisher = {{ACM}},
year = {2022}
}
@inproceedings{DBLP:conf/heart/KarleKP022,
author = {Christian Maximilian Karle and
Marius Kreutzer and
Johannes Pfau and
J{\"{u}}rgen Becker},
title = {A hardware/software co-design approach to prototype 6G mobile applications
inside the {GNU} Radio {SDR} Ecosystem using {FPGA} hardware accelerators},
booktitle = {{HEART}},
pages = {33--41},
publisher = {{ACM}},
year = {2022}
}
@inproceedings{DBLP:conf/hotchips/ShumarayevCHK22,
author = {Sergey Y. Shumarayev and
Allen Chan and
Tim Hoang and
Robert Keller},
title = {Heterogenous Integration Enables {FPGA} Based Hardware Acceleration
for {RF} Applications},
booktitle = {{HCS}},
pages = {1--20},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/hpec/ChenLHH22,
author = {Shaofen Chen and
Haiyan Lin and
Wenjin Huang and
Yihua Huang},
title = {Hardware Design and Implementation of Classic McEliece Post-Quantum
Cryptosystem Based on {FPGA}},
booktitle = {{HPEC}},
pages = {1--6},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/ic3i/KumarSMBTK22,
author = {Keshav Kumar and
Vijay Singh and
Gaurav Mishra and
Bellam Ravindra Babu and
Nandita Tripathi and
Pramod Kumar},
title = {Power-Efficient Secured Hardware Design of {AES} Algorithm on High
Performance {FPGA}},
booktitle = {{IC3I}},
pages = {1634--1637},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/icce-tw/JiangWWHF22,
author = {Ko{-}Yi Jiang and
Hsing{-}Yao Wang and
Chung{-}Bin Wu and
Yin{-}Tsung Hwang and
Chih{-}Peng Fan},
title = {Quantized Lite Convolutional Neural Network Hardware Accelerator Design
with {FPGA} for Face Direction Recognition},
booktitle = {{ICCE-TW}},
pages = {61--62},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/iccel/WuWL22,
author = {Chung{-}Bin Wu and
Yu{-}Hu Wu and
Yi{-}Yen Lai},
title = {{AI} Crowd Control Detection System Implemented on {FPGA} Hardware
Development Platform},
booktitle = {{ICCE}},
pages = {1--4},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/icic/YuMZ22,
author = {Naizhao Yu and
Xiao Min and
Liang Zhao},
title = {A Hardware Implementation Method of Radar Video Scanning Transformation
Based on Dual {FPGA}},
booktitle = {{ICIC} {(1)}},
series = {Lecture Notes in Computer Science},
volume = {13393},
pages = {363--375},
publisher = {Springer},
year = {2022}
}
@inproceedings{DBLP:conf/icm2/MassoudASE22,
author = {Essraa Massoud and
Mohamed Abdelsalam and
Mona Safar and
M. Watheq El{-}Kharashi},
title = {A Reusable UVM-SystemC Verification Environment for Simulation, Hardware
Emulation, and {FPGA} Prototyping: Case Studies},
booktitle = {{ICM}},
pages = {38--41},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/icm2/YacoubISMR22,
author = {Mohammed H. Yacoub and
Samar M. Ismail and
Lobna A. Said and
Ahmed H. Madian and
Ahmed G. Radwan},
title = {Generic Hardware Realization of {K} Nearest Neighbors on {FPGA}},
booktitle = {{ICM}},
pages = {169--172},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/icppw/ShangZLZQ022,
author = {Jiangwei Shang and
Zhan Zhang and
Chuanyou Li and
Kun Zhang and
Lei Qian and
Hongwei Liu},
title = {A Software/Hardware Co-design Local Irregular Sparsity Method for
Accelerating CNNs on {FPGA}},
booktitle = {{ICPP} Workshops},
pages = {25:1--25:7},
publisher = {{ACM}},
year = {2022}
}
@inproceedings{DBLP:conf/iecon/RobertMCG22,
author = {T{\'{e}}o Robert and
Romain Month{\'{e}}ard and
Valentin Combet and
Mathieu Gavelle},
title = {Hardware-In-the-Loop Simulation of a High Frequency Interleaved Converter
based on a Low-Cost {FPGA} Platform},
booktitle = {{IECON}},
pages = {1--6},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/iftc/YangC22,
author = {Dong Yang and
Li Chen},
title = {FPGA-Based Hardware Implementation of {JPEG} {XS} Encoder},
booktitle = {{IFTC}},
series = {Communications in Computer and Information Science},
volume = {1766},
pages = {191--202},
publisher = {Springer},
year = {2022}
}
@inproceedings{DBLP:conf/ipps/ClausingP22,
author = {Lennart Clausing and
Marco Platzner},
title = {ReconOS\({}^{\mbox{64}}\): {A} Hardware Operating System for Modern
Platform FPGAs with 64-Bit Support},
booktitle = {{IPDPS} Workshops},
pages = {120--127},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/ipps/DiaconuPBL22,
author = {Dana Diaconu and
Lucian Petrica and
Michaela Blott and
Miriam Leeser},
title = {Machine Learning Aided Hardware Resource Estimation for {FPGA} {DNN}
Implementations},
booktitle = {{IPDPS} Workshops},
pages = {77--83},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/iscas/MansooriC22,
author = {Mohammad Amir Mansoori and
Mario R. Casu},
title = {HLS-based dataflow hardware architecture for Support Vector Machine
in {FPGA}},
booktitle = {{ISCAS}},
pages = {41--45},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/iscas/SuzukiT22,
author = {Haruto Suzuki and
Hiroyuki Torikai},
title = {A Novel Hardware-Efficient Network of Ergodic Cellular Automaton Neuron
Models and its On-FPGA Learning},
booktitle = {{ISCAS}},
pages = {2266--2270},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/ises/SurajWR22,
author = {Alavala Venkata Suraj and
Shaik Mohammed Waseem and
Subir Kumar Roy},
title = {Resource Constrained Hardware Architecture for Training Deep Neural
Networks at the Edge - {FPGA} Implementation},
booktitle = {iSES},
pages = {358--361},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/isocc/ChenSCCYLLLY22,
author = {Yixiao Chen and
Jinfeng Song and
Shuai Chen and
Yuan Cao and
Jing Ye and
Huawei Li and
Xiaowei Li and
Xin Lou and
Enyi Yao},
title = {Exploring the high-throughput and low-delay hardware design of {SM4}
on {FPGA}},
booktitle = {{ISOCC}},
pages = {211--212},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/isocc/DasJ22,
author = {Monalisa Das and
Babita Jajodia},
title = {Hardware Design of Optimized Large Integer Schoolbook Polynomial Multiplications
on {FPGA}},
booktitle = {{ISOCC}},
pages = {65--66},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/isocc/DasJ22a,
author = {Monalisa Das and
Babita Jajodia},
title = {{FPGA} Implementation of Hybrid Karatsuba Multiplications for {NIST}
Post-Quantum Cryptographic Hardware Primitives},
booktitle = {{ISOCC}},
pages = {81--82},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/isocc/ShiomiT22,
author = {Yuta Shiomi and
Hiroyuki Torikai},
title = {A hardware-efficient ergodic sequential logic neuron network for brain
prosthetic {FPGA}},
booktitle = {{ISOCC}},
pages = {276--277},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/isvlsi/CarpegnaSC22,
author = {Alessio Carpegna and
Alessandro Savino and
Stefano Di Carlo},
title = {Spiker: an FPGA-optimized Hardware accelerator for Spiking Neural
Networks},
booktitle = {{ISVLSI}},
pages = {14--19},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/isvlsi/LiLXW22,
author = {Binjing Li and
Siyuan Lu and
Keli Xie and
Zhongfeng Wang},
title = {Accelerating {NLP} Tasks on {FPGA} with Compressed {BERT} and a Hardware-Oriented
Early Exit Method},
booktitle = {{ISVLSI}},
pages = {410--413},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/isvlsi/LuJJHS22,
author = {Qing Lu and
Weiwen Jiang and
Meng Jiang and
Jingtong Hu and
Yiyu Shi},
title = {Hardware/Software Co-Exploration for Graph Neural Architectures on
FPGAs},
booktitle = {{ISVLSI}},
pages = {358--362},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/isvlsi/MatrangoloMNO22,
author = {Paul{-}Antoine Matrangolo and
C{\'{e}}dric Marchand and
David Navarro and
Ian O'Connor},
title = {Hardware Emulation of FeFET On {FPGA}},
booktitle = {{ISVLSI}},
pages = {380--385},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/iwssip/IbroM22a,
author = {Marsida Ibro and
Galia Marinova},
title = {Hardware Encryption logic on {FPGA} and Power Consumption},
booktitle = {{IWSSIP}},
pages = {1--4},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/lascas/YashTJ22,
author = {Palak Yash and
Mansi Thakare and
Babita Jajodia},
title = {Optimized Hardware Implementation of Vedic Binary Multiplier using
Nikhilam Sutra on {FPGA}},
booktitle = {{LASCAS}},
pages = {1--4},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/mcsoc/RR22,
author = {Soujanya S. R and
Madhav Rao},
title = {Hardware characterization of Integer-Net based seizure detection models
on {FPGA}},
booktitle = {MCSoC},
pages = {224--231},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/mcsoc/SunFW22,
author = {Wei{-}Che Sun and
Chih{-}Peng Fan and
Chung{-}Bin Wu},
title = {Design and {FPGA} Implementation of Lite Convolutional Neural Network
Based Hardware Accelerator for Ocular Biometrics Recognition Technology},
booktitle = {MCSoC},
pages = {278--283},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/meco/AftowiczLL22,
author = {Marcin Aftowicz and
Kai Lehniger and
Peter Langendoerfer},
title = {Scalable {FPGA} Hardware Accelerator for {SVM} Inference},
booktitle = {{MECO}},
pages = {1--4},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/prime/SangiovanniSC22,
author = {Mario Andrea Sangiovanni and
Fanny Spagnolo and
Pasquale Corsonello},
title = {Hardware-Oriented Multi-Exposure Fusion Approach for Real-Time Video
Processing on {FPGA}},
booktitle = {{PRIME}},
pages = {129--132},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/pris2/LiuD022,
author = {Xiaojuan Liu and
Jietao Diao and
Nan Li},
title = {{FPGA} hardware implementation of Q-learning algorithm with low resource
consumption},
booktitle = {{PRIS}},
pages = {8--13},
publisher = {{ACM}},
year = {2022}
}
@inproceedings{DBLP:conf/rev/CristeaB22,
author = {Andreea Cristina Suiu Cristea and
Alexandra Balan},
title = {{AES} Hardware Implementation Based on {FPGA} with Improved Throughput},
booktitle = {{REV}},
series = {Lecture Notes in Networks and Systems},
volume = {524},
pages = {41--50},
publisher = {Springer},
year = {2022}
}
@inproceedings{DBLP:conf/rivf/NghiT22,
author = {Huynh Phuc Nghi and
Tran Ngoc Thinh},
title = {A CNN-Based Vehicle Identification Solution in Parking System With
Hardware Accelerator on {FPGA}},
booktitle = {{RIVF}},
pages = {518--523},
publisher = {{IEEE}},
year = {2022}
}
@inproceedings{DBLP:conf/spa/SzolcK22,
author = {Hubert Szolc and
Tomasz Kryjak},
title = {Hardware-in-the-loop simulation of a {UAV} autonomous landing algorithm
implemented in SoC {FPGA}},
booktitle = {{SPA}},
pages = {135--140},
publisher = {{IEEE}},
year = {2022}
}
@article{DBLP:journals/corr/abs-2201-06993,
author = {Alessio Carpegna and
Alessandro Savino and
Stefano Di Carlo},
title = {FPGA-optimized Hardware acceleration for Spiking Neural Networks},
journal = {CoRR},
volume = {abs/2201.06993},
year = {2022}
}
@article{DBLP:journals/corr/abs-2201-09670,
author = {Yu Wang and
Wujun Xie and
Haochang Chen and
David Day{-}Uei Li},
title = {Low hardware consumption, resolution-configurable Gray code oscillator
time-to-digital converters implemented in 16nm, 20nm and 28nm FPGAs},
journal = {CoRR},
volume = {abs/2201.09670},
year = {2022}
}
@article{DBLP:journals/corr/abs-2207-04625,
author = {Yashael Faith Arthanto and
David Ojika and
Joo{-}Young Kim},
title = {{FSHMEM:} Supporting Partitioned Global Address Space on FPGAs for
Large-Scale Hardware Acceleration Infrastructure},
journal = {CoRR},
volume = {abs/2207.04625},
year = {2022}
}
@article{DBLP:journals/corr/abs-2207-12198,
author = {Hubert Szolc and
Tomasz Kryjak},
title = {Hardware-in-the-loop simulation of a {UAV} autonomous landing algorithm
implemented in SoC {FPGA}},
journal = {CoRR},
volume = {abs/2207.12198},
year = {2022}
}
@article{DBLP:journals/corr/abs-2208-03646,
author = {Hongwu Peng and
Shaoyi Huang and
Shiyang Chen and
Bingbing Li and
Tong Geng and
Ang Li and
Weiwen Jiang and
Wujie Wen and
Jinbo Bi and
Hang Liu and
Caiwen Ding},
title = {A Length Adaptive Algorithm-Hardware Co-design of Transformer on {FPGA}
Through Sparse Attention and Dynamic Pipelining},
journal = {CoRR},
volume = {abs/2208.03646},
year = {2022}
}
@article{DBLP:journals/corr/abs-2210-09481,
author = {Ramchander Rao Bhaskara and
Manoranjan Majji},
title = {{FPGA} Hardware Acceleration for Feature-Based Relative Navigation
Applications},
journal = {CoRR},
volume = {abs/2210.09481},
year = {2022}
}
@article{DBLP:journals/corr/abs-2212-09460,
author = {Mohamed Alshemi and
Sherif M. Saif and
Mohamed Taher},
title = {Hardware Acceleration of Lane Detection Algorithm: {A} {GPU} Versus
{FPGA} Comparison},
journal = {CoRR},
volume = {abs/2212.09460},
year = {2022}
}
@phdthesis{DBLP:phd/hal/Baumela21,
author = {Thomas Baumela},
title = {Integrating devices in {FPGA} using an end-to-end hardware/software
co-designedmessage-based approach. (Int{\'{e}}gration mat{\'{e}}riel/logiciel
sur {FPGA} {\`{a}} l'aide d'une strat{\'{e}}gie de communication
par messages)},
school = {Grenoble Alpes University, France},
year = {2021}
}
@phdthesis{DBLP:phd/it/Stornaiuolo21,
author = {Luca Stornaiuolo},
title = {Hardware/software co-design for scientific computing and convolutional
neural networks on FPGA-based embedded architectures},
school = {Polytechnic University of Milan, Italy},
year = {2021}
}
@phdthesis{DBLP:phd/us/Huang21a,
author = {Sitao Huang},
title = {High-efficiency and high-usability heterogeneous hardware acceleration
with FPGAs},
school = {University of Illinois Urbana-Champaign, {USA}},
year = {2021}
}
@article{DBLP:journals/access/El-MaksoudEKM21,
author = {Ahmed J. Abd El{-}Maksoud and
Mohamed Ebbed and
Ahmed H. Khalil and
Hassan Mostafa},
title = {Power Efficient Design of High-Performance Convolutional Neural Networks
Hardware Accelerator on {FPGA:} {A} Case Study With GoogLeNet},
journal = {{IEEE} Access},
volume = {9},
pages = {151897--151911},
year = {2021}
}
@article{DBLP:journals/access/GomezNDG21,
author = {Jorge Torres G{\'{o}}mez and
Yannelys Virginia Jerez Naranjo and
Falko Dressler and
M. Julia Fern{\'{a}}ndez{-}Getino Garc{\'{\i}}a},
title = {Undergraduate Curriculum to Teach and Provide Research Skills on Hardware
Design for {SDR} Applications in {FPGA} Technology},
journal = {{IEEE} Access},
volume = {9},
pages = {93967--93975},
year = {2021}
}
@article{DBLP:journals/access/Huang21a,
author = {Chun{-}Hsian Huang},
title = {An FPGA-Based Hardware/Software Design Using Binarized Neural Networks
for Agricultural Applications: {A} Case Study},
journal = {{IEEE} Access},
volume = {9},
pages = {26523--26531},
year = {2021}
}
@article{DBLP:journals/access/KhanLH21,
author = {Safiullah Khan and
Wai{-}Kong Lee and
Seong Oun Hwang},
title = {A Flexible Gimli Hardware Implementation in {FPGA} and Its Application
to {RFID} Authentication Protocols},
journal = {{IEEE} Access},
volume = {9},
pages = {105327--105340},
year = {2021}
}
@article{DBLP:journals/access/YouW21,
author = {Weijie You and
Chang Wu},
title = {{RSNN:} {A} Software/Hardware Co-Optimized Framework for Sparse Convolutional
Neural Networks on FPGAs},
journal = {{IEEE} Access},
volume = {9},
pages = {949--960},
year = {2021}
}
@article{DBLP:journals/algorithms/BhattiG21,
author = {Faraz Bhatti and
Thomas Greiner},
title = {Design of an {FPGA} Hardware Optimizing the Performance and Power
Consumption of a Plenoptic Camera Depth Estimation Algorithm},
journal = {Algorithms},
volume = {14},
number = {7},
pages = {215},
year = {2021}
}
@article{DBLP:journals/asc/OrtizMBPMM21,
author = {Alexandro Ortiz and
Efrain Mendez and
David Balderas and
Pedro Ponce and
Israel Macias and
Arturo Molina},
title = {Hardware implementation of metaheuristics through LabVIEW {FPGA}},
journal = {Appl. Soft Comput.},
volume = {113},
number = {Part},
pages = {107908},
year = {2021}
}
@article{DBLP:journals/elektrik/KashifC21,
author = {Muhammad Kashif and
Ihsan {\c{C}}i{\c{c}}ek},
title = {Field-programmable gate array {(FPGA)} hardware design and implementation
of a new area efficient elliptic curve crypto-processor},
journal = {Turkish J. Electr. Eng. Comput. Sci.},
volume = {29},
number = {4},
pages = {2127--2139},
year = {2021}
}
@article{DBLP:journals/esl/UllahNK21,
author = {Salim Ullah and
Tuan Duy Anh Nguyen and
Akash Kumar},
title = {Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware
Accelerators},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {13},
number = {2},
pages = {41--44},
year = {2021}
}
@article{DBLP:journals/ijhpsa/Adam21,
author = {George K. Adam},
title = {Multithreading on reconfigurable hardware: a performance evaluation
approach of a multicore {FPGA} architecture},
journal = {Int. J. High Perform. Syst. Archit.},
volume = {10},
number = {2},
pages = {105--116},
year = {2021}
}
@article{DBLP:journals/ijin/LeelavathiSV21,
author = {G. Leelavathi and
K. Shaila and
K. R. Venugopal},
title = {Hardware performance analysis of {RSA} cryptosystems on {FPGA} for
wireless sensor nodes},
journal = {Int. J. Intell. Networks},
volume = {2},
pages = {184--194},
year = {2021}
}
@article{DBLP:journals/ijon/HuangYRD21,
author = {Hui Huang and
Jing Yang and
Hai{-}Jun Rong and
Shaoyi Du},
title = {A generic FPGA-based hardware architecture for recursive least mean
p-power extreme learning machine},
journal = {Neurocomputing},
volume = {456},
pages = {421--435},
year = {2021}
}
@article{DBLP:journals/integration/VuNN21,
author = {Hoang Gia Vu and
Takashi Nakada and
Yasuhiko Nakashima},
title = {Efficient hardware task migration for heterogeneous {FPGA} computing
using HDL-based checkpointing},
journal = {Integr.},
volume = {77},
pages = {180--192},
year = {2021}
}
@article{DBLP:journals/jaiscr/KopczynskiG21,
author = {Maciej Kopczynski and
Tomasz Grzes},
title = {Hardware Rough Set Processor Parallel Architecture in {FPGA} for Finding
Core in Big Datasets},
journal = {J. Artif. Intell. Soft Comput. Res.},
volume = {11},
number = {2},
pages = {99--110},
year = {2021}
}
@article{DBLP:journals/jcsc/GafsiAHMM21,
author = {Mohamed Gafsi and
Nessrine Abbassi and
Mohamed Ali Hajjaji and
Jihene Malek and
Abdellatif Mtibaa},
title = {Xilinx Zynq {FPGA} for Hardware Implementation of a Chaos-Based Cryptosystem
for Real-Time Image Protection},
journal = {J. Circuits Syst. Comput.},
volume = {30},
number = {11},
pages = {2150204:1--2150204:26},
year = {2021}
}
@article{DBLP:journals/jrtip/BoukhtacheBGB21,
author = {Seyfeddine Boukhtache and
Beno{\^{\i}}t Blaysat and
Michel Gr{\'{e}}diac and
Fran{\c{c}}ois Berry},
title = {FPGA-based architecture for bi-cubic interpolation: the best trade-off
between precision and hardware resource consumption},
journal = {J. Real Time Image Process.},
volume = {18},
number = {3},
pages = {901--911},
year = {2021}
}
@article{DBLP:journals/mam/HanL21a,
author = {Dong Han and
Gang Li},
title = {Development of smart english classroom system based on {FPGA} software
and hardware co-simulation test},
journal = {Microprocess. Microsystems},
volume = {81},
pages = {103774},
year = {2021}
}
@article{DBLP:journals/mam/JinJ21,
author = {Shujiao Jin and
Hu Jin},
title = {Optimization of Motion Estimation Algorithm Based on {FPGA} Hardware
System and Video Tracking},
journal = {Microprocess. Microsystems},
volume = {82},
pages = {103867},
year = {2021}
}
@article{DBLP:journals/mam/JingX21,
author = {Hu Jing and
Xing Xiaoqiong},
title = {Sports image detection based on {FPGA} hardware system and particle
swarm algorithm},
journal = {Microprocess. Microsystems},
volume = {80},
pages = {103348},
year = {2021}
}
@article{DBLP:journals/mta/GuptaJVKK21,
author = {Namit Gupta and
Arpit Jain and
Kunwar Singh Vaisla and
Adesh Kumar and
Rajeev Kumar},
title = {Performance analysis of {DSDV} and {OLSR} wireless sensor network
routing protocols using {FPGA} hardware and machine learning},
journal = {Multim. Tools Appl.},
volume = {80},
number = {14},
pages = {22301--22319},
year = {2021}
}
@article{DBLP:journals/nca/ShymkovychTK21,
author = {Volodymyr M. Shymkovych and
Sergii Telenyk and
Petro I. Kravets},
title = {Hardware implementation of radial-basis neural networks with Gaussian
activation functions on {FPGA}},
journal = {Neural Comput. Appl.},
volume = {33},
number = {15},
pages = {9467--9479},
year = {2021}
}
@article{DBLP:journals/npl/SateesanSGV21,
author = {Arish Sateesan and
Sharad Sinha and
Smitha K. G. and
A. P. Vinod},
title = {A Survey of Algorithmic and Hardware Optimization Techniques for Vision
Convolutional Neural Networks on FPGAs},
journal = {Neural Process. Lett.},
volume = {53},
number = {3},
pages = {2331--2377},
year = {2021}
}
@article{DBLP:journals/queue/Mattioli21,
author = {Michael Mattioli},
title = {FPGAs in Client Compute Hardware: Despite certain challenges, FPGAs
provide security and performance benefits over ASICs},
journal = {{ACM} Queue},
volume = {19},
number = {6},
pages = {66--88},
year = {2021}
}
@article{DBLP:journals/remotesensing/RapuanoMPDFGF21,
author = {Emilio Rapuano and
Gabriele Meoni and
Tommaso Pacini and
Gianmarco Dinelli and
Gianluca Furano and
Gianluca Giuffrida and
Luca Fanucci},
title = {An FPGA-Based Hardware Accelerator for CNNs Inference on Board Satellites:
Benchmarking with Myriad 2-Based Solution for the CloudScout Case
Study},
journal = {Remote. Sens.},
volume = {13},
number = {8},
pages = {1518},
year = {2021}
}
@article{DBLP:journals/tches/XingL21,
author = {Yufei Xing and
Shuguo Li},
title = {A Compact Hardware Implementation of CCA-Secure Key Exchange Mechanism
{CRYSTALS-KYBER} on {FPGA}},
journal = {{IACR} Trans. Cryptogr. Hardw. Embed. Syst.},
volume = {2021},
number = {2},
pages = {328--356},
year = {2021}
}
@article{DBLP:journals/tecs/SahaS21,
author = {Debasri Saha and
Susmita Sur{-}Kolay},
title = {Minimization of {WCRT} with Recovery Assurance from Hardware Trojans
for Tasks on FPGA-based Cloud},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {20},
number = {1},
pages = {1:1--1:25},
year = {2021}
}
@article{DBLP:journals/tecs/ZhangWZTH21,
author = {Xinyi Zhang and
Yawen Wu and
Peipei Zhou and
Xulong Tang and
Jingtong Hu},
title = {Algorithm-hardware Co-design of Attention Mechanism on {FPGA} Devices},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {20},
number = {5s},
pages = {71:1--71:24},
year = {2021}
}
@article{DBLP:journals/tetc/TsigkanosKTP21,
author = {Antonis Tsigkanos and
Nektarios Kranitis and
George Theodorou and
Antonis M. Paschalis},
title = {A 3.3 Gbps {CCSDS} 123.0-B-1 Multispectral {\&} Hyperspectral
Image Compression Hardware Accelerator on a Space-Grade {SRAM} {FPGA}},
journal = {{IEEE} Trans. Emerg. Top. Comput.},
volume = {9},
number = {1},
pages = {90--103},
year = {2021}
}
@article{DBLP:journals/tie/DaiKQC21,
author = {Xunhua Dai and
Chenxu Ke and
Quan Quan and
Kai{-}Yuan Cai},
title = {Simulation Credibility Assessment Methodology With FPGA-based Hardware-in-the-Loop
Platform},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {68},
number = {4},
pages = {3282--3291},
year = {2021}
}
@article{DBLP:journals/tie/HosseinabadiBS21,
author = {Amir Hossein Hadi Hosseinabadi and
David G. Black and
Septimiu E. Salcudean},
title = {Ultra Low-Noise FPGA-Based Six-Axis Optical Force-Torque Sensor: Hardware
and Software},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {68},
number = {10},
pages = {10207--10217},
year = {2021}
}
@article{DBLP:journals/tsg/DuanHD21,
author = {Tong Duan and
Zhen Huang and
Venkata Dinavahi},
title = {{RTCE:} Real-Time Co-Emulation Framework for EMT-Based Power System
and Communication Network on FPGA-MPSoC Hardware Architecture},
journal = {{IEEE} Trans. Smart Grid},
volume = {12},
number = {3},
pages = {2544--2553},
year = {2021}
}
@article{DBLP:journals/tvlsi/BoukhtacheBGB21,
author = {Seyfeddine Boukhtache and
Beno{\^{\i}}t Blaysat and
Michel Gr{\'{e}}diac and
Fran{\c{c}}ois Berry},
title = {Alternatives to Bicubic Interpolation Considering {FPGA} Hardware
Resource Consumption},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {247--258},
year = {2021}
}
@inproceedings{DBLP:conf/IEEEssd/BouguezziFS21a,
author = {Safa Bouguezzi and
Hassene Faiedh and
Chokri Souani},
title = {Hardware Implementation of Tanh Exponential Activation Function using
{FPGA}},
booktitle = {{SSD}},
pages = {1020--1025},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/IEEEssd/MaraouiMBAKM21,
author = {Amna Maraoui and
Seifeddine Messaoud and
Soulef Bouaafia and
Ahmed Chiheb Ammari and
Lazhar Khriji and
Mohsen Machhout},
title = {{PYNQ} {FPGA} Hardware implementation of LeNet-5-Based Traffic Sign
Recognition Application},
booktitle = {{SSD}},
pages = {1004--1009},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/aicas/WangCX21,
author = {Hao Wang and
Shan Cao and
Shugong Xu},
title = {A Real-Time Face Recognition System by Efficient Hardware-Software
Co-Design on {FPGA} SoCs},
booktitle = {{AICAS}},
pages = {1--2},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/applepies/CominoPRF21,
author = {Corrado Comino and
Tommaso Pacini and
Emilio Rapuano and
Luca Fanucci},
title = {Design and Implementation of an FPGA-Based {CNN} Hardware Accelerator
Using Partial Reconfigurability: The CloudScout Case Study},
booktitle = {ApplePies},
series = {Lecture Notes in Electrical Engineering},
volume = {866},
pages = {187--193},
publisher = {Springer},
year = {2021}
}
@inproceedings{DBLP:conf/applepies/FlorianVGCMCCC21,
author = {Werner Florian and
Bruno Valinoti and
Luis Guillermo Garc{\'{\i}}a and
Marcos Cervetto and
Edgardo Marchi and
Maria Liz Crespo and
Sergio Carrato and
Andres Cicuttin},
title = {An Open-Source Hardware/Software Architecture for Remote Control of
SoC-FPGA Based Systems},
booktitle = {ApplePies},
series = {Lecture Notes in Electrical Engineering},
volume = {866},
pages = {69--75},
publisher = {Springer},
year = {2021}
}
@inproceedings{DBLP:conf/asap/WangL21,
author = {Yu Wang and
Peng Li},
title = {Algorithm and Hardware Co-Design for {FPGA} Acceleration of Hamiltonian
Monte Carlo Based No-U-Turn Sampler},
booktitle = {{ASAP}},
pages = {9--16},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/asscc/BaiFSKZ21,
author = {Jinyu Bai and
Yunqian Fan and
Sifan Sun and
Wang Kang and
Weisheng Zhao},
title = {Tiny neural network search and implementation for embedded {FPGA:}
a software-hardware co-design approach},
booktitle = {{A-SSCC}},
pages = {1--3},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/ccgrid/WangFLT00D21,
author = {Yuke Wang and
Boyuan Feng and
Gushu Li and
Georgios Tzimpragos and
Lei Deng and
Yuan Xie and
Yufei Ding},
title = {TiAcc: Triangle-inequality based Hardware Accelerator for K-means
on FPGAs},
booktitle = {{CCGRID}},
pages = {133--142},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/dsd/KreddigCMS21,
author = {Arne Kreddig and
Simon Conrady and
Manu Manuel and
Walter Stechele},
title = {A Framework for Hardware-Accelerated Design Space Exploration for
Approximate Computing on {FPGA}},
booktitle = {{DSD}},
pages = {1--8},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/fccm/KhouyganiMBC21,
author = {Verjina Torosian Khouygani and
Shahnam Mirzaei and
Christian Beck and
Debi Prasad Choudhary},
title = {An {FPGA} Based Hardware Accelerated Framework for Solar Spectra Matching
with Parameterized Matched Filter {IP} Core},
booktitle = {{FCCM}},
pages = {278},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/fie/LiNMQ21,
author = {Ying Li and
Jianwei Niu and
Simbarashe Matutu and
Qianben Qi},
title = {Teaching practice reforms towards software-hardware collaboration
in computer system ability training-Taking {FPGA} Design course as
an example},
booktitle = {{FIE}},
pages = {1--5},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/fpl/NgoTMP21,
author = {Duc{-}Minh Ngo and
Andriy Temko and
Colin C. Murphy and
Emanuel M. Popovici},
title = {{FPGA} Hardware Acceleration Framework for Anomaly-based Intrusion
Detection System in IoT},
booktitle = {{FPL}},
pages = {69--75},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/fpt/AttiaB21,
author = {Sameh Attia and
Vaughn Betz},
title = {StateLink: {FPGA} System Debugging via Flexible Simulation/Hardware
Integration},
booktitle = {{FPT}},
pages = {1--10},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/fpt/SuhMNVKCS21,
author = {Han{-}Sok Suh and
Jian Meng and
Ty Nguyen and
Shreyas K. Venkataramanaiah and
Vijay Kumar and
Yu Cao and
Jae{-}sun Seo},
title = {Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection
on Resource-Constrained {FPGA}},
booktitle = {{FPT}},
pages = {1--9},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/fpt/ZhangFO21,
author = {Nathan Zhang and
Matthew Feldman and
Kunle Olukotun},
title = {High performance lattice regression on FPGAs via a high level hardware
description language},
booktitle = {{FPT}},
pages = {1--10},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/icaiic/MunKK21a,
author = {Gwonhan Mun and
Hee Wook Kim and
Daeho Kim},
title = {{CNPC} deinterleaver implementation to increase hardware logic utilization
on {FPGA}},
booktitle = {{ICAIIC}},
pages = {385--389},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/icassp/BhattiG21,
author = {Faraz Bhatti and
Thomas Greiner},
title = {{FPGA} Hardware Design for Plenoptic 3D Image Processing Algorithm
Targeting a Mobile Application},
booktitle = {{ICASSP}},
pages = {7863--7867},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/icbip/XuSLWKZZ21,
author = {Xianfu Xu and
Wenjun Su and
Bin Li and
Yini Wei and
Deyu Kong and
Hongjie Zeng and
Xuejun Zhang},
title = {An FPGA-Based Hardware Accelerator for 2D Labeling},
booktitle = {{ICBIP}},
pages = {72--78},
publisher = {{ACM}},
year = {2021}
}
@inproceedings{DBLP:conf/icce-tw/ChenLW021,
author = {Tzu{-}Chieh Chen and
Yi{-}Jhen Luo and
Wei{-}Chung Wan and
Tsung{-}Han Tsai},
title = {Knee Lift Detection using Convolutional Neural Network Method with
{FPGA} Hardware Design},
booktitle = {{ICCE-TW}},
pages = {1--2},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/iccel/AhmadH21,
author = {Waqar Ahmad and
Ilker Hamzaoglu},
title = {An Efficient Approximate Sum of Absolute Differences Hardware for
FPGAs},
booktitle = {{ICCE}},
pages = {1--5},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/iccp2/ZaporojanCS21,
author = {Sergiu Zaporojan and
Viorel Carbune and
Radu Razvan Slavescu},
title = {Hardware implementation of Hopfield-like neural networks: Quantitative
analysis of {FPGA} approach},
booktitle = {{ICCP}},
pages = {243--250},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/iceei/CAS21,
author = {Ardian Dwi C and
Trio Adiono and
Nana Sutisna},
title = {{FPGA} Based Hardware Accelerator Design for Convolution Process in
Convolutional Neural Network},
booktitle = {{ICEEI}},
pages = {1--5},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/icm2/El-MaksoudGHSAE21,
author = {Ahmed J. Abd El{-}Maksoud and
Amr Gamal and
Aya Hesham and
Gamal Saied and
Mennat{-}Allah Ayman and
Omnia Essam and
Sara M. Mohamed and
Eman El Mandouh and
Ziad Ibrahim and
Sara Mohamed and
Hassan Mostafa},
title = {Hardware-Accelerated {ZYNQ-NET} Convolutional Neural Networks on Virtex-7
{FPGA}},
booktitle = {{ICM}},
pages = {70--73},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/icta3/ChenLZ21,
author = {Xiang Chen and
Jindong Li and
Yong Zhao},
title = {Hardware Resource and Computational Density Efficient {CNN} Accelerator
Design Based on {FPGA}},
booktitle = {{ICTA}},
pages = {204--205},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/igarss/DingZLY21,
author = {Ning Ding and
Zhulin Zong and
Bolun Liu and
Shiwei Yuan},
title = {An {FPGA} Hardware Implementation for Omega-K {SAR} Imaging Algorithm},
booktitle = {{IGARSS}},
pages = {5155--5158},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/isalalife/WhitleyYC21,
author = {Derek Whitley and
Jason Yoder and
Nicklas Carpenter},
title = {Resurrecting {FPGA} Intrinsic Analog Evolvable Hardware},
booktitle = {{ALIFE}},
pages = {106},
publisher = {{MIT} Press},
year = {2021}
}
@inproceedings{DBLP:conf/iscas/AmidOASN21,
author = {Alon Amid and
Albert J. Ou and
Krste Asanovic and
Yakun Sophia Shao and
Borivoje Nikolic},
title = {Vertically Integrated Computing Labs Using Open-Source Hardware Generators
and Cloud-Hosted FPGAs},
booktitle = {{ISCAS}},
pages = {1--5},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/iscas/ZhangLLZNLJ21,
author = {Cong Zhang and
Dongsheng Liu and
Xingjie Liu and
Xuecheng Zou and
Guangda Niu and
Bo Liu and
Quming Jiang},
title = {Towards Efficient Hardware Implementation of {NTT} for Kyber on FPGAs},
booktitle = {{ISCAS}},
pages = {1--5},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/mcsoc/LuZSEM21,
author = {Yufan Lu and
Xiaojun Zhai and
Sangeet Saha and
Shoaib Ehsan and
Klaus D. McDonald{-}Maier},
title = {{FPGA} based Adaptive Hardware Acceleration for Multiple Deep Learning
Tasks},
booktitle = {MCSoC},
pages = {204--209},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/mwscas/ThakareYCJ21,
author = {Mansi Thakare and
Palak Yash and
Debaleena Chakraborty and
Babita Jajodia},
title = {Efficient Hardware Implementation of Cube Architecture using Yavadunam
Sutra on {FPGA}},
booktitle = {{MWSCAS}},
pages = {373--376},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/niles/El-MaksoudMTAEK21,
author = {Ahmed J. Abd El{-}Maksoud and
Abdallah Mohamed and
Ahmed Tarek and
Amr Adel and
Amr Eid and
Farida Khaled and
Fatma Khaled and
Ziad Ibrahim and
Eman El Mandouh and
Hassan Mostafa},
title = {{FPGA} Design of High-Speed Convolutional Neural Network Hardware
Accelerator},
booktitle = {{NILES}},
pages = {376--379},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/pasc/KenterSFA21,
author = {Tobias Kenter and
Adesh Shambhu and
Sara Faghih{-}Naini and
Vadym Aizinger},
title = {Algorithm-hardware co-design of a discontinuous Galerkin shallow-water
model for a dataflow architecture on {FPGA}},
booktitle = {{PASC}},
pages = {13:1--13:11},
publisher = {{ACM}},
year = {2021}
}
@inproceedings{DBLP:conf/sac/SeyoumPBB21,
author = {Biruk B. Seyoum and
Marco Pagani and
Alessandro Biondi and
Giorgio C. Buttazzo},
title = {Automating the design flow under dynamic partial reconfiguration for
hardware-software co-design in {FPGA} SoC},
booktitle = {{SAC}},
pages = {481--490},
publisher = {{ACM}},
year = {2021}
}
@inproceedings{DBLP:conf/sbac-pad/HarisGCAK21,
author = {Jude Haris and
Perry Gibson and
Jos{\'{e}} Cano and
Nicolas Bohm Agostini and
David R. Kaeli},
title = {{SECDA:} Efficient Hardware/Software Co-Design of FPGA-based {DNN}
Accelerators for Edge Inference},
booktitle = {{SBAC-PAD}},
pages = {33--43},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/vdat/KrishnanSS21,
author = {Abi K. Krishnan and
M. H. Supriya and
Nalesh Sivanandan},
title = {A Hardware-Software Co-design based Approach for Development of a
Distributed {DAQ} System using {FPGA}},
booktitle = {{VDAT}},
pages = {1--6},
publisher = {{IEEE}},
year = {2021}
}
@inproceedings{DBLP:conf/vdat/ShekhawatJP21,
author = {Diksha Shekhawat and
Apoorva Jangir and
Jai Gopal Pandey},
title = {A Hardware Generator for Posit Arithmetic and its {FPGA} Prototyping},
booktitle = {{VDAT}},
pages = {1--6},
publisher = {{IEEE}},
year = {2021}
}
@article{DBLP:journals/corr/abs-2101-01745,
author = {Tom Hogervorst and
Tong Dong Qiu and
Giacomo Marchiori and
Alf Birger Rustad and
Markus Blatt and
Razvan Nane},
title = {Hardware Acceleration of {HPC} Computational Flow Dynamics using HBM-enabled
FPGAs},
journal = {CoRR},
volume = {abs/2101.01745},
year = {2021}
}
@article{DBLP:journals/corr/abs-2102-01351,
author = {Olivia Weng and
Alireza Khodamoradi and
Ryan Kastner},
title = {Hardware-efficient Residual Networks for FPGAs},
journal = {CoRR},
volume = {abs/2102.01351},
year = {2021}
}
@article{DBLP:journals/corr/abs-2105-07131,
author = {Amir{-}Hossein Kiamarzi and
Pezhman Torabi and
Reza Sameni},
title = {Hardware Synthesis of State-Space Equations; Application to {FPGA}
Implementation of Shallow and Deep Neural Networks},
journal = {CoRR},
volume = {abs/2105.07131},
year = {2021}
}
@article{DBLP:journals/corr/abs-2109-03276,
author = {V{\'{\i}}ctor Mayoral Vilches and
Giulio Corradi},
title = {Adaptive Computing in Robotics, Leveraging {ROS} 2 to Enable Software-Defined
Hardware for FPGAs},
journal = {CoRR},
volume = {abs/2109.03276},
year = {2021}
}
@article{DBLP:journals/corr/abs-2110-00478,
author = {Jude Haris and
Perry Gibson and
Jos{\'{e}} Cano and
Nicolas Bohm Agostini and
David R. Kaeli},
title = {{SECDA:} Efficient Hardware/Software Co-Design of FPGA-based {DNN}
Accelerators for Edge Inference},
journal = {CoRR},
volume = {abs/2110.00478},
year = {2021}
}
@article{DBLP:journals/corr/abs-2112-12836,
author = {Ahsan Javed Awan and
Fidan Aliyeva},
title = {Hardware Support for {FPGA} Resource Elasticity},
journal = {CoRR},
volume = {abs/2112.12836},
year = {2021}
}
@article{DBLP:journals/iacr/DangMG21,
author = {Viet Ba Dang and
Kamyar Mohajerani and
Kris Gaj},
title = {High-Speed Hardware Architectures and {FPGA} Benchmarking of CRYSTALS-Kyber,
NTRU, and Saber},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {1508},
year = {2021}
}
@article{DBLP:journals/mam/QiY21,
title = {Artificial intelligence enterprise human resource management system
based on {FPGA} high performance computer hardware},
journal = {Microprocess. Microsystems},
volume = {82},
pages = {103876},
year = {2021},
note = {Withdrawn.}
}
@phdthesis{DBLP:phd/basesearch/Gnad20,
author = {Dennis Gnad},
title = {Remote Attacks on {FPGA} Hardware},
school = {Karlsruhe University, Germany},
year = {2020}
}
@phdthesis{DBLP:phd/hal/Pagani20,
author = {Marco Pagani},
title = {Enabling Predictable Hardware Acceleration in Heterogeneous SoC-FPGA
Computing Platforms. (Techniques pour l'am{\'{e}}lioration de
la pr{\'{e}}visibilit{\'{e}} de l'acc{\'{e}}l{\'{e}}ration
mat{\'{e}}rielle pour les plateformes informatiques h{\'{e}}t{\'{e}}rog{\`{e}}nes
SoC-FPGA)},
school = {University of Lille, France},
year = {2020}
}
@phdthesis{DBLP:phd/it/Erdem20,
author = {Ahmet Erdem},
title = {Exploration and mapping of deep neural networks to low-power hardware
accelerators and FPGAs},
school = {Polytechnic University of Milan, Italy},
year = {2020}
}
@phdthesis{DBLP:phd/it/Tucci20,
author = {Lorenzo Di Tucci},
title = {Hugenomic: exploiting FPGAs as hardware accelerators in the genomic
domain},
school = {Polytechnic University of Milan, Italy},
year = {2020}
}
@article{DBLP:journals/access/Al-ShatariHAWT20,
author = {Mohammed Omar Awadh Al{-}Shatari and
Fawnizu Azmadi Hussin and
Azrina Abd Aziz and
Gunawan Witjaksono and
Xuan{-}Tu Tran},
title = {FPGA-Based Lightweight Hardware Architecture of the {PHOTON} Hash
Function for IoT Edge Devices},
journal = {{IEEE} Access},
volume = {8},
pages = {207610--207618},
year = {2020}
}
@article{DBLP:journals/access/AslamJSPF20,
author = {Sohaib Aslam and
Ian K. Jennions and
Mohammad Samie and
Suresh Perinpanayagam and
Yisen Fang},
title = {Ingress of Threshold Voltage-Triggered Hardware Trojan in the Modern
{FPGA} Fabric-Detection Methodology and Mitigation},
journal = {{IEEE} Access},
volume = {8},
pages = {31371--31397},
year = {2020}
}
@article{DBLP:journals/access/KawashimaMT20,
author = {Ichiro Kawashima and
Takashi Morie and
Hakaru Tamukoh},
title = {{FPGA} Implementation of Hardware-Oriented Chaotic Boltzmann Machines},
journal = {{IEEE} Access},
volume = {8},
pages = {204360--204377},
year = {2020}
}
@article{DBLP:journals/access/LedwonCH20,
author = {Morgan Ledwon and
Bruce F. Cockburn and
Jie Han},
title = {High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression
and Decompression Using High-Level Synthesis},
journal = {{IEEE} Access},
volume = {8},
pages = {62207--62217},
year = {2020}
}
@article{DBLP:journals/access/NguyenAH20,
author = {Anh Hoang Ngoc Nguyen and
Masashi Aono and
Yuko Hara{-}Azumi},
title = {FPGA-Based Hardware/Software Co-Design of a Bio-Inspired {SAT} Solver},
journal = {{IEEE} Access},
volume = {8},
pages = {49053--49065},
year = {2020}
}
@article{DBLP:journals/access/SuYYT20,
author = {Yang Su and
Bailong Yang and
Chen Yang and
Luogeng Tian},
title = {FPGA-Based Hardware Accelerator for Leveled Ring-LWE Fully Homomorphic
Encryption},
journal = {{IEEE} Access},
volume = {8},
pages = {168008--168025},
year = {2020}
}
@article{DBLP:journals/access/WangXWLLW20,
author = {Zixiao Wang and
Ke Xu and
Shuaixiao Wu and
Li Liu and
Lingzhi Liu and
Dong Wang},
title = {Sparse-YOLO: Hardware/Software Co-Design of an {FPGA} Accelerator
for YOLOv2},
journal = {{IEEE} Access},
volume = {8},
pages = {116569--116585},
year = {2020}
}
@article{DBLP:journals/access/WangXX20,
author = {Dong Wang and
Jia Xu and
Ke Xu},
title = {An FPGA-Based Hardware Accelerator for Real-Time Block-Matching and
3D Filtering},
journal = {{IEEE} Access},
volume = {8},
pages = {121987--121998},
year = {2020}
}
@article{DBLP:journals/access/YanTZ20,
author = {Weian Yan and
Weiqin Tong and
Xiaoli Zhi},
title = {{FPGAN:} An {FPGA} Accelerator for Graph Attention Networks With Software
and Hardware Co-Optimization},
journal = {{IEEE} Access},
volume = {8},
pages = {171608--171620},
year = {2020}
}
@article{DBLP:journals/access/ZhiCDD20,
author = {Shuaiqing Zhi and
Yani Cui and
Jiaxian Deng and
Wencai Du},
title = {An FPGA-Based Simple {RGB-HSI} Space Conversion Algorithm for Hardware
Image Processing},
journal = {{IEEE} Access},
volume = {8},
pages = {173838--173853},
year = {2020}
}
@article{DBLP:journals/casa/Pham-Quoc20,
author = {Cuong Pham{-}Quoc},
title = {Automatic FPGA-based Hardware Accelerator Design: {A} Case Study with
Image Processing Applications},
journal = {{EAI} Endorsed Trans. Context aware Syst. Appl.},
volume = {7},
number = {20},
pages = {e5},
year = {2020}
}
@article{DBLP:journals/cbm/InamBQO20,
author = {Omair Inam and
Abdul Basit and
Mahmood Qureshi and
Hammad Omer},
title = {FPGA-based hardware accelerator for {SENSE} (a parallel {MR} image
reconstruction method)},
journal = {Comput. Biol. Medicine},
volume = {117},
pages = {103598},
year = {2020}
}
@article{DBLP:journals/darts/RestucciaPBMB20,
author = {Francesco Restuccia and
Marco Pagani and
Alessandro Biondi and
Mauro Marinoni and
Giorgio C. Buttazzo},
title = {Modeling and Analysis of Bus Contention for Hardware Accelerators
in {FPGA} SoCs (Artifact)},
journal = {Dagstuhl Artifacts Ser.},
volume = {6},
number = {1},
pages = {04:1--04:3},
year = {2020}
}
@article{DBLP:journals/esl/KumarML20,
author = {Vikas Kumar and
Mithun Mukherjee and
Jaime Lloret},
title = {A Hardware-Efficient and Reconfigurable {UFMC} Transmitter Architecture
With its {FPGA} Prototype},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {12},
number = {4},
pages = {109--112},
year = {2020}
}
@article{DBLP:journals/jrnal/HondaT20,
author = {Kentaro Honda and
Hakaru Tamukoh},
title = {A Hardware-Oriented Echo State Network and its {FPGA} Implementation},
journal = {J. Robotics Netw. Artif. Life},
volume = {7},
number = {1},
pages = {58--62},
year = {2020}
}
@article{DBLP:journals/jstsp/JainGAFA20,
author = {Akshay Jain and
Pulkit Goel and
Shivam Aggarwal and
Alexander Fell and
Saket Anand},
title = {Symmetric {\textdollar}k{\textdollar}-Means for Deep Neural Network
Compression and Hardware Acceleration on FPGAs},
journal = {{IEEE} J. Sel. Top. Signal Process.},
volume = {14},
number = {4},
pages = {737--749},
year = {2020}
}
@article{DBLP:journals/mam/HassaneinEDR20,
author = {Ahmed Hassanein and
Mohammed El{-}Abd and
Issam W. Damaj and
Haseeb Ur Rehman},
title = {Parallel hardware implementation of the brain storm optimization algorithm
using FPGAs},
journal = {Microprocess. Microsystems},
volume = {74},
pages = {103005},
year = {2020}
}
@article{DBLP:journals/mam/HusseinDR20,
author = {Fady Hussein and
Luka Daoud and
Nader Rafla},
title = {A reconfigurable HexCell-based systolic array architecture for evolvable
hardware on {FPGA}},
journal = {Microprocess. Microsystems},
volume = {74},
pages = {103014},
year = {2020}
}
@article{DBLP:journals/mam/MertOS20,
author = {Ahmet Can Mert and
Erdin{\c{c}} {\"{O}}zt{\"{u}}rk and
Erkay Savas},
title = {{FPGA} implementation of a run-time configurable NTT-based polynomial
multiplication hardware},
journal = {Microprocess. Microsystems},
volume = {78},
pages = {103219},
year = {2020}
}
@article{DBLP:journals/mam/SwamynathanB20,
author = {S. M. Swamynathan and
Velusamy Bhanumathi},
title = {Efficient hardware trojan diagnosis in {SRAM} based on {FPGA} processors
using inject detect masking algorithm for multimedia signal Processors},
journal = {Microprocess. Microsystems},
volume = {77},
pages = {103168},
year = {2020}
}
@article{DBLP:journals/mssp/PhadikarMC20,
author = {Amit Phadikar and
Himadri S. Mandal and
Tien{-}Lung Chiu},
title = {Parallel hardware implementation of data hiding scheme for quality
access control of grayscale image based on {FPGA}},
journal = {Multidimens. Syst. Signal Process.},
volume = {31},
number = {1},
pages = {73--101},
year = {2020}
}
@article{DBLP:journals/mta/PhadikarMC20,
author = {Amit Phadikar and
Himadri S. Mandal and
Tien{-}Lung Chiu},
title = {A novel {QIM} data hiding scheme and its hardware implementation using
{FPGA} for quality access control of digital image},
journal = {Multim. Tools Appl.},
volume = {79},
number = {17-18},
pages = {12507--12532},
year = {2020}
}
@article{DBLP:journals/peerj-cs/KakkaraBYMLM20,
author = {Varsha Kakkara and
Karthi Balasubramanian and
B. Yamuna and
Deepak Mishra and
Karthikeyan Lingasubramanian and
Senthil Murugan},
title = {A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation
study},
journal = {PeerJ Comput. Sci.},
volume = {6},
pages = {e250},
year = {2020}
}
@article{DBLP:journals/taco/Abdelrahman20,
author = {Tarek S. Abdelrahman},
title = {Cooperative Software-hardware Acceleration of K-means on a Tightly
Coupled {CPU-FPGA} System},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {17},
number = {3},
pages = {20:1--20:24},
year = {2020}
}
@article{DBLP:journals/tcad/LuoWQLTWG20,
author = {Tao Luo and
Xuan Wang and
Chuping Qu and
Matthew Kay Fei Lee and
Wai Teng Tang and
Weng{-}Fai Wong and
Rick Siow Mong Goh},
title = {An FPGA-Based Hardware Emulator for Neuromorphic Chip With {RRAM}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {2},
pages = {438--450},
year = {2020}
}
@article{DBLP:journals/tcad/WangXGG20,
author = {Dong Wang and
Ke Xu and
Jingning Guo and
Soheil Ghiasi},
title = {DSP-Efficient Hardware Acceleration of Convolutional Neural Network
Inference on FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {12},
pages = {4867--4880},
year = {2020}
}
@article{DBLP:journals/tcas/AhmadP20,
author = {Afzal Ahmad and
Muhammad Adeel Pasha},
title = {Optimizing Hardware Accelerated General Matrix-Matrix Multiplication
for CNNs on FPGAs},
journal = {{IEEE} Trans. Circuits Syst.},
volume = {67-II},
number = {11},
pages = {2692--2696},
year = {2020}
}
@article{DBLP:journals/tim/QinZWZTRD20,
author = {Xi Qin and
Wenzhe Zhang and
Lin Wang and
Yuxi Zhao and
Yu Tong and
Xing Rong and
Jiangfeng Du},
title = {An FPGA-Based Hardware Platform for the Control of Spin-Based Quantum
Systems},
journal = {{IEEE} Trans. Instrum. Meas.},
volume = {69},
number = {4},
pages = {1127--1139},
year = {2020}
}
@article{DBLP:journals/tjs/GuhaMSC20,
author = {Krishnendu Guha and
Atanu Majumder and
Debasri Saha and
Amlan Chakrabarti},
title = {Dynamic power-aware scheduling of real-time tasks for FPGA-based cyber
physical systems against power draining hardware trojan attacks},
journal = {J. Supercomput.},
volume = {76},
number = {11},
pages = {8972--9009},
year = {2020}
}
@article{DBLP:journals/trets/DelomierGCJ20,
author = {Yann Delomier and
Bertrand Le Gal and
J{\'{e}}r{\'{e}}mie Crenne and
Christophe J{\'{e}}go},
title = {Model-based Design of Hardware {SC} Polar Decoders for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {2},
pages = {10:1--10:27},
year = {2020}
}
@article{DBLP:journals/tvlsi/ZhuHYZZS20,
author = {Chaoyang Zhu and
Kejie Huang and
Shuyuan Yang and
Ziqi Zhu and
Hejia Zhang and
Haibin Shen},
title = {An Efficient Hardware Accelerator for Structured Sparse Convolutional
Neural Networks on FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {9},
pages = {1953--1965},
year = {2020}
}
@article{DBLP:journals/wc/ChamolaPKG20,
author = {Vinay Chamola and
Sambit Patra and
Neeraj Kumar and
Mohsen Guizani},
title = {{FPGA} for 5G: Re-configurable Hardware for Next Generation Communication},
journal = {{IEEE} Wirel. Commun.},
volume = {27},
number = {3},
pages = {140--147},
year = {2020}
}
@inproceedings{DBLP:conf/aca/LiangXYS20,
author = {Dongbao Liang and
Jiale Xiao and
Yangbin Yu and
Tao Su},
title = {A {CNN} Hardware Accelerator in {FPGA} for Stacked Hourglass Network},
booktitle = {{ACA}},
series = {Communications in Computer and Information Science},
volume = {1256},
pages = {101--116},
publisher = {Springer},
year = {2020}
}
@inproceedings{DBLP:conf/acns/LabafniyaBM20,
author = {Mansoureh Labafniya and
Shahram Etemadi Borujeni and
Nele Mentens},
title = {Evolvable Hardware Architectures on {FPGA} for Side-Channel Security},
booktitle = {{ACNS} Workshops},
series = {Lecture Notes in Computer Science},
volume = {12418},
pages = {163--180},
publisher = {Springer},
year = {2020}
}
@inproceedings{DBLP:conf/arc/BacchusSK20,
author = {Pascal Bacchus and
Robert J. Stewart and
Ekaterina Komendantskaya},
title = {Accuracy, Training Time and Hardware Efficiency Trade-Offs for Quantized
Neural Networks on FPGAs},
booktitle = {{ARC}},
series = {Lecture Notes in Computer Science},
volume = {12083},
pages = {121--135},
publisher = {Springer},
year = {2020}
}
@inproceedings{DBLP:conf/arc/IkedaSNMT20,
author = {Taiga Ikeda and
Kento Sakurada and
Atsuyoshi Nakamura and
Masato Motomura and
Shinya Takamaeda{-}Yamazaki},
title = {Hardware/Algorithm Co-optimization for Fully-Parallelized Compact
Decision Tree Ensembles on FPGAs},
booktitle = {{ARC}},
series = {Lecture Notes in Computer Science},
volume = {12083},
pages = {345--357},
publisher = {Springer},
year = {2020}
}
@inproceedings{DBLP:conf/asianhost/SahaB20,
author = {Sujan Kumar Saha and
Christophe Bobda},
title = {{FPGA} Accelerated Embedded System Security Through Hardware Isolation},
booktitle = {AsianHOST},
pages = {1--6},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/asplos/KarandikarOAMKN20,
author = {Sagar Karandikar and
Albert J. Ou and
Alon Amid and
Howard Mao and
Randy H. Katz and
Borivoje Nikolic and
Krste Asanovic},
title = {FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance
Profiling and Co-Design},
booktitle = {{ASPLOS}},
pages = {715--731},
publisher = {{ACM}},
year = {2020}
}
@inproceedings{DBLP:conf/atsip/MhaouchEA20,
author = {Ayoub Mhaouch and
Wajdi Elhamzi and
Mohamed Atri},
title = {Lightweight Hardware Architectures for the Piccolo Block Cipher in
{FPGA}},
booktitle = {{ATSIP}},
pages = {1--4},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/cosade/BarenghiBFPZ20,
author = {Alessandro Barenghi and
Matteo Brevi and
William Fornaciari and
Gerardo Pelosi and
Davide Zoni},
title = {Integrating Side Channel Security in the {FPGA} Hardware Design Flow},
booktitle = {{COSADE}},
series = {Lecture Notes in Computer Science},
volume = {12244},
pages = {275--290},
publisher = {Springer},
year = {2020}
}
@inproceedings{DBLP:conf/cscloud/Li0TNC20,
author = {Wanyi Li and
Yongxin Zhu and
Li Tian and
Tianhao Nan and
Xintong Chen},
title = {FPGA-based Hardware Acceleration for Image Copyright Protection Syetem
Based on Blockchain},
booktitle = {CSCloud/EdgeCom},
pages = {234--239},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/csoc/KajurP20,
author = {Renuka Kajur and
K. V. Prasad},
title = {Hardware Realization of {GMSK} System Using Pipelined {CORDIC} Module
on {FPGA}},
booktitle = {{CSOC} {(3)}},
series = {Advances in Intelligent Systems and Computing},
volume = {1226},
pages = {21--31},
publisher = {Springer},
year = {2020}
}
@inproceedings{DBLP:conf/dac/KwadjoB20,
author = {Danielle Tchuinkou Kwadjo and
Christophe Bobda},
title = {Late Breaking Results: Automated Hardware Generation of {CNN} Models
on FPGAs},
booktitle = {{DAC}},
pages = {1--2},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/dac/RestucciaBMCB20,
author = {Francesco Restuccia and
Alessandro Biondi and
Mauro Marinoni and
Giorgiomaria Cicero and
Giorgio C. Buttazzo},
title = {{AXI} HyperConnect: {A} Predictable, Hypervisor-level Interconnect
for Hardware Accelerators in {FPGA} SoC},
booktitle = {{DAC}},
pages = {1--6},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/dac/SunZGPLL20,
author = {Mengshu Sun and
Pu Zhao and
Mehmet G{\"{u}}ng{\"{o}}r and
Massoud Pedram and
Miriam Leeser and
Xue Lin},
title = {3D {CNN} Acceleration on {FPGA} using Hardware-Aware Pruning},
booktitle = {{DAC}},
pages = {1--6},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/dcis/CarvalhoFT20,
author = {Guilherme Carvalho and
Jo{\~{a}}o Canas Ferreira and
V{\'{\i}}tor Grade Tavares},
title = {Hardware architecture for integrate-and-fire signal reconstruction
on {FPGA}},
booktitle = {{DCIS}},
pages = {1--6},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/dsd/FariasNC20,
author = {Marcos Santana Farias and
Nadia Nedjah and
Paulo Victor R. de Carvalho},
title = {Active Redundant Hardware Architecture for Increased Reliability in
FPGA-Based Nuclear Reactors Critical Systems},
booktitle = {{DSD}},
pages = {608--615},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/dsd/PalaciosCDF20,
author = {Jorge Andr{\'{e}}s Palacios and
Vincenzo Caro and
Miguel Dur{\'{a}}n and
Miguel E. Figueroa},
title = {A hardware architecture for Multiscale Retinex with Chromacity Preservation
on an {FPGA}},
booktitle = {{DSD}},
pages = {73--80},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/ecrts/RestucciaPBMB20,
author = {Francesco Restuccia and
Marco Pagani and
Alessandro Biondi and
Mauro Marinoni and
Giorgio C. Buttazzo},
title = {Modeling and Analysis of Bus Contention for Hardware Accelerators
in {FPGA} SoCs},
booktitle = {{ECRTS}},
series = {LIPIcs},
volume = {165},
pages = {12:1--12:23},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2020}
}
@inproceedings{DBLP:conf/euc/RiveraW20,
author = {Luis Ramirez Rivera and
Xiaofang Wang},
title = {Run-time Hardware Trojan Detection and Recovery for Third-Party IPs
in SoC FPGAs},
booktitle = {{EUC}},
pages = {9--16},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/ewdts/GorbachovBPK20,
author = {Valeriy Gorbachov and
Abdulrahman Kataeba Batiaa and
Olha Ponomarenko and
Oksana Kotkova},
title = {Hardware Obfuscation Techniques on FPGA-Based Systems},
booktitle = {{EWDTS}},
pages = {1--5},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/fie/LiZMY20,
author = {Ying Li and
Jiong Zhang and
Hritik Mitra and
Shicheng Yu},
title = {The Systematic Thinking Ability of Hardware/Software Co-design using
{FPGA}},
booktitle = {{FIE}},
pages = {1--6},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/fpga/AttiaB20,
author = {Sameh Attia and
Vaughn Betz},
title = {StateMover: Combining Simulation and Hardware Execution for Efficient
{FPGA} Debugging},
booktitle = {{FPGA}},
pages = {175--185},
publisher = {{ACM}},
year = {2020}
}
@inproceedings{DBLP:conf/fpga/DewanG20,
author = {Samuel Dewan and
Paulo Garcia},
title = {Programming Abstractions for Configurable Hardware: Survey and Research
Directions},
booktitle = {{FPGA}},
pages = {310},
publisher = {{ACM}},
year = {2020}
}
@inproceedings{DBLP:conf/fpga/Martinez-Corral20,
author = {Unai Martinez{-}Corral and
Guillermo Callaghan and
Konstantinos Iordanou and
Cosmin Gorgovan and
Koldo Basterretxea and
Mikel Luj{\'{a}}n},
title = {{DBHI:} {A} Tool for Decoupled Functional Hardware-Software Co-Design
on SoCs},
booktitle = {{FPGA}},
pages = {326},
publisher = {{ACM}},
year = {2020}
}
@inproceedings{DBLP:conf/fpga/MatasLGPK20,
author = {Kaspar Matas and
Tuan La and
Nikola Grunchevski and
Khoa Dang Pham and
Dirk Koch},
title = {Invited Tutorial: {FPGA} Hardware Security for Datacenters and Beyond},
booktitle = {{FPGA}},
pages = {11--20},
publisher = {{ACM}},
year = {2020}
}
@inproceedings{DBLP:conf/fpga/MiedemaSNAMS20,
author = {Rene Miedema and
Georgios Smaragdos and
Mario Negrello and
Zaid Al{-}Ars and
Matthias M{\"{o}}ller and
Christos Strydis},
title = {Synthesis-Free, Flexible and Fast Hardware Library for Biophysically
Plausible Neurosimulations},
booktitle = {{FPGA}},
pages = {319},
publisher = {{ACM}},
year = {2020}
}
@inproceedings{DBLP:conf/fpga/MokriALH20,
author = {Parnian Mokri and
Maziar Amiraskari and
Yuelin Liu and
Mark Hempstead},
title = {Early-stage Automated Identification of Similar Hardware Implementations
with Abstract-Syntax-Tree},
booktitle = {{FPGA}},
pages = {312},
publisher = {{ACM}},
year = {2020}
}
@inproceedings{DBLP:conf/fpga/PortE20,
author = {Oron Port and
Yoav Etsion},
title = {Hardware Description Beyond Register-Transfer Level Languages},
booktitle = {{FPGA}},
pages = {312},
publisher = {{ACM}},
year = {2020}
}
@inproceedings{DBLP:conf/fpga/RybalkinW20,
author = {Vladimir Rybalkin and
Norbert Wehn},
title = {When Massive {GPU} Parallelism Ain't Enough: {A} Novel Hardware Architecture
of 2D-LSTM Neural Network},
booktitle = {{FPGA}},
pages = {111--121},
publisher = {{ACM}},
year = {2020}
}
@inproceedings{DBLP:conf/fpga/TineELVK20,
author = {Blaise Tine and
Fares Elsabbagh and
Seyong Lee and
Jeffrey S. Vetter and
Hyesoon Kim},
title = {Cash: {A} Single-Source Hardware-Software Codesign Framework for Rapid
Prototyping},
booktitle = {{FPGA}},
pages = {321},
publisher = {{ACM}},
year = {2020}
}
@inproceedings{DBLP:conf/fpga/TineLVK20,
author = {Blaise Tine and
Seyong Lee and
Jeffrey S. Vetter and
Hyesoon Kim},
title = {Productive Hardware Designs using Hybrid {HLS-RTL} Development},
booktitle = {{FPGA}},
pages = {311},
publisher = {{ACM}},
year = {2020}
}
@inproceedings{DBLP:conf/fpl/HaghiAPDHM20,
author = {Abbas Haghi and
Lluc Alvarez and
Jord{\`{a}} Polo and
Dionysios Diamantopoulos and
Christoph Hagleitner and
Miquel Moret{\'{o}}},
title = {A Hardware/Software Co-Design of K-mer Counting Using a CAPI-Enabled
{FPGA}},
booktitle = {{FPL}},
pages = {57--64},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/fpl/MahmoudHS20,
author = {Dina G. Mahmoud and
Wei Hu and
Mirjana Stojilovic},
title = {X-Attack: Remote Activation of Satisfiability Don't-Care Hardware
Trojans on Shared FPGAs},
booktitle = {{FPL}},
pages = {185--192},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/fpl/SkarmanG0K20,
author = {Frans Skarman and
Oscar Gustafsson and
Daniel Jung and
Mattias Krysander},
title = {Acceleration of Simulation Models Through Automatic Conversion to
{FPGA} Hardware},
booktitle = {{FPL}},
pages = {359--360},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/fruct/AntonovBF20,
author = {Alexander P. Antonov and
Denis Besedin and
Alexey S. Filippov},
title = {Research of the Efficiency of High-level Synthesis Tool for {FPGA}
Based Hardware Implementation of Some Basic Algorithms for the Big
Data Analysis and Management Tasks},
booktitle = {{FRUCT}},
pages = {1--7},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/i2mtc/Dai0YZY20,
author = {Xuefeng Dai and
Jun Gu and
Peng Ye and
Yu Zhao and
Kuojun Yang},
title = {{FPGA} Realization of Hardware-Flexible Parallel Structure {FIR} Filters
Using Combined Systolic Arrays},
booktitle = {{I2MTC}},
pages = {1--5},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/icaart/WiemM20,
author = {Belhedi Wiem and
Hannachi Marwa},
title = {Supervised Hardware/Software Partitioning Algorithms for FPGA-based
Applications},
booktitle = {{ICAART} {(2)}},
pages = {860--864},
publisher = {{SCITEPRESS}},
year = {2020}
}
@inproceedings{DBLP:conf/icarcv/KopczynskiG20,
author = {Maciej Kopczynski and
Tomasz Grzes},
title = {Parallelized Hardware Rough Set Processor Architecture in {FPGA} for
Core Calculation in Big Datasets},
booktitle = {{ICARCV}},
pages = {1098--1103},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/icce-berlin/ColangeloSSM20,
author = {Philip Colangelo and
Oren Segal and
Alexander Speicher and
Martin Margala},
title = {Automated Hardware and Neural Network Architecture co-design of {FPGA}
accelerators using multi-objective Neural Architecture Search},
booktitle = {ICCE-Berlin},
pages = {1--6},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/icfpt/KwadjoMB20,
author = {Danielle Tchuinkou Kwadjo and
Joel Mandebi Mbongue and
Christophe Bobda},
title = {Performance Exploration on Pre-implemented {CNN} Hardware Accelerator
on {FPGA}},
booktitle = {{FPT}},
pages = {298--299},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/icm2/ChetanMLS20,
author = {S. Chetan and
J. Manikandan and
V. Lekshmi and
S. Sudhakar},
title = {Hardware Implementation of Floating Point Matrix Inversion Modules
on FPGAs},
booktitle = {{ICM}},
pages = {1--4},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/icm2/ShattaAAADHH20,
author = {Maha Shatta and
Ihab Adly and
Hassanein H. Amer and
Gehad I. Alkady and
Ramez M. Daoud and
Sahar Hamed and
Shahenda Hatem},
title = {FPGA-based Architectures to Recover from Hardware Trojan Horses, Single
Event Upsets and Hard Failures},
booktitle = {{ICM}},
pages = {1--4},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/icta3/LiuW0020,
author = {Ye Liu and
Yin Wang and
Liang Chang and
Jun Zhou},
title = {A Fast and Efficient FPGA-based Level Set Hardware Accelerator for
Image Segmentation},
booktitle = {{ICTA}},
pages = {61--62},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/icton/LeeHW20,
author = {Jeonghun Lee and
Jiayuan He and
Ke Wang},
title = {Neural Networks and {FPGA} Hardware Accelerators for Millimeter-Wave
Radio-over-Fiber Systems},
booktitle = {{ICTON}},
pages = {1--4},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/ipccc/BawejaRDH20,
author = {Randeep S. Baweja and
Devin B. Ridge and
Harpreet S. Dhillon and
William C. Headley},
title = {{FPGA} Implementation of a Pseudo-Random Signal Generator for {RF}
Hardware Test and Evaluation},
booktitle = {{IPCCC}},
pages = {1--7},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/ipps/FiscalettiSSSS20,
author = {Giorgia Fiscaletti and
Marco Speziali and
Luca Stornaiuolo and
Marco D. Santambrogio and
Donatella Sciuto},
title = {Hardware resources analysis of BNNs splitting for FARD-based multi-FPGAs
Distributed Systems},
booktitle = {{IPDPS} Workshops},
pages = {135--138},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/iscas/AhmadPR20,
author = {Afzal Ahmad and
Muhammad Adeel Pasha and
Ghulam Jilani Raza},
title = {Accelerating Tiny YOLOv3 using FPGA-Based Hardware/Software Co-Design},
booktitle = {{ISCAS}},
pages = {1--5},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/iscas/DinelliMRF20,
author = {Gianmarco Dinelli and
Gabriele Meoni and
Emilio Rapuano and
Luca Fanucci},
title = {Advantages and Limitations of Fully on-Chip {CNN} FPGA-Based Hardware
Accelerator},
booktitle = {{ISCAS}},
pages = {1--5},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/iscas/GrycelW20,
author = {Jacob T. Grycel and
Robert J. Walls},
title = {{DRAB-LOCUS:} An Area-Efficient {AES} Architecture for Hardware Accelerator
Co-Location on FPGAs},
booktitle = {{ISCAS}},
pages = {1--5},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/iscas/MadsenTP20,
author = {Anne K. Madsen and
Michael Scott Trimboli and
Darshika G. Perera},
title = {An Optimized FPGA-Based Hardware Accelerator for Physics-Based {EKF}
for Battery Cell Management},
booktitle = {{ISCAS}},
pages = {1--5},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/iscas/WangCXZ20,
author = {Hao Wang and
Shan Cao and
Shugong Xu and
Shunqing Zhang},
title = {Hardware-Software Co-Design for Face Recognition on {FPGA} SoCs},
booktitle = {{ISCAS}},
pages = {1--5},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/iscc/PengMGGT20,
author = {Ping Peng and
Cunqing Ma and
Jingquan Ge and
Neng Gao and
Chenyang Tu},
title = {A Hardware/Software Collaborative {SM4} Implementation Resistant to
Side-channel Attacks on {ARM-FPGA} Embedded SoC},
booktitle = {{ISCC}},
pages = {1--7},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/isocc/ChenFC20,
author = {Yu{-}Hsiang Chen and
Chih{-}Peng Fan and
Robert Chen{-}Hao Chang},
title = {Prototype of Low Complexity {CNN} Hardware Accelerator with FPGA-based
{PYNQ} Platform for Dual-Mode Biometrics Recognition},
booktitle = {{ISOCC}},
pages = {189--190},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/isvlsi/ZhangWMW20,
author = {Hui Zhang and
Wei Wu and
Yufei Ma and
Zhongfeng Wang},
title = {Efficient Hardware Post Processing of Anchor-Based Object Detection
on {FPGA}},
booktitle = {{ISVLSI}},
pages = {580--585},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/kka/Wojtulewicz20,
author = {Andrzej Wojtulewicz},
title = {Hardware Accelerators for Fast Implementation of {DMC} and {GPC} Control
Algorithms Using {FPGA} and Their Applications to a Servomotor},
booktitle = {{KKA}},
series = {Advances in Intelligent Systems and Computing},
volume = {1196},
pages = {1079--1091},
publisher = {Springer},
year = {2020}
}
@inproceedings{DBLP:conf/niles/GadAAM20,
author = {Ali H. Gad and
Seif Eldeen E. Abdalazeem and
Omar A. Abdelmegid and
Hassan Mostafa},
title = {Low power and area {SHA-256} hardware accelerator on Virtex-7 {FPGA}},
booktitle = {{NILES}},
pages = {181--185},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/norchip/LiuWWLHYHZ020,
author = {Lizheng Liu and
Deyu Wang and
Yuning Wang and
Anders Lansner and
Ahmed Hemani and
Yu Yang and
Xiaoming Hu and
Zhuo Zou and
Lirong Zheng},
title = {A FPGA-based Hardware Accelerator for Bayesian Confidence Propagation
Neural Network},
booktitle = {NorCAS},
pages = {1--6},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/norchip/WulfWG20,
author = {Cornelia Wulf and
Michael Willig and
Diana G{\"{o}}hringer},
title = {Low Power Scheduling of Periodic Hardware Tasks in Flash-Based FPGAs},
booktitle = {NorCAS},
pages = {1--7},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/ross-ws/HeinzHS020,
author = {Carsten Heinz and
Jaco A. Hofmann and
Lukas Sommer and
Andreas Koch},
title = {Improving Job Launch Rates in the TaPaSCo {FPGA} Middleware by Hardware/Software-Co-Design},
booktitle = {ROSS@SC},
pages = {22--30},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/rsp/MoreacABHD20,
author = {Erwan Mor{\'{e}}ac and
El Mehdi Abdali and
Fran{\c{c}}ois Berry and
Dominique Heller and
Jean{-}Philippe Diguet},
title = {Hardware-in-the-loop simulation with dynamic partial {FPGA} reconfiguration
applied to computer vision in ROS-based {UAV}},
booktitle = {{RSP}},
pages = {1--7},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/sadasc/AtibiBABT20,
author = {Mohamed Atibi and
Mohamed Boussaa and
Issam Atouf and
Abdellatif Bennis and
Mohamed Tabaa},
title = {Hardware Implementation of Roadway Classification System in {FPGA}
Platform},
booktitle = {{SADASC}},
series = {Communications in Computer and Information Science},
volume = {1207},
pages = {200--208},
publisher = {Springer},
year = {2020}
}
@inproceedings{DBLP:conf/sbcci/MenezesHCN20,
author = {N{\'{a}}gila Ribeiro de Menezes and
Hugo Daniel Hern{\'{a}}ndez and
Dionisio Carvalho and
Wilhelmus A. M. Van Noije},
title = {All-digital FPGA-based {RF} pulsed transmitter with hardware complexity
reduction techniques},
booktitle = {{SBCCI}},
pages = {1--5},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/smartcloud/SteinertKWUS20,
author = {Fritjof Steinert and
Philipp Kreowsky and
Eric L. Wisotzky and
Christian Unger and
Benno Stabernack},
title = {A Hardware/Software Framework for the Integration of FPGA-based Accelerators
into Cloud Computing Infrastructures},
booktitle = {SmartCloud},
pages = {23--28},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/socc/GaoWAL20,
author = {Jia{-}Bao Gao and
Jian Wang and
Md Tanvir Arafin and
Jin{-}Mei Lai},
title = {{FABLE-DTS:} Hardware-Software Co-Design of a Fast and Stable Data
Transmission System for FPGAs},
booktitle = {SoCC},
pages = {207--212},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/spawc/BenzinODC20,
author = {Andreas Benzin and
Dennis Osterland and
Maksim Dill and
Giuseppe Caire},
title = {Centralized Single {FPGA} Real Time Zero Forcing Massive {MIMO} 5G
Basestation Hardware and Gateware},
booktitle = {{SPAWC}},
pages = {1--5},
publisher = {{IEEE}},
year = {2020}
}
@inproceedings{DBLP:conf/vdat/ChoudhariCCDI20,
author = {Onkar Choudhari and
Marisha Chopade and
Sourabh Chopde and
Swarali Dabhadkar and
Vaishali V. Ingale},
title = {{HARDWARE} {ACCELERATOR:} {IMPLEMENTATION} {OF} {CNN} {ON} {FPGA}
{FOR} {DIGIT} {RECOGNITION}},
booktitle = {{VDAT}},
pages = {1--6},
publisher = {{IEEE}},
year = {2020}
}
@article{DBLP:journals/corr/abs-2001-01955,
author = {Chaoyang Zhu and
Kejie Huang and
Shuyuan Yang and
Ziqi Zhu and
Hejia Zhang and
Haibin Shen},
title = {An Efficient Hardware Accelerator for Structured Sparse Convolutional
Neural Networks on FPGAs},
journal = {CoRR},
volume = {abs/2001.01955},
year = {2020}
}
@article{DBLP:journals/corr/abs-2005-07332,
author = {Dillon Staub and
Rashmi Jha and
David Kapp},
title = {A CRISPR-Cas-Inspired Mechanism for Detecting Hardware Trojans in
{FPGA} Devices},
journal = {CoRR},
volume = {abs/2005.07332},
year = {2020}
}
@article{DBLP:journals/corr/abs-2007-10560,
author = {Zhaoxiong Yang and
Shuihai Hu and
Kai Chen},
title = {FPGA-Based Hardware Accelerator of Homomorphic Encryption for Efficient
Federated Learning},
journal = {CoRR},
volume = {abs/2007.10560},
year = {2020}
}
@article{DBLP:journals/corr/abs-2009-01434,
author = {Zhe Lin and
Wei Zhang and
Sharad Sinha},
title = {Decision Tree Based Hardware Power Monitoring for Run Time Dynamic
Power Management in {FPGA}},
journal = {CoRR},
volume = {abs/2009.01434},
year = {2020}
}
@article{DBLP:journals/iacr/ElkhatibAM20,
author = {Rami Elkhatib and
Reza Azarderakhsh and
Mehran Mozaffari Kermani},
title = {Efficient and Fast Hardware Architectures for {SIKE} Round 2 on {FPGA}},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {611},
year = {2020}
}
@article{DBLP:journals/iacr/GhoshKDL20,
author = {Santosh Ghosh and
Luis S. Kida and
Soham Jayesh Desai and
Reshma Lal},
title = {A {\textgreater}100 Gbps Inline {AES-GCM} Hardware Engine and Protected
{DMA} Transfers between {SGX} Enclave and {FPGA} Accelerator Device},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {178},
year = {2020}
}
@book{DBLP:series/lnee/SkliarovaS19,
author = {Iouliia Skliarova and
Valery Sklyarov},
title = {{FPGA-BASED} Hardware Accelerators},
series = {Lecture Notes in Electrical Engineering},
volume = {566},
publisher = {Springer},
year = {2019}
}
@article{DBLP:journals/access/AdhikariHV19,
author = {Prottay M. Adhikari and
Hossein Hooshyar and
Luigi Vanfretti},
title = {Experimental Quantification of Hardware Requirements for FPGA-Based
Reconfigurable PMUs},
journal = {{IEEE} Access},
volume = {7},
pages = {57527--57538},
year = {2019}
}
@article{DBLP:journals/access/HussainTSR19,
author = {Ahmed A. Hussain and
Nizar Tayem and
Abdel{-}Hamid Soliman and
Redha M. Radaydeh},
title = {FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source
{DOA} Estimation Algorithms},
journal = {{IEEE} Access},
volume = {7},
pages = {88845--88858},
year = {2019}
}
@article{DBLP:journals/access/LiuLHD19,
author = {Qin Liu and
Tian Liang and
Zhen Huang and
Venkata Dinavahi},
title = {Real-Time FPGA-Based Hardware Neural Network for Fault Detection and
Isolation in More Electric Aircraft},
journal = {{IEEE} Access},
volume = {7},
pages = {159831--159841},
year = {2019}
}
@article{DBLP:journals/access/MedusIFBM19,
author = {Leandro D. Medus and
Taras Iakymchuk and
Jos{\'{e}} Vicente Franc{\'{e}}s{-}V{\'{\i}}llora and
Manuel Bataller{-}Mompe{\'{a}}n and
Alfredo Rosado Mu{\~{n}}oz},
title = {A Novel Systolic Parallel Hardware Architecture for the {FPGA} Acceleration
of Feedforward Neural Networks},
journal = {{IEEE} Access},
volume = {7},
pages = {76084--76103},
year = {2019}
}
@article{DBLP:journals/access/MinatiMMGPMAHGM19,
author = {Ludovico Minati and
Vardan Movsisyan and
Matthew McCormick and
Khachatur Gyozalyan and
Tigran Papazyan and
Hrach Makaryan and
Stefano Aldrigo and
Taron Harutyunyan and
Hayk Ghaltaghchyan and
Chris Mccormick and
Mick Fandrich},
title = {iFLEX: {A} Fully Open-Source, High-Density Field-Programmable Gate
Array (FPGA)-Based Hardware Co-Processor for Vector Similarity Searching},
journal = {{IEEE} Access},
volume = {7},
pages = {112269--112283},
year = {2019}
}
@article{DBLP:journals/access/RaviSGS19,
author = {Murali Ravi and
Angu Sewa and
Shashidhar T. G. and
Siva Sankara Sai Sanagapati},
title = {{FPGA} as a Hardware Accelerator for Computation Intensive Maximum
Likelihood Expectation Maximization Medical Image Reconstruction Algorithm},
journal = {{IEEE} Access},
volume = {7},
pages = {111727--111735},
year = {2019}
}
@article{DBLP:journals/access/ZhuZZCZJM19,
author = {Zongwei Zhu and
Junneng Zhang and
Jinjin Zhao and
Jing Cao and
Duan Zhao and
Gangyong Jia and
Qingyong Meng},
title = {A Hardware and Software Task-Scheduling Framework Based on {CPU+FPGA}
Heterogeneous Architecture in Edge Computing},
journal = {{IEEE} Access},
volume = {7},
pages = {148975--148988},
year = {2019}
}
@article{DBLP:journals/cssp/BonnyDME19,
author = {Talal Bonny and
Ridhwan Al Debsi and
Sohaib Majzoub and
Ahmed S. Elwakil},
title = {Hardware Optimized {FPGA} Implementations of High-Speed True Random
Bit Generators Based on Switching-Type Chaotic Oscillators},
journal = {Circuits Syst. Signal Process.},
volume = {38},
number = {3},
pages = {1342--1359},
year = {2019}
}
@article{DBLP:journals/esl/ReddyV19,
author = {Kuladeep Sai Reddy and
Kizheppatt Vipin},
title = {OpenNoC: An Open-Source NoC Infrastructure for FPGA-Based Hardware
Acceleration},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {11},
number = {4},
pages = {123--126},
year = {2019}
}
@article{DBLP:journals/et/RanjbarSPA19,
author = {Omid Ranjbar and
Siavash Bayat Sarmadi and
Fatemeh Pooyan and
Hossein Asadi},
title = {A Unified Approach to Detect and Distinguish Hardware Trojans and
Faults in SRAM-based FPGAs},
journal = {J. Electron. Test.},
volume = {35},
number = {2},
pages = {201--214},
year = {2019}
}
@article{DBLP:journals/ieiceee/ZhaoJYWG19,
author = {Jiafei Zhao and
Rongkun Jiang and
Hao Yang and
Xuetian Wang and
Hongmin Gao},
title = {Reconfigurable hardware architecture for Mean Level and log-t {CFAR}
detectors in {FPGA} implementations},
journal = {{IEICE} Electron. Express},
volume = {16},
number = {21},
pages = {20190584},
year = {2019}
}
@article{DBLP:journals/ieicet/RanawakaETDAS19,
author = {Piyumal Ranawaka and
Mongkol Ekpanyapong and
Adriano Tavares and
Mathew Dailey and
Krit Athikulwongse and
Vitor Alberto Silva},
title = {High Performance Application Specific Stream Architecture for Hardware
Acceleration of {HOG-SVM} on {FPGA}},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {102-A},
number = {12},
pages = {1792--1803},
year = {2019}
}
@article{DBLP:journals/iet-cds/MoussaBK19,
author = {Intissar Moussa and
Adel Bouallegue and
Adel Khedher},
title = {New wind turbine emulator based on {DC} machine: hardware implementation
using {FPGA} board for an open-loop operation},
journal = {{IET} Circuits Devices Syst.},
volume = {13},
number = {6},
pages = {896--902},
year = {2019}
}
@article{DBLP:journals/iet-cds/PandeyGK19,
author = {Jai Gopal Pandey and
Tarun Goel and
Abhijit Karmakar},
title = {Hardware architectures for {PRESENT} block cipher and their {FPGA}
implementations},
journal = {{IET} Circuits Devices Syst.},
volume = {13},
number = {7},
pages = {958--969},
year = {2019}
}
@article{DBLP:journals/ijaac/SirineBF19,
author = {Telmoudi Brini Sirine and
Badreddine Bouzouita and
Faouzi Bouani},
title = {A hardware/software architecture dedicated to model predictive control
law and implemented into an {FPGA} platform},
journal = {Int. J. Autom. Control.},
volume = {13},
number = {3},
pages = {301--323},
year = {2019}
}
@article{DBLP:journals/ijes/PereraL19,
author = {Darshika G. Perera and
Kin Fun Li},
title = {A design methodology for mobile and embedded applications on FPGA-based
dynamic reconfigurable hardware},
journal = {Int. J. Embed. Syst.},
volume = {11},
number = {5},
pages = {661--677},
year = {2019}
}
@article{DBLP:journals/ijmssc/BenhamadoucheDB19,
author = {Abdelouahab D. Benhamadouche and
Farid Djahli and
Adel Ballouti and
Abdeslem Sahli},
title = {FPGA-based hardware-in-the-loop for multi-domain simulation},
journal = {Int. J. Model. Simul. Sci. Comput.},
volume = {10},
number = {4},
pages = {1950020:1--1950020:18},
year = {2019}
}
@article{DBLP:journals/ijrc/DinelliMRBF19,
author = {Gianmarco Dinelli and
Gabriele Meoni and
Emilio Rapuano and
Gionata Benelli and
Luca Fanucci},
title = {An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories
Only: Design and Benchmarking with Intel Movidius Neural Compute Stick},
journal = {Int. J. Reconfigurable Comput.},
volume = {2019},
pages = {7218758:1--7218758:13},
year = {2019}
}
@article{DBLP:journals/iotj/ChenGWLL19,
author = {Zhe Chen and
Shize Guo and
Jian Wang and
Yubai Li and
Zhonghai Lu},
title = {Toward {FPGA} Security in IoT: {A} New Detection Technique for Hardware
Trojans},
journal = {{IEEE} Internet Things J.},
volume = {6},
number = {4},
pages = {7061--7068},
year = {2019}
}
@article{DBLP:journals/jcsc/SamirHKEOYAMSM19,
author = {Nagham Samir and
Abdelrahman Sobeih Hussein and
Mohaned Khaled and
Ahmed N. El{-}Zeiny and
Mahetab Osama and
Heba Yassin and
Ali Abdelbaky and
Omar Mahmoud and
Ahmed Shawky and
Hassan Mostafa},
title = {{ASIC} and {FPGA} Comparative Study for IoT Lightweight Hardware Security
Algorithms},
journal = {J. Circuits Syst. Comput.},
volume = {28},
number = {12},
pages = {1930009:1--1930009:25},
year = {2019}
}
@article{DBLP:journals/jcsc/SugiartoAC19,
author = {Indar Sugiarto and
Cristian Axenie and
J{\"{o}}rg Conradt},
title = {FPGA-Based Hardware Accelerator for an Embedded Factor Graph with
Configurable Optimization},
journal = {J. Circuits Syst. Comput.},
volume = {28},
number = {2},
pages = {1950031:1--1950031:30},
year = {2019}
}
@article{DBLP:journals/jcsm/DeviC019,
author = {D. Indhumathi Devi and
S. Chithra and
M. Sethumadhavan},
title = {Hardware Random Number GeneratorUsing {FPGA}},
journal = {J. Cyber Secur. Mobil.},
volume = {8},
number = {4},
pages = {409--418},
year = {2019}
}
@article{DBLP:journals/jrtip/GeS19,
author = {Hangqi Ge and
Jin Sha},
title = {FPGA-based low-complexity high-throughput real-time hardware accelerator
for robust watermarking},
journal = {J. Real Time Image Process.},
volume = {16},
number = {4},
pages = {813--820},
year = {2019}
}
@article{DBLP:journals/jrtip/IbraheemHALG19,
author = {Mohammed Shaaban Ibraheem and
Khalil Hachicha and
Syed Zahid Ahmed and
Laurent Lambert and
Patrick Garda},
title = {High-throughput parallel {DWT} hardware architecture implemented on
an FPGA-based platform},
journal = {J. Real Time Image Process.},
volume = {16},
number = {6},
pages = {2043--2057},
year = {2019}
}
@article{DBLP:journals/jvcir/RaoY19,
author = {Perumalla Srinivasa Rao and
Yedukondalu Kamatham},
title = {Hardware implementation of digital image skeletonization algorithm
using {FPGA} for computer vision applications},
journal = {J. Vis. Commun. Image Represent.},
volume = {59},
pages = {140--149},
year = {2019}
}
@article{DBLP:journals/mam/FournarisPK19,
author = {Apostolos P. Fournaris and
Lampros Pyrgas and
Paris Kitsos},
title = {An efficient multi-parameter approach for {FPGA} hardware Trojan detection},
journal = {Microprocess. Microsystems},
volume = {71},
year = {2019}
}
@article{DBLP:journals/pvldb/OwaidaAFHM19,
author = {Muhsen Owaida and
Gustavo Alonso and
Laura Fogliarini and
Anthony Hock{-}Koon and
Pierre{-}Etienne Melet},
title = {Lowering the Latency of Data Processing Pipelines Through {FPGA} based
Hardware Acceleration},
journal = {Proc. {VLDB} Endow.},
volume = {13},
number = {1},
pages = {71--85},
year = {2019}
}
@article{DBLP:journals/ria/KumarNM19,
author = {Kaushal Kumar and
Durgesh Nandan and
Ritesh Kumar Mishra},
title = {Compact Hardware of Running Gaussian Average Algorithm for Moving
Object Detection Realized on {FPGA} and {ASIC}},
journal = {Rev. d'Intelligence Artif.},
volume = {33},
number = {4},
pages = {305--311},
year = {2019}
}
@article{DBLP:journals/saj/RouxSV19,
author = {Rikus le Roux and
George van Schoor and
Pieter A. van Vuuren},
title = {Parsing and analysis of a Xilinx {FPGA} bitstream for generating new
hardware by direct bit manipulation in real-time},
journal = {South Afr. Comput. J.},
volume = {31},
number = {1},
year = {2019}
}
@article{DBLP:journals/sensors/LiYLMY19,
author = {Jian Li and
Xinlei Yan and
Maojin Li and
Ming Meng and
Xin Yan},
title = {A Method of FPGA-Based Extraction of High-Precision Time-Difference
Information and Implementation of Its Hardware Circuit},
journal = {Sensors},
volume = {19},
number = {23},
pages = {5067},
year = {2019}
}
@article{DBLP:journals/tcas/NakaT19,
author = {Taiki Naka and
Hiroyuki Torikai},
title = {A Novel Generalized Hardware-Efficient Neuron Model Based on Asynchronous
{CA} Dynamics and Its Biologically Plausible On-FPGA Learnings},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {66-II},
number = {7},
pages = {1247--1251},
year = {2019}
}
@article{DBLP:journals/tcas/WisniewskiBS19,
author = {Remigiusz Wisniewski and
Grzegorz Bazydlo and
Pawel Szczesniak},
title = {Low-Cost {FPGA} Hardware Implementation of Matrix Converter Switch
Control},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {66-II},
number = {7},
pages = {1177--1181},
year = {2019}
}
@article{DBLP:journals/tci/ChenHCL19,
author = {Huan{-}Yuan Chen and
Wen{-}Jyi Hwang and
Chau{-}Jern Cheng and
Xin{-}Ji Lai},
title = {An FPGA-Based Autofocusing Hardware Architecture for Digital Holography},
journal = {{IEEE} Trans. Computational Imaging},
volume = {5},
number = {2},
pages = {287--300},
year = {2019}
}
@article{DBLP:journals/tinstmc/AkbatiUA19,
author = {Onur Akbati and
Hatice Didem {\"{U}}zg{\"{u}}n and
Sirin Akkaya},
title = {Hardware-in-the-loop simulation and implementation of a fuzzy logic
controller with {FPGA:} case study of a magnetic levitation system},
journal = {Trans. Inst. Meas. Control},
volume = {41},
number = {8},
pages = {2150--2159},
year = {2019}
}
@article{DBLP:journals/vlsisp/ReichenbachHHLB19,
author = {Marc Reichenbach and
Philipp Holzinger and
Konrad H{\"{a}}ublein and
Tobias Lieske and
Paul Blinzer and
Dietmar Fey},
title = {Heterogeneous Computing Utilizing FPGAs - {A} New and Flexible Approach
Integrating Dedicated Hardware Accelerators into Common Computing
Platforms},
journal = {J. Signal Process. Syst.},
volume = {91},
number = {7},
pages = {745--757},
year = {2019}
}
@inproceedings{DBLP:conf/arc/PeltenburgSBHA19,
author = {Johan Peltenburg and
Jeroen van Straten and
Matthijs Brobbel and
H. Peter Hofstee and
Zaid Al{-}Ars},
title = {Supporting Columnar In-memory Formats on {FPGA:} The Hardware Design
of Fletcher for Apache Arrow},
booktitle = {{ARC}},
series = {Lecture Notes in Computer Science},
volume = {11444},
pages = {32--47},
publisher = {Springer},
year = {2019}
}
@inproceedings{DBLP:conf/asicon/LiMWZY19,
author = {Yafei Li and
Kuizhi Mei and
Xiao Wang and
Zeng Zhang and
Hejie Yu},
title = {Collaborative Implementation of Hardware-Oriented {GBDT} Compress
Algorithm Based on {DSP+FPGA}},
booktitle = {{ASICON}},
pages = {1--4},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/asicon/ZhaoWN19,
author = {Ziwei Zhao and
Fei Wang and
Qi Ni},
title = {An FPGA-based Hardware Accelerator of {RANSAC} Algorithm for Matching
of Images Feature Points},
booktitle = {{ASICON}},
pages = {1--4},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/ccece/LedwonC019,
author = {Morgan Ledwon and
Bruce F. Cockburn and
Jie Han},
title = {Design and Evaluation of an FPGA-based Hardware Accelerator for Deflate
Data Decompression},
booktitle = {{CCECE}},
pages = {1--6},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/ccs/GrossJZS19,
author = {Mathieu Gross and
Nisha Jacob and
Andreas Zankl and
Georg Sigl},
title = {Breaking TrustZone Memory Isolation through Malicious Hardware on
a Modern FPGA-SoC},
booktitle = {ASHES@CCS},
pages = {3--12},
publisher = {{ACM}},
year = {2019}
}
@inproceedings{DBLP:conf/codes/VazquezGS19,
author = {Ruben Vazquez and
Ann Gordon{-}Ross and
Greg Stitt},
title = {Offloading cache configuration prediction to an {FPGA} for hardware
speedup and overhead reduction: work-in-progress},
booktitle = {{CODES+ISSS}},
pages = {11:1--11:2},
publisher = {{ACM}},
year = {2019}
}
@inproceedings{DBLP:conf/coins/StratakosGTEMS19,
author = {Ioannis Stratakos and
Dimitrios Gourounas and
Vasileios Tsoutsouras and
Theodore L. Economopoulos and
George K. Matsopoulos and
Dimitrios Soudris},
title = {Hardware Acceleration of Image Registration Algorithm on FPGA-based
Systems on Chip},
booktitle = {{COINS}},
pages = {92--97},
publisher = {{ACM}},
year = {2019}
}
@inproceedings{DBLP:conf/crisis/ChaouchDDMOB19,
author = {Asma Chaouch and
Fangan{-}Yssouf Dosso and
Laurent{-}St{\'{e}}phane Didier and
Nadia El Mrabet and
Bouraoui Ouni and
Belgacem Bouallegue},
title = {Hardware Optimization on {FPGA} for the Modular Multiplication in
the {AMNS} Representation},
booktitle = {CRiSIS},
series = {Lecture Notes in Computer Science},
volume = {12026},
pages = {113--127},
publisher = {Springer},
year = {2019}
}
@inproceedings{DBLP:conf/csps/AnCZWZ19,
author = {Junru An and
Zhiwei Cui and
Zhenhui Zhang and
Liji Wu and
Xiangmin Zhang},
title = {Research on Temperature Characteristics of IoT Chip Hardware Trojan
Based on {FPGA}},
booktitle = {{CSPS}},
series = {Lecture Notes in Electrical Engineering},
volume = {571},
pages = {1222--1230},
publisher = {Springer},
year = {2019}
}
@inproceedings{DBLP:conf/dcis/GarciaO19,
author = {Javier Cereijo Garc{\'{\i}}a and
Roberto R. Osorio},
title = {Hardware Implementation of Statecharts for FPGA-based Control in Scientific
Facilities},
booktitle = {{DCIS}},
pages = {1--6},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/ecrts/PaganiRBMLB19,
author = {Marco Pagani and
Enrico Rossi and
Alessandro Biondi and
Mauro Marinoni and
Giuseppe Lipari and
Giorgio C. Buttazzo},
title = {A Bandwidth Reservation Mechanism for AXI-Based Hardware Accelerators
on FPGAs},
booktitle = {{ECRTS}},
series = {LIPIcs},
volume = {133},
pages = {24:1--24:24},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2019}
}
@inproceedings{DBLP:conf/esscirc/ErbagciAEM19,
author = {Burak Erbagci and
Nail Etkin Can Akkaya and
Cagri Erbagci and
Ken Mai},
title = {An Inherently Secure {FPGA} using {PUF} Hardware-Entanglement and
Side-Channel Resistant Logic in 65nm Bulk {CMOS}},
booktitle = {{ESSCIRC}},
pages = {65--68},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/eucnc/ChiotakisPP19,
author = {Spyros Chiotakis and
S{\'{e}}bastien Pinneterre and
Michele Paolino},
title = {vFPGAmanager: {A} Hardware-Software Framework for Optimal {FPGA} Resources
Exploitation in Network Function Virtualization},
booktitle = {EuCNC},
pages = {47--51},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/fccm/GuoLR0C19,
author = {Licheng Guo and
Jason Lau and
Zhenyuan Ruan and
Peng Wei and
Jason Cong},
title = {Hardware Acceleration of Long Read Pairwise Overlapping in Genome
Sequencing: {A} Race Between {FPGA} and {GPU}},
booktitle = {{FCCM}},
pages = {127--135},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/fccm/LuXHZL019,
author = {Liqiang Lu and
Jiaming Xie and
Ruirui Huang and
Jiansong Zhang and
Wei Lin and
Yun Liang},
title = {An Efficient Hardware Accelerator for Sparse Convolutional Neural
Networks on FPGAs},
booktitle = {{FCCM}},
pages = {17--25},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/fpga/CoughlinCWKW19,
author = {Aimee Coughlin and
Greg Cusack and
Jack Wampler and
Eric Keller and
Eric Wustrow},
title = {Breaking the Trust Dependence on Third Party Processes for Reconfigurable
Secure Hardware},
booktitle = {{FPGA}},
pages = {282--291},
publisher = {{ACM}},
year = {2019}
}
@inproceedings{DBLP:conf/fpga/GuYSPFXW19,
author = {Yanjie Gu and
Jian Yu and
Tieli Sun and
Chen Pan and
Zhenhao Feng and
Liewei Xu and
Chang Wu},
title = {Highly Efficient Sparse Neural Network Computing: Hardware and Software
Solutions},
booktitle = {{FPGA}},
pages = {121},
publisher = {{ACM}},
year = {2019}
}
@inproceedings{DBLP:conf/fpga/HeKZ19,
author = {Xin He and
Liu Ke and
Xuan Zhang},
title = {SparseBNN: Joint Algorithm/Hardware Optimization to Exploit Structured
Sparsity in Binary Neural Network},
booktitle = {{FPGA}},
pages = {117--118},
publisher = {{ACM}},
year = {2019}
}
@inproceedings{DBLP:conf/fpga/KapralosC19,
author = {Michael P. Kapralos and
John A. Chandy},
title = {HOTMeTaL: Hardware Optimization Tool for Memory Table and Logic Conversion},
booktitle = {{FPGA}},
pages = {307--308},
publisher = {{ACM}},
year = {2019}
}
@inproceedings{DBLP:conf/fpga/ShererFLL19,
author = {Zachary Sherer and
Eric Finnerty and
Yan Luo and
Hang Liu},
title = {Software Hardware Co-Optimized {BFS} on FPGAs},
booktitle = {{FPGA}},
pages = {190},
publisher = {{ACM}},
year = {2019}
}
@inproceedings{DBLP:conf/fpga/YangHWZ0GBLVWK19,
author = {Yifan Yang and
Qijing Huang and
Bichen Wu and
Tianjun Zhang and
Liang Ma and
Giulio Gambardella and
Michaela Blott and
Luciano Lavagno and
Kees A. Vissers and
John Wawrzynek and
Kurt Keutzer},
title = {Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on
Embedded FPGAs},
booktitle = {{FPGA}},
pages = {23--32},
publisher = {{ACM}},
year = {2019}
}
@inproceedings{DBLP:conf/fpl/AgrawalBEK19,
author = {Rashmi S. Agrawal and
Lake Bu and
Alan Ehret and
Michel A. Kinsy},
title = {Open-Source {FPGA} Implementation of Post-Quantum Cryptographic Hardware
Primitives},
booktitle = {{FPL}},
pages = {211--217},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/glvlsi/HuTSRSMSS19,
author = {Bo Hu and
Jingxiang Tian and
Mustafa M. Shihab and
Gaurav Rajavendra Reddy and
William Swartz and
Yiorgos Makris and
Benjamin Carri{\'{o}}n Sch{\"{a}}fer and
Carl Sechen},
title = {Functional Obfuscation of Hardware Accelerators through Selective
Partial Design Extraction onto an Embedded {FPGA}},
booktitle = {{ACM} Great Lakes Symposium on {VLSI}},
pages = {171--176},
publisher = {{ACM}},
year = {2019}
}
@inproceedings{DBLP:conf/ic-nc/KagawaIN19,
author = {Hiroshi Kagawa and
Yasuaki Ito and
Koji Nakano},
title = {Throughput-Optimal Hardware Implementation of {LZW} Decompression
on the {FPGA}},
booktitle = {{CANDAR} Workshops},
pages = {78--83},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/iccd/GeGTXL19,
author = {Jingquan Ge and
Neng Gao and
Chenyang Tu and
Ji Xiang and
Zeyi Liu},
title = {AdapTimer: Hardware/Software Collaborative Timer Resistant to Flush-Based
Cache Attacks on {ARM-FPGA} Embedded SoC},
booktitle = {{ICCD}},
pages = {585--593},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/icce-tw/ChangF19,
author = {Keng{-}Chia Chang and
Chih{-}Peng Fan},
title = {Cost-Efficient Adaboost-based Face Detection with {FPGA} Hardware
Accelerator},
booktitle = {{ICCE-TW}},
pages = {1--2},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/icecsys/ShinOH19,
author = {Duckgyu Shin and
Naoya Onizawa and
Takahiro Hanyu},
title = {{FPGA} Implementation of Binarized Perceptron Learning Hardware Using
{CMOS} Invertible Logic},
booktitle = {{ICECS}},
pages = {115--116},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/icfpt/LuoX19,
author = {Yukui Luo and
Xiaolin Xu},
title = {{HILL:} {A} Hardware Isolation Framework Against Information Leakage
on Multi-Tenant {FPGA} Long-Wires},
booktitle = {{FPT}},
pages = {331--334},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/icfpt/TianPN19,
author = {Ye Tian and
Jean{-}Christophe Pr{\'{e}}votet and
Fabienne Nouvel},
title = {Efficient {OS} Hardware Accelerators Preemption Management in {FPGA}},
booktitle = {{FPT}},
pages = {367--370},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/icm2/HarethMS19,
author = {Sherry Hareth and
Hassan Mostafa and
Khaled Ali Shehata},
title = {Low power {CNN} hardware {FPGA} implementation},
booktitle = {{ICM}},
pages = {162--165},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/icvs/ScharfVLRTVVG19,
author = {Dietmar Scharf and
Bach Le Viet and
Thi Bich Hoa Le and
Janine Rechenberg and
Stefan Tschierschke and
Ernst Vogl and
Ambra Vandone and
Mattia Giardini},
title = {Hardware Accelerated Image Processing on an FPGA-SoC Based Vision
System for Closed Loop Monitoring and Additive Manufacturing Process
Control},
booktitle = {{ICVS}},
series = {Lecture Notes in Computer Science},
volume = {11754},
pages = {3--12},
publisher = {Springer},
year = {2019}
}
@inproceedings{DBLP:conf/iolts/GizopoulosPCR0U19,
author = {Dimitris Gizopoulos and
George Papadimitriou and
Athanasios Chatzidimitriou and
Vijay Janapa Reddi and
Behzad Salami and
Osman S. Unsal and
Adri{\'{a}}n Cristal Kestelman and
Jingwen Leng},
title = {Modern Hardware Margins: CPUs, GPUs, FPGAs Recent System-Level Studies},
booktitle = {{IOLTS}},
pages = {129--134},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/iscas/KolonkoVK19,
author = {Lech Kolonko and
J{\"{o}}rg Velten and
Anton Kummert},
title = {Live Demonstration: {A} Raspberry Pi Based Video Pipeline for 2-D
Wave Digital Filters on Low-Cost {FPGA} Hardware},
booktitle = {{ISCAS}},
pages = {1},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/iscas/KolonkoVK19a,
author = {Lech Kolonko and
J{\"{o}}rg Velten and
Anton Kummert},
title = {A Raspberry Pi Based Video Pipeline for 2-D Wave Digital Filters on
Low-Cost {FPGA} Hardware},
booktitle = {{ISCAS}},
pages = {1--5},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/iscas/PereiraSZM19,
author = {Lucas M. V. Pereira and
Douglas A. dos Santos and
Cesar A. Zeferino and
Douglas R. Melo},
title = {A Low-Cost Hardware Accelerator for {CCSDS} 123 Predictor in {FPGA}},
booktitle = {{ISCAS}},
pages = {1--5},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/ises/0003PCM19,
author = {Samik Basu and
Soumya Pandit and
Amlan Chakrabarti and
Soma Barman Mandal},
title = {{FPGA} Based Hardware Design for Noise Suppression and Seismic Event
Detection},
booktitle = {iSES},
pages = {382--385},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/itc-asia/YangYLHLH19,
author = {Yipei Yang and
Jing Ye and
Xiaowei Li and
Yinhe Han and
Huawei Li and
Yu Hu},
title = {Implementation of Parametric Hardware Trojan in {FPGA}},
booktitle = {ITC-Asia},
pages = {37--42},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/mwscas/BhattiG19,
author = {Faraz Bhatti and
Thomas Greiner},
title = {{HLS} Based Optimizations of an {FPGA} Hardware Design for Plenoptic
Image Processing Algorithm},
booktitle = {{MWSCAS}},
pages = {690--693},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/newcas/RoshdyTSMR19,
author = {Merna Roshdy and
Mohammed F. Tolba and
Lobna A. Said and
Ahmed H. Madian and
Ahmed G. Radwan},
title = {Generic Hardware of Fractional Order Multi-Scrolls Chaotic Generator
Based on {FPGA}},
booktitle = {{NEWCAS}},
pages = {1--4},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/norchip/CabaRBTDL19,
author = {Juli{\'{a}}n Caba and
Fernando Rinc{\'{o}}n and
Jes{\'{u}}s Barba and
Jos{\'{e}} Antonio de la Torre and
Julio Dondo and
Juan Carlos L{\'{o}}pez},
title = {HALib: Hardware Assertion Library for on-board verification of FPGA-based
modules using {HLS}},
booktitle = {{NORCAS}},
pages = {1--7},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/sbcci/FerreiraGS19,
author = {Willian de Assis Pedrobon Ferreira and
Ian Andrew Grout and
Alexandre C{\'{e}}sar Rodrigues da Silva},
title = {{FPGA} hardware linear regression implementation using fixed-point
arithmetic},
booktitle = {{SBCCI}},
pages = {10},
publisher = {{ACM}},
year = {2019}
}
@inproceedings{DBLP:conf/smartcloud/Nan0LCSH19,
author = {Tianhao Nan and
Yongxin Zhu and
Wanyi Li and
Xintong Chen and
Yuefeng Song and
Junjie Hou},
title = {An FPGA-based Hardware Acceleration For Key Steps of Facet Imaging
Algorithm},
booktitle = {SmartCloud},
pages = {86--91},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/smartnets/Al-SharaaIB19,
author = {Sara Al{-}Shara'a and
Raid Khalid Ibraheem and
Oguz Bayat},
title = {Implementation of cryptanalysis based on {FPGA} hardware using {AES}
with {SHA-1}},
booktitle = {SmartNets},
pages = {1--7},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/space/GovindanKDPC19,
author = {Vidya Govindan and
Sandhya Koteshwara and
Amitabh Das and
Keshab K. Parhi and
Rajat Subhra Chakraborty},
title = {ProTro: {A} Probabilistic Counter Based Hardware Trojan Attack on
{FPGA} Based MACSec Enabled Ethernet Switch},
booktitle = {{SPACE}},
series = {Lecture Notes in Computer Science},
volume = {11947},
pages = {159--175},
publisher = {Springer},
year = {2019}
}
@inproceedings{DBLP:conf/tamc/HoraKT19,
author = {Martin Hora and
V{\'{a}}clav Koncick{\'{y}} and
Jakub Tetek},
title = {Theoretical Model of Computation and Algorithms for FPGA-Based Hardware
Accelerators},
booktitle = {{TAMC}},
series = {Lecture Notes in Computer Science},
volume = {11436},
pages = {295--312},
publisher = {Springer},
year = {2019}
}
@article{DBLP:journals/corr/abs-1907-03981,
author = {Xunhua Dai and
Chenxu Ke and
Quan Quan and
Kai{-}Yuan Cai},
title = {Simulation Credibility Assessment Methodology with FPGA-based Hardware-in-the-loop
Platform},
journal = {CoRR},
volume = {abs/1907.03981},
year = {2019}
}
@article{DBLP:journals/corr/abs-1910-05086,
author = {Sergei Skorobogatov},
title = {Hardware Security Evaluation of {MAX} 10 {FPGA}},
journal = {CoRR},
volume = {abs/1910.05086},
year = {2019}
}
@article{DBLP:journals/corr/abs-1911-04378,
author = {Jacob T. Grycel and
Robert J. Walls},
title = {{DRAB-LOCUS:} An Area-Efficient {AES} Architecture for Hardware Accelerator
Co-Location on FPGAs},
journal = {CoRR},
volume = {abs/1911.04378},
year = {2019}
}
@article{DBLP:journals/corr/abs-1911-05944,
author = {Tolulope A. Odetola and
Katie M. Groves and
Syed Rafay Hasan},
title = {2L-3W: 2-Level 3-Way Hardware-Software Co-Verification for the Mapping
of Deep Learning Architecture {(DLA)} onto {FPGA} Boards},
journal = {CoRR},
volume = {abs/1911.05944},
year = {2019}
}
@article{DBLP:journals/iacr/VliegenRCM19,
author = {Jo Vliegen and
Md Masoom Rabbani and
Mauro Conti and
Nele Mentens},
title = {A Novel {FPGA} Architecture and Protocol for the Self-attestation
of Configurable Hardware},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {405},
year = {2019}
}
@article{DBLP:journals/corr/abs-1910-05683,
title = {Hardware/Software Codesign for Training/Testing Multiple Neural Networks
on Multiple FPGAs},
journal = {CoRR},
volume = {abs/1910.05683},
year = {2019},
note = {Withdrawn.}
}
@phdthesis{DBLP:phd/basesearch/Ma18a,
author = {Yufei Ma},
title = {Hardware Acceleration of Deep Convolutional Neural Networks on {FPGA}},
school = {Arizona State University, Tempe, {USA}},
year = {2018}
}
@phdthesis{DBLP:phd/hal/Du18,
author = {Ke Du},
title = {Building and analyzing processing graphs on FPGAs with strong time
and hardware constraints. (Cr{\'{e}}ation et analyse de graphes
de traitements sur FPGA, sous contraintes mat{\'{e}}rielles et
contexte temps r{\'{e}}el dur)},
school = {University of Burgundy - Franche-Comt{\'{e}}, France},
year = {2018}
}
@article{DBLP:journals/access/HussainTBSAA18,
author = {Ahmed A. Hussain and
Nizar Tayem and
Muhammad Omair Butt and
Abdel{-}Hamid Soliman and
Abdulrahman A. Alhamed and
Saleh AlShebeili},
title = {{FPGA} Hardware Implementation of {DOA} Estimation Algorithm Employing
{LU} Decomposition},
journal = {{IEEE} Access},
volume = {6},
pages = {17666--17680},
year = {2018}
}
@article{DBLP:journals/access/LiWPHL18,
author = {Shih{-}An Li and
Wei{-}Yen Wang and
Wei{-}Zheng Pan and
Chen{-}Chien James Hsu and
Cheng{-}Kai Lu},
title = {FPGA-Based Hardware Design for Scale-Invariant Feature Transform},
journal = {{IEEE} Access},
volume = {6},
pages = {43850--43864},
year = {2018}
}
@article{DBLP:journals/access/NguyenHNIP18,
author = {Xuan{-}Thuan Nguyen and
Trong{-}Thuc Hoang and
Hong{-}Thu Nguyen and
Katsumi Inoue and
Cong{-}Kha Pham},
title = {An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index
Creation},
journal = {{IEEE} Access},
volume = {6},
pages = {16046--16059},
year = {2018}
}
@article{DBLP:journals/computers/SharmaKK18,
author = {Dimple Sharma and
Lev Kirischian and
Valeri Kirischian},
title = {Run-Time Mitigation of Power Budget Variations and Hardware Faults
by Structural Adaptation of FPGA-Based Multi-Modal SoPC},
journal = {Comput.},
volume = {7},
number = {4},
pages = {52},
year = {2018}
}
@article{DBLP:journals/csr/BakiriGCO18,
author = {Mohammed Bakiri and
Christophe Guyeux and
Jean{-}Fran{\c{c}}ois Couchot and
Abdelkrim Kamel Oudjida},
title = {Survey on hardware implementation of random number generators on {FPGA:}
Theory and experimental analyses},
journal = {Comput. Sci. Rev.},
volume = {27},
pages = {135--153},
year = {2018}
}
@article{DBLP:journals/ejwcn/YiN18,
author = {Haibo Yi and
Zhe Nie},
title = {High-speed hardware architecture for implementations of multivariate
signature generations on FPGAs},
journal = {{EURASIP} J. Wirel. Commun. Netw.},
volume = {2018},
pages = {93},
year = {2018}
}
@article{DBLP:journals/ieicet/SakakibaraMNM18,
author = {Yuma Sakakibara and
Shin Morishima and
Kohei Nakamura and
Hiroki Matsutani},
title = {A Hardware-Based Caching System on {FPGA} {NIC} for Blockchain},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {101-D},
number = {5},
pages = {1350--1360},
year = {2018}
}
@article{DBLP:journals/jcsc/JiangLLLL18,
author = {Hongxu Jiang and
Shenglan Li and
Huiyong Li and
Tingshan Liu and
Jinyuan Lu},
title = {A High-Performance and Hardware-Efficient PCIe Transmission for a
Multi-Channel Video Using Command Caching and Dynamic Splicing on
{FPGA}},
journal = {J. Circuits Syst. Comput.},
volume = {27},
number = {4},
pages = {1850067:1--1850067:19},
year = {2018}
}
@article{DBLP:journals/jhss/GovindanCSC18,
author = {Vidya Govindan and
Rajat Subhra Chakraborty and
Pranesh Santikellur and
Aditya Kumar Chaudhary},
title = {A Hardware Trojan Attack on FPGA-Based Cryptographic Key Generation:
Impact and Detection},
journal = {J. Hardw. Syst. Secur.},
volume = {2},
number = {3},
pages = {225--239},
year = {2018}
}
@article{DBLP:journals/jmmis/SongK18,
author = {Seok Bin Song and
Jin Heon Kim},
title = {Brief Paper: FPGA-based Hardware Prediction Rendering for Low-Latency
Touch Platform},
journal = {J. Multim. Inf. Syst.},
volume = {5},
number = {1},
pages = {59--62},
year = {2018}
}
@article{DBLP:journals/jsa/ChoiKS18,
author = {Seungdo Choi and
Youngil Kim and
Yong Ho Song},
title = {False history filtering for reducing hardware overhead of FPGA-based
{LZ77} compressor},
journal = {J. Syst. Archit.},
volume = {88},
pages = {110--119},
year = {2018}
}
@article{DBLP:journals/spic/HajiRassoulihaT18,
author = {Amir HajiRassouliha and
Andrew J. Taberner and
Martyn P. Nash and
Poul M. F. Nielsen},
title = {Suitability of recent hardware accelerators (DSPs, FPGAs, and GPUs)
for computer vision and image processing algorithms},
journal = {Signal Process. Image Commun.},
volume = {68},
pages = {101--119},
year = {2018}
}
@article{DBLP:journals/tcad/AghaieKA18,
author = {Anita Aghaie and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {Reliable and Fault Diagnosis Architectures for Hardware and Software-Efficient
Block Cipher {KLEIN} Benchmarked on {FPGA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {901--905},
year = {2018}
}
@article{DBLP:journals/tcad/LiangSZ18,
author = {Hao Liang and
Sharad Sinha and
Wei Zhang},
title = {Parallelizing Hardware Tasks on Multicontext {FPGA} With Efficient
Placement and Scheduling Algorithms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {350--363},
year = {2018}
}
@article{DBLP:journals/tcas/CheangMM18,
author = {Chak{-}Fong Cheang and
Pui{-}In Mak and
Rui Paulo Martins},
title = {A Hardware-Efficient Feedback Polynomial Topology for {DPD} Linearization
of Power Amplifiers: Theory and {FPGA} Validation},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {65-I},
number = {9},
pages = {2889--2902},
year = {2018}
}
@article{DBLP:journals/tcsv/SeyidRCL18,
author = {Kerem Seyid and
Andrea Richaud and
Raffaele Capoccia and
Yusuf Leblebici},
title = {FPGA-Based Hardware Implementation of Real-Time Optical Flow Calculation},
journal = {{IEEE} Trans. Circuits Syst. Video Technol.},
volume = {28},
number = {1},
pages = {206--216},
year = {2018}
}
@article{DBLP:journals/tdsc/Lumbiarres-Lopez18,
author = {Ruben Lumbiarres{-}Lopez and
Mariano L{\'{o}}pez{-}Garc{\'{\i}}a and
Enrique F. Cant{\'{o}}{-}Navarro},
title = {Hardware Architecture Implemented on {FPGA} for Protecting Cryptographic
Keys against Side-Channel Attacks},
journal = {{IEEE} Trans. Dependable Secur. Comput.},
volume = {15},
number = {5},
pages = {898--905},
year = {2018}
}
@article{DBLP:journals/tie/XuLXLJ18,
author = {Yunwen Xu and
Dewei Li and
Yugeng Xi and
Jian Lan and
Tengfei Jiang},
title = {An Improved Predictive Controller on the {FPGA} by Hardware Matrix
Inversion},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {65},
number = {9},
pages = {7395--7405},
year = {2018}
}
@article{DBLP:journals/tjs/YazdinejadBJ18,
author = {Abbas Yazdinejad and
Ali Bohlooli and
Kamal Jamshidi},
title = {Efficient design and hardware implementation of the OpenFlow v1.3
Switch on the Virtex-6 {FPGA} {ML605}},
journal = {J. Supercomput.},
volume = {74},
number = {3},
pages = {1299--1320},
year = {2018}
}
@article{DBLP:journals/vlsisp/IngemarssonG18,
author = {Carl Ingemarsson and
Oscar Gustafsson},
title = {{SFF} - The Single-Stream FPGA-Optimized Feedforward {FFT} Hardware
Architecture},
journal = {J. Signal Process. Syst.},
volume = {90},
number = {11},
pages = {1583--1592},
year = {2018}
}
@inproceedings{DBLP:conf/ahs/DorflingerASFMK18,
author = {Alexander D{\"{o}}rflinger and
Mark Albers and
Johannes Schlatow and
Bj{\"{o}}rn Fiethe and
Harald Michalik and
Phillip Keldenich and
S{\'{a}}ndor P. Fekete},
title = {Hardware and Software Task Scheduling for {ARM-FPGA} Platforms},
booktitle = {{AHS}},
pages = {66--73},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/ahs/Fahmy18,
author = {Suhaib A. Fahmy},
title = {Design Abstraction for Autonomous Adaptive Hardware Systems on FPGAs},
booktitle = {{AHS}},
pages = {142--147},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/arc/KachrisSKS18,
author = {Christoforos Kachris and
Ioannis Stamelos and
Elias Koromilas and
Dimitrios Soudris},
title = {Seamless {FPGA} Deployment over Spark in Cloud Computing: {A} Use
Case on Machine Learning Hardware Acceleration},
booktitle = {{ARC}},
series = {Lecture Notes in Computer Science},
volume = {10824},
pages = {673--684},
publisher = {Springer},
year = {2018}
}
@inproceedings{DBLP:conf/asplos/MoreauCC18,
author = {Thierry Moreau and
Tianqi Chen and
Luis Ceze},
title = {Leveraging the {VTA-TVM} Hardware-Software Stack for {FPGA} Acceleration
of 8-bit ResNet-18 Inference},
booktitle = {ReQuEST@ASPLOS},
pages = {5},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/ats/YeH018,
author = {Jing Ye and
Yu Hu and
Xiaowei Li},
title = {Hardware Trojan in {FPGA} {CNN} Accelerator},
booktitle = {{ATS}},
pages = {68--73},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/ccs/MartinasekHSMMK18,
author = {Zdenek Martinasek and
Jan Hajny and
David Smekal and
Lukas Malina and
Denis Matousek and
Michal Kekely and
Nele Mentens},
title = {200 Gbps Hardware Accelerated Encryption System for {FPGA} Network
Cards},
booktitle = {ASHES@CCS},
pages = {11--17},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/ccs/YoonSJCKKK18,
author = {Junghwan Yoon and
Yezee Seo and
Jaedong Jang and
Mingi Cho and
JinGoog Kim and
HyeonSook Kim and
Taekyoung Kwon},
title = {A Bitstream Reverse Engineering Tool for {FPGA} Hardware Trojan Detection},
booktitle = {{CCS}},
pages = {2318--2320},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/cist/Bousmar18,
author = {Khadija Bousmar},
title = {A Pure Hardware k-SAT Solver for {FPGA}},
booktitle = {{CIST}},
pages = {481--485},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/csae/ZhongLWZL18,
author = {Baoyan Zhong and
Xiaofeng Lu and
Qiaoyuan Wang and
Siqi Zhao and
Qianyun Liu},
title = {A Hardware Architecture of Target Tracking System on {FPGA}},
booktitle = {{CSAE}},
pages = {65:1--65:5},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/dac/LiuKWC18,
author = {Xinheng Liu and
Dae Hee Kim and
Chang Wu and
Deming Chen},
title = {Resource and data optimization for hardware implementation of deep
neural networks targeting FPGA-based edge devices},
booktitle = {SLIP@DAC},
pages = {1:1--1:8},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/dac/UllahRPKH0018,
author = {Salim Ullah and
Semeen Rehman and
Bharath Srinivas Prabakaran and
Florian Kriebel and
Muhammad Abdullah Hanif and
Muhammad Shafique and
Akash Kumar},
title = {Area-optimized low-latency approximate multipliers for FPGA-based
hardware accelerators},
booktitle = {{DAC}},
pages = {159:1--159:6},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/data2/DhibTM18,
author = {Farah Dhib and
Elmehdi Tatar and
Mohsen Machhout},
title = {Hardware implementation of a fingerprint recognition algorithm on
{FPGA} cyclone {II}},
booktitle = {{DATA}},
pages = {5:1--5:7},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/dsd/FournarisPK18,
author = {Apostolos P. Fournaris and
Lampros Pyrgas and
Paris Kitsos},
title = {An {FPGA} Hardware Trojan Detection Approach Based on Multiple Parameter
Analysis},
booktitle = {{DSD}},
pages = {516--522},
publisher = {{IEEE} Computer Society},
year = {2018}
}
@inproceedings{DBLP:conf/dsd/GuhaMSC18,
author = {Krishnendu Guha and
Atanu Majumder and
Debasri Saha and
Amlan Chakrabarti},
title = {Reliability Driven Mixed Critical Tasks Processing on FPGAs Against
Hardware Trojan Attacks},
booktitle = {{DSD}},
pages = {537--544},
publisher = {{IEEE} Computer Society},
year = {2018}
}
@inproceedings{DBLP:conf/fccm/WijesunderaPPHS18,
author = {Deshya Wijesundera and
Alok Prakash and
Thilina Perera and
Kalindu Herath and
Thambipillai Srikanthan},
title = {Wibheda: Framework for Data Dependency-Aware Multi-Constrained Hardware-Software
Partitioning in FPGA-Based SoCs for IoT Devices},
booktitle = {{FCCM}},
pages = {213},
publisher = {{IEEE} Computer Society},
year = {2018}
}
@inproceedings{DBLP:conf/fpga/DingZMG18,
author = {Nan Ding and
Wei Zhang and
Yanhua Ma and
Zhenguo Gao},
title = {Software/Hardware Co-design for Multichannel Scheduling in {IEEE}
802.11p {MLME:} (Abstract Only)},
booktitle = {{FPGA}},
pages = {289},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/fpga/GuerrieriKALBI18,
author = {Andrea Guerrieri and
Sahand Kashani{-}Akhavan and
Mikhail Asiatici and
Pasquale Lombardi and
Bilel Belhadj and
Paolo Ienne},
title = {LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing
Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only)},
booktitle = {{FPGA}},
pages = {295},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/fpt/HategekimanaMPB18,
author = {Festus Hategekimana and
Joel Mandebi Mbongue and
Md Jubaer Hossain Pantho and
Christophe Bobda},
title = {Secure Hardware Kernels Execution in {CPU+FPGA} Heterogeneous Cloud},
booktitle = {{FPT}},
pages = {182--189},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/glvlsi/DingRYMLLYW18,
author = {Caiwen Ding and
Ao Ren and
Geng Yuan and
Xiaolong Ma and
Jiayu Li and
Ning Liu and
Bo Yuan and
Yanzhi Wang},
title = {Structured Weight Matrices-Based Hardware Accelerators in Deep Neural
Networks: FPGAs and ASICs},
booktitle = {{ACM} Great Lakes Symposium on {VLSI}},
pages = {353--358},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/heart/MohsinP18,
author = {Mokhles A. Mohsin and
Darshika G. Perera},
title = {An FPGA-Based Hardware Accelerator for K-Nearest Neighbor Classification
for Machine Learning on Mobile Devices},
booktitle = {{HEART}},
pages = {16:1--16:7},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/heart/SchmitzZ18,
author = {Jesse Schmitz and
Lei Zhang},
title = {{FPGA} Hardware Implementation and Optimization for Neural Network
based Chaotic System Design},
booktitle = {{HEART}},
pages = {18:1--18:6},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/heart/WijesunderaPPHS18,
author = {Deshya Wijesundera and
Alok Prakash and
Thilina Perera and
Kalindu Herath and
Thambipillai Srikanthan},
title = {Wibheda+: Framework for Data Dependency-aware Multi-constrained Hardware-Software
Partitioning in FPGA-based SoCs for IoT Applications},
booktitle = {{HEART}},
pages = {3:1--3:6},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/icacci/BhardwajCL18,
author = {Aastha Bhardwaj and
Surbhi Chhabra and
Kusum Lata},
title = {{FPGA} Implementation of Traffic Light Controller and its Analysis
in the Presence of Hardware Trojan},
booktitle = {{ICACCI}},
pages = {375--380},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/iccad/MaZ0VS18,
author = {Yufei Ma and
Tu Zheng and
Yu Cao and
Sarma B. K. Vrudhula and
Jae{-}sun Seo},
title = {Algorithm-hardware co-design of single shot detector for fast object
detection on FPGAs},
booktitle = {{ICCAD}},
pages = {57},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/iccad/YeF018,
author = {Mengmei Ye and
Xianglong Feng and
Sheng Wei},
title = {{HISA:} hardware isolation-based secure architecture for {CPU-FPGA}
embedded systems},
booktitle = {{ICCAD}},
pages = {90},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/iccad/ZhangWZLXHC18,
author = {Xiaofan Zhang and
Junsong Wang and
Chao Zhu and
Yonghua Lin and
Jinjun Xiong and
Wen{-}Mei W. Hwu and
Deming Chen},
title = {DNNBuilder: an automated tool for building high-performance {DNN}
hardware accelerators for FPGAs},
booktitle = {{ICCAD}},
pages = {56},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/iciot2/AlhafidhDAA18,
author = {Basman M. Hasan Alhafidh and
Amar I. Daood and
Mohammed M. Alawad and
William H. Allen},
title = {{FPGA} Hardware Implementation of Smart Home Autonomous System Based
on Deep Learning},
booktitle = {{ICIOT}},
series = {Lecture Notes in Computer Science},
volume = {10972},
pages = {121--133},
publisher = {Springer},
year = {2018}
}
@inproceedings{DBLP:conf/iconip/AokiKS18,
author = {Shunsuke Aoki and
Seitaro Koyama and
Toshimichi Saito},
title = {{FPGA} Based Hardware Implementation of Simple Dynamic Binary Neural
Networks},
booktitle = {{ICONIP} {(7)}},
series = {Lecture Notes in Computer Science},
volume = {11307},
pages = {647--655},
publisher = {Springer},
year = {2018}
}
@inproceedings{DBLP:conf/icteri/KolesnykKP18,
author = {Inna Kolesnyk and
Vitaliy Kulanov and
Artem Perepelitsyn},
title = {Markov Model of {FPGA} Resources as a Service Considering Hardware
Failures},
booktitle = {PhD@ICTERI},
series = {{CEUR} Workshop Proceedings},
volume = {2122},
pages = {56--62},
publisher = {CEUR-WS.org},
year = {2018}
}
@inproceedings{DBLP:conf/iecon/Gil-NarvionNSL18,
author = {Jos{\'{e}} Miguel Gil{-}Narvi{\'{o}}n and
Denis Navarro and
Hector Sarnago and
Oscar Luc{\'{\i}}a},
title = {FPGA-Based Hardware in the Loop Test-Bench for Robust Software Development
of Induction Heating Appliances},
booktitle = {{IECON}},
pages = {3497--3501},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/iecon/KeikhaFMF18,
author = {Mahsa Keikha and
Xiaoliang Fu and
Mehrdad Moallem and
Ken Fong},
title = {Development of {FPGA} based Hardware-in-the-loop Simulator for {RF}
Cavity Resonator},
booktitle = {{IECON}},
pages = {2256--2261},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/iecon/ParmarS18,
author = {Yashrajsinh Parmar and
K. Sridharan},
title = {Hardware-Efficient Velocity Estimation of Dynamic Obstacles Based
on a Novel Radix-4 {CORDIC} and {FPGA} Implementation},
booktitle = {{IECON}},
pages = {3770--3775},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/iecon/SaengerH18,
author = {P. Saenger and
Micka{\"{e}}l Hilairet},
title = {Hardware-In-the-Loop simulation of a DC-machine with {INTEL} {FPGA}
boards},
booktitle = {{IECON}},
pages = {2815--2820},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/ipccc/JadhavGDKN18,
author = {Shrikant S. Jadhav and
Clay Gloster and
Christopher C. Doss and
Youngsoo Kim and
Jannatun Naher},
title = {AutoRARE: An Automated Tool For Generating FPGA-Based Multi-Memory
Hardware Accelerators For Compute-Intensive Applications},
booktitle = {{IPCCC}},
pages = {1--8},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/ipps/PodobasM18,
author = {Artur Podobas and
Satoshi Matsuoka},
title = {Hardware Implementation of POSITs and Their Application in FPGAs},
booktitle = {{IPDPS} Workshops},
pages = {138--145},
publisher = {{IEEE} Computer Society},
year = {2018}
}
@inproceedings{DBLP:conf/ipps/TucciCCHDS18,
author = {Lorenzo Di Tucci and
Davide Conficconi and
Alessandro Comodi and
Steven A. Hofmeyr and
David Donofrio and
Marco D. Santambrogio},
title = {A Parallel, Energy Efficient Hardware Architecture for the merAligner
on {FPGA} Using Chisel {HCL}},
booktitle = {{IPDPS} Workshops},
pages = {214--217},
publisher = {{IEEE} Computer Society},
year = {2018}
}
@inproceedings{DBLP:conf/iscas/KarimHMGLHTTMJ18,
author = {Shvan Karim and
Jim Harkin and
Liam McDaid and
Bryan Gardiner and
Junxiu Liu and
David M. Halliday and
Andy M. Tyrrell and
Jon Timmis and
Alan G. Millard and
Anju P. Johnson},
title = {FPGA-based Fault-injection and Data Acquisition of Self-repairing
Spiking Neural Network Hardware},
booktitle = {{ISCAS}},
pages = {1--5},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/iscas/WeidleVMZ18,
author = {Guilherme F. Weidle and
Felipe Viel and
Douglas Rossi de Melo and
Cesar A. Zeferino},
title = {A Hardware Accelerator for Anisotropic Diffusion Filtering in {FPGA}},
booktitle = {{ISCAS}},
pages = {1--5},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/isda/RamCSS18,
author = {R. Gautham Sundar Ram and
Nitin Chaturvedi and
Sumeet Saurav and
Sanjay Singh},
title = {An {FPGA} Based Hardware Accelerator for Classification of Handwritten
Digits},
booktitle = {{ISDA} {(1)}},
series = {Advances in Intelligent Systems and Computing},
volume = {940},
pages = {945--954},
publisher = {Springer},
year = {2018}
}
@inproceedings{DBLP:conf/ised/VaniCK18,
author = {G. Divya Vani and
M. C. Chinnaiah and
Srinivasa Rao Karumuri},
title = {Hardware Scheme for Autonomous Docking Algorithm using {FPGA} based
Mobile Robot},
booktitle = {{ISED}},
pages = {110--115},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/isqed/NazemiEP18,
author = {Mahdi Nazemi and
Amir Erfan Eshratifar and
Massoud Pedram},
title = {A hardware-friendly algorithm for scalable training and deployment
of dimensionality reduction models on {FPGA}},
booktitle = {{ISQED}},
pages = {395--400},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/isvlsi/KamaliAGHS18,
author = {Hadi Mardani Kamali and
Kimia Zamiri Azar and
Kris Gaj and
Houman Homayoun and
Avesta Sasan},
title = {LUT-Lock: {A} Novel LUT-Based Logic Obfuscation for FPGA-Bitstream
and ASIC-Hardware Protection},
booktitle = {{ISVLSI}},
pages = {405--410},
publisher = {{IEEE} Computer Society},
year = {2018}
}
@inproceedings{DBLP:conf/ivsw/MahmudOK18,
author = {Shakil Mahmud and
Brooks Olney and
Robert Karam},
title = {Architectural Diversity: Bio-Inspired Hardware Security for FPGAs},
booktitle = {{IVSW}},
pages = {48--51},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/mbmv/RiessBS18,
author = {Marcel Rie{\ss} and
Cedrik Bock and
Frank Slomka},
title = {Generic Reusable Hardware/Software Co-Design Implementation of a Complete
{FH-FSK} Modem for Robust Multi-User Acoustic Underwater Communication
and System Validation on a {FPGA}},
booktitle = {{MBMV}},
publisher = {Universit{\"{a}}t T{\"{u}}bingen},
year = {2018}
}
@inproceedings{DBLP:conf/micsecs/DorofeevaND18,
author = {Eleonora Dorofeeva and
Danila Nikiforovskii and
Ivan Deyneka},
title = {Features of the hardware implementation of real time Hough transform
on {FPGA}},
booktitle = {{MICSECS}},
series = {{CEUR} Workshop Proceedings},
volume = {2344},
publisher = {CEUR-WS.org},
year = {2018}
}
@inproceedings{DBLP:conf/micsecs/NikiforovskiiDS18,
author = {Danila Nikiforovskii and
Ivan Deyneka and
Daniil Smirnov},
title = {Features of hardware implementation of Particle Swarm Optimization
{(PSO)} on {FPGA}},
booktitle = {{MICSECS}},
series = {{CEUR} Workshop Proceedings},
volume = {2344},
publisher = {CEUR-WS.org},
year = {2018}
}
@inproceedings{DBLP:conf/mwscas/NairMG18,
author = {Arathy B. Nair and
Arijit Mondal and
Shayan Srinivasa Garani},
title = {A Low-complexity Hardware {AWGN} Channel Emulator on {FPGA} using
Central Limit Theorem},
booktitle = {{MWSCAS}},
pages = {428--431},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/mwscas/WuHMMGZ18,
author = {Zhongpan Wu and
Karim Hammad and
Robinson Mittmann and
Sebastian Magierowski and
Ebrahim Ghafar{-}Zadeh and
Xiaoyong Zhong},
title = {FPGA-based {DNA} Basecalling Hardware Acceleration},
booktitle = {{MWSCAS}},
pages = {1098--1101},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/noms/NagyOTKV18,
author = {Bal{\'{a}}zs Nagy and
Peter Orosz and
Tamas Tothfalusi and
L{\'{a}}szl{\'{o}} Kov{\'{a}}cs and
P{\'{a}}l Varga},
title = {Detecting DDoS attacks within milliseconds by using FPGA-based hardware
acceleration},
booktitle = {{NOMS}},
pages = {1--4},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/racs/HungHYLL18,
author = {Shih{-}Hao Hung and
Yi{-}Mo Ho and
Chih Wei Yeh and
Cheng{-}Yueh Liu and
Chen{-}Pang Lee},
title = {Hardware-accelerated cache simulation for multicore by {FPGA}},
booktitle = {{RACS}},
pages = {231--236},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/reconfig/AkgunKEG18,
author = {G{\"{o}}khan Akg{\"{u}}n and
Habib ul Hasan Khan and
Mahmoud Ahmed Elshimy and
Diana G{\"{o}}hringer},
title = {Dynamic tunable and reconfigurable hardware controller with EKF-based
state reconstruction through FPGA-in the loop},
booktitle = {ReConFig},
pages = {1--8},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/reconfig/AveyJZ18,
author = {Joe Avey and
Phillip H. Jones and
Joseph Zambreno},
title = {An FPGA-based Hardware Accelerator for Iris Segmentation},
booktitle = {ReConFig},
pages = {1--8},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/socc/CacciottiCSPE18,
author = {Mattia Cacciotti and
Vincent Camus and
Jeremy Schlachter and
Alessandro Pezzotta and
Christian C. Enz},
title = {Hardware Acceleration of HDR-Image Tone Mapping on an {FPGA-CPU} Platform
Through High-Level Synthesis},
booktitle = {SoCC},
pages = {158--162},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/tsp/SmekalHM18,
author = {David Smekal and
Jan Hajny and
Zdenek Martinasek},
title = {Hardware-Accelerated Twofish Core for {FPGA}},
booktitle = {{TSP}},
pages = {1--5},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/vlsi/JuniorB18,
author = {Luiz Antonio de Oliveira Junior and
Edna Barros},
title = {An FPGA-based Hardware Accelerator for Scene Text Character Recognition},
booktitle = {VLSI-SoC},
pages = {125--130},
publisher = {{IEEE}},
year = {2018}
}
@incollection{DBLP:books/sp/18/SanoN18,
author = {Kentaro Sano and
Hiroki Nakahara},
title = {Hardware Algorithms},
booktitle = {Principles and Structures of FPGAs},
pages = {137--177},
publisher = {Springer},
year = {2018}
}
@article{DBLP:journals/corr/abs-1801-04014,
author = {Mahdi Nazemi and
Amir Erfan Eshratifar and
Massoud Pedram},
title = {A Hardware-Friendly Algorithm for Scalable Training and Deployment
of Dimensionality Reduction Models on {FPGA}},
journal = {CoRR},
volume = {abs/1801.04014},
year = {2018}
}
@article{DBLP:journals/corr/abs-1803-11207,
author = {Xuan{-}Thuan Nguyen and
Trong{-}Thuc Hoang and
Hong{-}Thu Nguyen and
Katsumi Inoue and
Cong{-}Kha Pham},
title = {An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index
Creation},
journal = {CoRR},
volume = {abs/1803.11207},
year = {2018}
}
@article{DBLP:journals/corr/abs-1804-11239,
author = {Caiwen Ding and
Ao Ren and
Geng Yuan and
Xiaolong Ma and
Jiayu Li and
Ning Liu and
Bo Yuan and
Yanzhi Wang},
title = {Structured Weight Matrices-Based Hardware Accelerators in Deep Neural
Networks: FPGAs and ASICs},
journal = {CoRR},
volume = {abs/1804.11239},
year = {2018}
}
@article{DBLP:journals/corr/abs-1804-11275,
author = {Hadi Mardani Kamali and
Kimia Zamiri Azar and
Kris Gaj and
Houman Homayoun and
Avesta Sasan},
title = {LUT-Lock: {A} Novel LUT-based Logic Obfuscation for FPGA-Bitstream
and ASIC-Hardware Protection},
journal = {CoRR},
volume = {abs/1804.11275},
year = {2018}
}
@article{DBLP:journals/corr/abs-1807-03611,
author = {Martin Hora and
V{\'{a}}clav Koncick{\'{y}} and
Jakub Tetek},
title = {Theoretical Model of Computation and Algorithms for FPGA-based Hardware
Accelerators},
journal = {CoRR},
volume = {abs/1807.03611},
year = {2018}
}
@article{DBLP:journals/corr/abs-1811-08634,
author = {Yifan Yang and
Qijing Huang and
Bichen Wu and
Tianjun Zhang and
Liang Ma and
Giulio Gambardella and
Michaela Blott and
Luciano Lavagno and
Kees A. Vissers and
John Wawrzynek and
Kurt Keutzer},
title = {Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on
Embedded FPGAs},
journal = {CoRR},
volume = {abs/1811.08634},
year = {2018}
}
@phdthesis{DBLP:phd/dnb/Werner17,
author = {Stefan Werner},
title = {Hybrid architecture for hardware-accelerated query processing in semantic
web databases based on runtime reconfigurable FPGAs},
school = {University of L{\"{u}}beck, Germany},
year = {2017}
}
@article{DBLP:journals/access/EbrahimiZ17,
author = {Abbas Ebrahimi and
Mohammad Zandsalimy},
title = {Evaluation of {FPGA} Hardware as a New Approach for Accelerating the
Numerical Solution of {CFD} Problems},
journal = {{IEEE} Access},
volume = {5},
pages = {9717--9727},
year = {2017}
}
@article{DBLP:journals/asc/BenrejebS17,
author = {Mohamed Sadok Ben Ameur and
Anis Sakly},
title = {{FPGA} based hardware implementation of Bat Algorithm},
journal = {Appl. Soft Comput.},
volume = {58},
pages = {378--387},
year = {2017}
}
@article{DBLP:journals/concurrency/LiGQDL17,
author = {Yibin Li and
Keke Gai and
Meikang Qiu and
Wenyun Dai and
Meiqin Liu},
title = {Adaptive human detection approach using FPGA-based parallel architecture
in reconfigurable hardware},
journal = {Concurr. Comput. Pract. Exp.},
volume = {29},
number = {14},
year = {2017}
}
@article{DBLP:journals/elektrik/AbdelaliKM17,
author = {Abdessalem Ben Abdelali and
Mohamed Nidhal Krifa and
Abdellatif Mtibaa},
title = {FPGA-based {SOC} for hardware implementation of a local histogram-based
video shot detector},
journal = {Turkish J. Electr. Eng. Comput. Sci.},
volume = {25},
pages = {3300--3318},
year = {2017}
}
@article{DBLP:journals/ieicet/BlockM17,
author = {Henry Block and
Tsutomu Maruyama},
title = {{FPGA} Hardware Acceleration of a Phylogenetic Tree Reconstruction
with Maximum Parsimony Algorithm},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {100-D},
number = {2},
pages = {256--264},
year = {2017}
}
@article{DBLP:journals/iet-cdt/ParmarRD17,
author = {Chintan A. Parmar and
Bhaskar Ramanadham and
Anand D. Darji},
title = {{FPGA} implementation of hardware efficient adaptive filter robust
to impulsive noise},
journal = {{IET} Comput. Digit. Tech.},
volume = {11},
number = {3},
pages = {107--116},
year = {2017}
}
@article{DBLP:journals/ijcomsys/StuartP17,
author = {Celine Mary Stuart and
Deepthi P. Pattathil},
title = {{FPGA} implementation of highly secure, hardware-efficient {QC-LDPC}
code-based nonlinear cryptosystem for wireless sensor networks},
journal = {Int. J. Commun. Syst.},
volume = {30},
number = {10},
year = {2017}
}
@article{DBLP:journals/ijhpcn/WangBP17,
author = {Wei Wang and
Miodrag Bolic and
Jonathan Parri},
title = {pvFPGA: paravirtualising an FPGA-based hardware accelerator towards
general purpose computing},
journal = {Int. J. High Perform. Comput. Netw.},
volume = {10},
number = {3},
pages = {179--193},
year = {2017}
}
@article{DBLP:journals/ijig/Nnolim17,
author = {Uche Afam Nnolim},
title = {FPGA-Based Multiplier-Less Log-Based Hardware Architectures for Hybrid
Color Image Enhancement System},
journal = {Int. J. Image Graph.},
volume = {17},
number = {1},
pages = {1750004:1--1750004:53},
year = {2017}
}
@article{DBLP:journals/ijig/Nnolim17a,
author = {Uche Afam Nnolim},
title = {FPGA-Based Hardware Architecture for Fuzzy Homomorphic Enhancement
Based on Partial Differential Equations},
journal = {Int. J. Image Graph.},
volume = {17},
number = {4},
pages = {1750022:1--1750022:46},
year = {2017}
}
@article{DBLP:journals/ijwmc/Al-HussainiAVHF17,
author = {Khalid Al{-}Hussaini and
Borhanuddin Mohd Ali and
Pooria Varahram and
Shaiful J. Hashim and
Ronan Farrell},
title = {Hardware co-simulation for a low complexity {PAPR} reduction scheme
on an {FPGA}},
journal = {Int. J. Wirel. Mob. Comput.},
volume = {12},
number = {1},
pages = {49--61},
year = {2017}
}
@article{DBLP:journals/jcsc/ZaidanZ17,
author = {B. B. Zaidan and
A. A. Zaidan},
title = {Software and Hardware FPGA-Based Digital Watermarking and Steganography
Approaches: Toward New Methodology for Evaluation and Benchmarking
Using Multi-Criteria Decision-Making Techniques},
journal = {J. Circuits Syst. Comput.},
volume = {26},
number = {7},
pages = {1750116:1--1750116:27},
year = {2017}
}
@article{DBLP:journals/jrtip/SahlbachTE17,
author = {Henning Sahlbach and
Daniel Thiele and
Rolf Ernst},
title = {A system-level {FPGA} design methodology for video applications with
weakly-programmable hardware components},
journal = {J. Real Time Image Process.},
volume = {13},
number = {2},
pages = {291--309},
year = {2017}
}
@article{DBLP:journals/jsa/SirkunanOSHM17,
author = {Jeevan Sirkunan and
Chia Yee Ooi and
Nasir Shaikh{-}Husin and
Yuan Wen Hau and
Muhammad N. Marsono},
title = {Hardware transactional memory architecture with adaptive version management
for multi-processor {FPGA} platforms},
journal = {J. Syst. Archit.},
volume = {73},
pages = {42--52},
year = {2017}
}
@article{DBLP:journals/mam/MandalPSCC17,
author = {Swagata Mandal and
Rourab Paul and
Suman Sau and
Amlan Chakrabarti and
Subhasis Chattopadhyay},
title = {Efficient dynamic priority based soft error mitigation techniques
for configuration memory of {FPGA} hardware},
journal = {Microprocess. Microsystems},
volume = {51},
pages = {313--330},
year = {2017}
}
@article{DBLP:journals/mam/MiskovskyKN17,
author = {Vojtech Miskovsk{\'{y}} and
Hana Kub{\'{a}}tov{\'{a}} and
Martin Novotn{\'{y}}},
title = {Influence of passive hardware redundancy on differential power analysis
resistance of {AES} cipher implemented in {FPGA}},
journal = {Microprocess. Microsystems},
volume = {51},
pages = {220--226},
year = {2017}
}
@article{DBLP:journals/mam/PirpilidisSVK17,
author = {Filippos Pirpilidis and
Kyriakos G. Stefanidis and
Artemios G. Voyiatzis and
Paris Kitsos},
title = {On the effects of ring oscillator length and hardware Trojan size
on an FPGA-based implementation of {AES}},
journal = {Microprocess. Microsystems},
volume = {54},
pages = {75--82},
year = {2017}
}
@article{DBLP:journals/mam/WijeyasingheT17,
author = {Marlon Wijeyasinghe and
David Thomas},
title = {Combining hardware and software codecs to enhance data channels in
{FPGA} streaming systems},
journal = {Microprocess. Microsystems},
volume = {51},
pages = {275--288},
year = {2017}
}
@article{DBLP:journals/tcas/Lara-NinoDM17,
author = {Carlos Andres Lara{-}Nino and
Arturo Diaz{-}Perez and
Miguel Morales{-}Sandoval},
title = {Lightweight Hardware Architectures for the Present Cipher in {FPGA}},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {64-I},
number = {9},
pages = {2544--2555},
year = {2017}
}
@article{DBLP:journals/tcas/TakedaT17,
author = {Kentaro Takeda and
Hiroyuki Torikai},
title = {A Novel Hardware-Efficient Cochlea Model Based on Asynchronous Cellular
Automaton Dynamics: Theoretical Analysis and {FPGA} Implementation},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {64-II},
number = {9},
pages = {1107--1111},
year = {2017}
}
@article{DBLP:journals/tci/ChenHHC17,
author = {Huan{-}Yuan Chen and
Shu{-}Hao Hsu and
Wen{-}Jyi Hwang and
Chau{-}Jern Cheng},
title = {An Efficient FPGA-Based Parallel Phase Unwrapping Hardware Architecture},
journal = {{IEEE} Trans. Computational Imaging},
volume = {3},
number = {4},
pages = {996--1007},
year = {2017}
}
@article{DBLP:journals/tvlsi/ChoiBA17,
author = {Jongsok Choi and
Stephen Dean Brown and
Jason Helge Anderson},
title = {From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis
for FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2867--2880},
year = {2017}
}
@article{DBLP:journals/tvlsi/ShiLYO17,
author = {Weijing Shi and
Xin Li and
Zhiyi Yu and
Gary Overett},
title = {An FPGA-Based Hardware Accelerator for Traffic Sign Detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1362--1372},
year = {2017}
}
@article{DBLP:journals/wpc/Al-HussainiAVH17,
author = {Khalid Al{-}Hussaini and
Borhanuddin Mohd Ali and
Pooria Varahram and
Shaiful Jahari Hashim},
title = {Designing and Implementing a Novel Single {IFFT} Scrambling {PAPR}
Reduction Scheme in {OFDM} Systems Using {FPGA} with Hardware Co-simulation},
journal = {Wirel. Pers. Commun.},
volume = {95},
number = {4},
pages = {4763--4788},
year = {2017}
}
@inproceedings{DBLP:conf/ahs/SharmaKK17,
author = {Dimple Sharma and
Lev Kirischian and
Valeri Kirischian},
title = {Run-time adaptation method for mitigation of hardware faults and power
budget variations in space-borne FPGA-based systems},
booktitle = {{AHS}},
pages = {32--39},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/arc/SantosTBTK17,
author = {Andr{\'{e}} Flores dos Santos and
Lucas Antunes Tambara and
Fabio Benevenuti and
Jorge L. Tonfat and
Fernanda Lima Kastensmidt},
title = {Applying {TMR} in Hardware Accelerators Generated by High-Level Synthesis
Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs},
booktitle = {{ARC}},
series = {Lecture Notes in Computer Science},
volume = {10216},
pages = {202--213},
year = {2017}
}
@inproceedings{DBLP:conf/ches/JacobHZRS17,
author = {Nisha Jacob and
Johann Heyszl and
Andreas Zankl and
Carsten Rolfes and
Georg Sigl},
title = {How to Break Secure Boot on {FPGA} SoCs Through Malicious Hardware},
booktitle = {{CHES}},
series = {Lecture Notes in Computer Science},
volume = {10529},
pages = {425--442},
publisher = {Springer},
year = {2017}
}
@inproceedings{DBLP:conf/cicba/MandalMPC17,
author = {Himadri S. Mandal and
Goutam Kr. Maity and
Amit Phadikar and
Tien{-}Lung Chiu},
title = {{FPGA} Based Low Power Hardware Implementation for Quality Access
Control of a Compressed Gray Scale Image},
booktitle = {{CICBA} {(1)}},
series = {Communications in Computer and Information Science},
volume = {775},
pages = {416--430},
publisher = {Springer},
year = {2017}
}
@inproceedings{DBLP:conf/dasip/ReichenbachHHLB17,
author = {Marc Reichenbach and
Philipp Holzinger and
Konrad H{\"{a}}ublein and
Tobias Lieske and
Paul Blinzer and
Dietmar Fey},
title = {LibHSA: One step towards mastering the era of heterogeneous hardware
accelerators using FPGAs},
booktitle = {{DASIP}},
pages = {1--6},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/date/JacobRZHS17,
author = {Nisha Jacob and
Carsten Rolfes and
Andreas Zankl and
Johann Heyszl and
Georg Sigl},
title = {Compromising {FPGA} SoCs using malicious hardware blocks},
booktitle = {{DATE}},
pages = {1122--1127},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/dsd/PyrgasPPK17,
author = {Lampros Pyrgas and
Filippos Pirpilidis and
Aliki Panayiotarou and
Paris Kitsos},
title = {Thermal Sensor Based Hardware Trojan Detection in FPGAs},
booktitle = {{DSD}},
pages = {268--273},
publisher = {{IEEE} Computer Society},
year = {2017}
}
@inproceedings{DBLP:conf/fpga/BanerjeeELCKCI17,
author = {Subho S. Banerjee and
Mohamed El{-}Hadedy and
Jong Bin Lim and
Daniel Chen and
Zbigniew T. Kalbarczyk and
Deming Chen and
Ravishankar K. Iyer},
title = {{ASAP:} Accelerated Short Read Alignment on Programmable Hardware
(Abstract Only)},
booktitle = {{FPGA}},
pages = {293--294},
publisher = {{ACM}},
year = {2017}
}
@inproceedings{DBLP:conf/fpga/BobdaWKKN17,
author = {Christophe Bobda and
Taylor J. L. Whitaker and
Charles A. Kamhoua and
Kevin A. Kwiat and
Laurent Njilla},
title = {Automatic Generation of Hardware Sandboxes for Trojan Mitigation in
Systems on Chip (Abstract Only)},
booktitle = {{FPGA}},
pages = {289},
publisher = {{ACM}},
year = {2017}
}
@inproceedings{DBLP:conf/fpga/HuangMRRHC17,
author = {Sitao Huang and
Gowthami Jayashri Manikandan and
Anand Ramachandran and
Kyle Rupnow and
Wen{-}mei W. Hwu and
Deming Chen},
title = {Hardware Acceleration of the Pair-HMM Algorithm for {DNA} Variant
Calling},
booktitle = {{FPGA}},
pages = {275--284},
publisher = {{ACM}},
year = {2017}
}
@inproceedings{DBLP:conf/fpga/PezzottiINCVA17,
author = {Emanuele Pezzotti and
Alex Iacobucci and
Gregory Nash and
Umer I. Cheema and
Paolo Vinella and
Rashid Ansari},
title = {FPGA-based Hardware Accelerator for Image Reconstruction in Magnetic
Resonance Imaging (Abstract Only)},
booktitle = {{FPGA}},
pages = {293},
publisher = {{ACM}},
year = {2017}
}
@inproceedings{DBLP:conf/fpga/RamanathanFWC17,
author = {Nadesh Ramanathan and
Shane T. Fleming and
John Wickerson and
George A. Constantinides},
title = {Hardware Synthesis of Weakly Consistent {C} Concurrency},
booktitle = {{FPGA}},
pages = {169--178},
publisher = {{ACM}},
year = {2017}
}
@inproceedings{DBLP:conf/fpgaworld/WehbeMKIJ17,
author = {Taimour Wehbe and
Vincent John Mooney and
David C. Keezer and
Omer T. Inan and
Abdul Qadir Javaid},
title = {Use of Analog Signatures for Hardware Trojan Detection},
booktitle = {FPGAworld},
pages = {15--22},
publisher = {{ACM}},
year = {2017}
}
@inproceedings{DBLP:conf/fpl/BlockM17,
author = {Henry Block and
Tsutomu Maruyama},
title = {An {FPGA} hardware implementation approach for a phylogenetic tree
reconstruction algorithm with incremental tree optimization},
booktitle = {{FPL}},
pages = {1--8},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/fpl/Bolsens17,
author = {Ivo Bolsens},
title = {"All programmable FPGA, providing hardware efficiency to software
programmers"},
booktitle = {{FPL}},
pages = {1--3},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/fpl/CabaRG17,
author = {Juli{\'{a}}n Caba and
Fernando Rinc{\'{o}}n and
Julio Dondo Gazzano},
title = {Functional {\&} timing in-hardware verification of FPGA-based
designs using unit testing frameworks},
booktitle = {{FPL}},
pages = {1--2},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/fpl/LinZS17,
author = {Zhe Lin and
Wei Zhang and
Sharad Sinha},
title = {Decision tree based hardware power monitoring for run time dynamic
power management in {FPGA}},
booktitle = {{FPL}},
pages = {1--8},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/fpt/DHollanderCB17,
author = {Erik H. D'Hollander and
Bruno Chevalier and
Koen De Bosschere},
title = {Calling hardware procedures in a reconfigurable accelerator using
{RPC-FPGA}},
booktitle = {{FPT}},
pages = {271--274},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/glvlsi/Putnam17,
author = {Andrew Putnam},
title = {FPGAs in the Datacenter: Combining the Worlds of Hardware and Software
Development},
booktitle = {{ACM} Great Lakes Symposium on {VLSI}},
pages = {5},
publisher = {{ACM}},
year = {2017}
}
@inproceedings{DBLP:conf/heart/SakakibaraNM17,
author = {Yuma Sakakibara and
Kohei Nakamura and
Hiroki Matsutani},
title = {An {FPGA} {NIC} Based Hardware Caching for Blockchain},
booktitle = {{HEART}},
pages = {1:1--1:6},
publisher = {{ACM}},
year = {2017}
}
@inproceedings{DBLP:conf/iccd/SozzoBAS17,
author = {Emanuele Del Sozzo and
Riyadh Baghdadi and
Saman P. Amarasinghe and
Marco D. Santambrogio},
title = {A Common Backend for Hardware Acceleration on {FPGA}},
booktitle = {{ICCD}},
pages = {427--430},
publisher = {{IEEE} Computer Society},
year = {2017}
}
@inproceedings{DBLP:conf/icdsc/AbdaliHPDB17,
author = {El Mehdi Abdali and
Abderrahmane Walid Hanniche and
Maxime Pelcat and
Jean{-}Philippe Diguet and
Fran{\c{c}}ois Berry},
title = {Hardware Acceleration of the Tracking Learning Detection {(TLD)} Algorithm
on {FPGA}},
booktitle = {{ICDSC}},
pages = {180--185},
publisher = {{ACM}},
year = {2017}
}
@inproceedings{DBLP:conf/icm2/BousmarMHDD17,
author = {Khadija Bousmar and
Fabrice Monteiro and
Zineb Habbas and
Sofi{\`{e}}ne Dellagi and
Abbas Dandache},
title = {A pure hardware k-SAT solver architecture for {FPGA} based on generic
tree-search},
booktitle = {{ICM}},
pages = {1--5},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/iconip/YeohMT17,
author = {Yoeng Jye Yeoh and
Takashi Morie and
Hakaru Tamukoh},
title = {A Hardware-Oriented Dropout Algorithm for Efficient {FPGA} Implementation},
booktitle = {{ICONIP} {(6)}},
series = {Lecture Notes in Computer Science},
volume = {10639},
pages = {821--829},
publisher = {Springer},
year = {2017}
}
@inproceedings{DBLP:conf/icufn/SenouciRHB17,
author = {Benaoumeur Senouci and
H. Rouis and
Dong{-}Seog Han and
E. Bourennanea},
title = {A hardware skin-segmentation {IP} for vision based smart {ADAS} through
an {FPGA} prototyping},
booktitle = {{ICUFN}},
pages = {197--199},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/idaacs/KravetsSS17,
author = {Petro I. Kravets and
Volodymyr M. Shymkovych and
Volodymyr Samotyy},
title = {Method and technology of synthesis of neural network models of object
control with their hardware implementation on {FPGA}},
booktitle = {{IDAACS}},
pages = {947--951},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/iscas/ChangC17,
author = {Andre Xian Ming Chang and
Eugenio Culurciello},
title = {Hardware accelerators for recurrent neural networks on {FPGA}},
booktitle = {{ISCAS}},
pages = {1--4},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/iscas/EnemaliAA17,
author = {Godwin Enemali and
Adewale Adetomi and
Tughrul Arslan},
title = {A placement management circuit for efficient realtime hardware reuse
on FPGAs targeting reliable autonomous systems},
booktitle = {{ISCAS}},
pages = {1--4},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/ispa/ZhangWGLSXLZ17,
author = {Yiwei Zhang and
Chao Wang and
Lei Gong and
Yuntao Lu and
Fan Sun and
Chongchong Xu and
Xi Li and
Xuehai Zhou},
title = {Implementation and Optimization of the Accelerator Based on {FPGA}
Hardware for {LSTM} Network},
booktitle = {{ISPA/IUCC}},
pages = {614--621},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/mwscas/KamaleldinHMGHE17,
author = {Ahmed Kamaleldin and
Sherif Hosny and
Khaled Mohamed and
Mostafa Gamal and
Abdelrhman Hussien and
Eslam Elnader and
Ahmed Shalash and
Abdelfattah Mohammad Obeid and
Yehea Ismail and
Hassan Mostafa},
title = {A reconfigurable hardware platform implementation for software defined
radio using dynamic partial reconfiguration on Xilinx Zynq {FPGA}},
booktitle = {{MWSCAS}},
pages = {1540--1543},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/nds/VeltenWKKTSK17,
author = {J{\"{o}}rg Velten and
Daniel Wagner and
Lech Kolonko and
Kathrin Kalischewski and
Stephan Tilgner and
Tim Schwerdtfeger and
Anton Kummert},
title = {Examination of direct form vs. {WDF} realization of a 2-D quadrantal
fan filter in {FPGA} hardware},
booktitle = {nDS},
pages = {1--6},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/rcar/FanLLZJLC17,
author = {Kun Fan and
Congyi Lyu and
Yunhui Liu and
Weiguo Zhou and
Xin Jiang and
Peng Li and
Haoyao Chen},
title = {Hardware implementation of a virtual blind cane on {FPGA}},
booktitle = {{RCAR}},
pages = {344--348},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/reconfig/SilvaANSHF17,
author = {Lucas B. da Silva and
Danilo Dami{\~{a}}o Almeida and
Jos{\'{e}} Augusto Miranda Nacif and
Ismael Sanchez{-}Osorio and
Carlos A. Hernandez{-}Martinez and
Ricardo Ferreira},
title = {Exploring the dynamics of large-scale gene regulatory networks using
hardware acceleration on a heterogeneous {CPU-FPGA} platform},
booktitle = {ReConFig},
pages = {1--7},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/rtas/ShriramBJS17,
author = {S. Shriram and
Raghavendra Barkur and
Joshua Produkku and
B. Shanthibhushan},
title = {Work-in-Progress: {FPGA} Implementation of Synchronous Serial Interface
for Hardware in Loop Simulation},
booktitle = {{RTAS}},
pages = {133--136},
publisher = {{IEEE} Computer Society},
year = {2017}
}
@inproceedings{DBLP:conf/sac/MakniBNA17,
author = {Mariem Makni and
Mouna Baklouti and
Sma{\"{\i}}l Niar and
Mohamed Abid},
title = {Hardware resource estimation for heterogeneous FPGA-based SoCs},
booktitle = {{SAC}},
pages = {1481--1487},
publisher = {{ACM}},
year = {2017}
}
@inproceedings{DBLP:conf/sbcci/BortolonM17,
author = {Felipe T. Bortolon and
Fernando Gehm Moraes},
title = {Hardware and software infrastructure to implement many-core systems
in modern FPGAs},
booktitle = {{SBCCI}},
pages = {79--83},
publisher = {{ACM}},
year = {2017}
}
@incollection{DBLP:series/sci/Ontiveros-RoblesVCC17,
author = {Emanuel Ontiveros{-}Robles and
Jos{\'{e}} Gonz{\'{a}}lez V{\'{a}}zquez and
Juan R. Castro and
Oscar Castillo},
title = {A FPGA-Based Hardware Architecture Approach for Real-Time Fuzzy Edge
Detection},
booktitle = {Nature-Inspired Design of Hybrid Intelligent Systems},
series = {Studies in Computational Intelligence},
volume = {667},
pages = {519--540},
publisher = {Springer},
year = {2017}
}
@article{DBLP:journals/corr/BayerCEM17,
author = {F{\'{a}}bio M. Bayer and
Renato J. Cintra and
Amila Edirisuriya and
Arjuna Madanayake},
title = {A Digital Hardware Fast Algorithm and FPGA-based Prototype for a Novel
16-point Approximate {DCT} for Image Compression Applications},
journal = {CoRR},
volume = {abs/1702.01805},
year = {2017}
}
@article{DBLP:journals/corr/BreierH17,
author = {Jakub Breier and
Wei He},
title = {Multiple Fault Attack on {PRESENT} with a Hardware Trojan Implementation
in {FPGA}},
journal = {CoRR},
volume = {abs/1702.08208},
year = {2017}
}
@article{DBLP:journals/corr/abs-1711-01010,
author = {Amr Al{-}Anwar and
Mona A. Aboelnaga and
Yousra Alkabani and
M. Watheq El{-}Kharashi and
Hassan Bedour},
title = {Dynamic {FPGA} Detection and Protection of Hardware Trojan: {A} Comparative
Analysis},
journal = {CoRR},
volume = {abs/1711.01010},
year = {2017}
}
@article{DBLP:journals/corr/abs-1711-05860,
author = {Yufeng Hao},
title = {A General Neural Network Hardware Architecture on {FPGA}},
journal = {CoRR},
volume = {abs/1711.05860},
year = {2017}
}
@article{DBLP:journals/iacr/JacobHZRS17,
author = {Nisha Jacob and
Johann Heyszl and
Andreas Zankl and
Carsten Rolfes and
Georg Sigl},
title = {How to Break Secure Boot on {FPGA} SoCs through Malicious Hardware},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {625},
year = {2017}
}
@phdthesis{DBLP:phd/ch/George16,
author = {Nithin George},
title = {FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific
Languages},
school = {EPFL, Switzerland},
year = {2016}
}
@phdthesis{DBLP:phd/hal/Alhamwi16,
author = {Ali Alhamwi},
title = {Co-design Hardware/Software of Real time Vision System on {FPGA} for
Obstacle Detection. (Conception conjointe mat{\'{e}}riel/logiciel
de syst{\`{e}}me de Vision en temps r{\'{e}}el sur le {FPGA}
pour la d{\'{e}}tection d'Obstacle)},
school = {Paul Sabatier University, Toulouse, France},
year = {2016}
}
@phdthesis{DBLP:phd/hal/Bourge16,
author = {Alban Bourge},
title = {Changement de contexte mat{\'{e}}riel sur {FPGA} entre {\'{e}}quipements
reconfigurables et h{\'{e}}t{\'{e}}rog{\`{e}}nes dans un
environnement de calcul distribu{\'{e}}. (Hardware task context
switch on {FPGA} between heterogeneous reconfigurable devices in a
cloud-FPGA environment)},
school = {Grenoble Alpes University, France},
year = {2016}
}
@article{DBLP:journals/cee/Frances-Villora16,
author = {Jos{\'{e}} Vicente Franc{\'{e}}s{-}V{\'{\i}}llora and
Alfredo Rosado Mu{\~{n}}oz and
Jos{\'{e}} M. Mart{\'{\i}}nez{-}Villena and
Manuel Bataller{-}Mompe{\'{a}}n and
Juan{-}Francisco Guerrero{-}Mart{\'{\i}}nez and
Marek Wegrzyn},
title = {Hardware implementation of real-time Extreme Learning Machine in {FPGA:}
Analysis of precision, resource occupation and performance},
journal = {Comput. Electr. Eng.},
volume = {51},
pages = {139--156},
year = {2016}
}
@article{DBLP:journals/cee/ShahadiJW16,
author = {Haider Ismael Shahadi and
Razali Jidin and
Wong Hung Way},
title = {Concurrent hardware architecture for dual-mode audio steganography
processor-based {FPGA}},
journal = {Comput. Electr. Eng.},
volume = {49},
pages = {95--116},
year = {2016}
}
@article{DBLP:journals/cse/Arcas-AbellaA0M16,
author = {Oriol Arcas{-}Abella and
Adri{\`{a}} Armejach and
Timothy Hayes and
Gorker Alp Malazgirt and
Oscar Palomar and
Behzad Salami and
Nehir S{\"{o}}nmez},
title = {Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs,
and Memory},
journal = {Comput. Sci. Eng.},
volume = {18},
number = {1},
pages = {80--87},
year = {2016}
}
@article{DBLP:journals/ejes/MuttilloVFPFTF16,
author = {Vittoriano Muttillo and
Giacomo Valente and
Fabio Federici and
Luigi Pomante and
Marco Faccio and
Carlo Tieri and
Serenella Ferri},
title = {A design methodology for soft-core platforms on {FPGA} with {SMP}
Linux, OpenMP support, and distributed hardware profiling system},
journal = {{EURASIP} J. Embed. Syst.},
volume = {2016},
pages = {15},
year = {2016}
}
@article{DBLP:journals/evs/YahiTBM16,
author = {Amira Yahi and
Salah Toumi and
El{-}Bay Bourennane and
Kamel Messaoudi},
title = {A speed {FPGA} hardware accelerator based {FSBMA-VBSME} used in {H.264/AVC}},
journal = {Evol. Syst.},
volume = {7},
number = {4},
pages = {233--241},
year = {2016}
}
@article{DBLP:journals/ijcat/FredjAMA16,
author = {Amira Hadj Fredj and
Mariem Ben Abdallah and
Jihene Malek and
Ahmad Taher Azar},
title = {Fundus image denoising using {FPGA} hardware architecture},
journal = {Int. J. Comput. Appl. Technol.},
volume = {54},
number = {1},
pages = {1--13},
year = {2016}
}
@article{DBLP:journals/ijon/ClementeMASMZFV16,
author = {Juan Antonio Clemente and
Wassim Mansour and
Rafic Ayoubi and
Felipe Serrano and
Hortensia Mecha and
Haissam Ziade and
Wassim El Falou and
Raoul Velazco},
title = {Hardware implementation of a fault-tolerant Hopfield Neural Network
on FPGAs},
journal = {Neurocomputing},
volume = {171},
pages = {1606--1609},
year = {2016}
}
@article{DBLP:journals/jrtip/Kurdthongmee16,
author = {W. Kurdthongmee},
title = {A hardware centric algorithm for the best matching unit searching
stage of the SOM-based quantizer and its {FPGA} implementation},
journal = {J. Real Time Image Process.},
volume = {12},
number = {1},
pages = {71--80},
year = {2016}
}
@article{DBLP:journals/mam/CotretGF16,
author = {Pascal Cotret and
Guy Gogniat and
Martha Johanna Sep{\'{u}}lveda Fl{\'{o}}rez},
title = {Protection of heterogeneous architectures on FPGAs: An approach based
on hardware firewalls},
journal = {Microprocess. Microsystems},
volume = {42},
pages = {127--141},
year = {2016}
}
@article{DBLP:journals/mam/Milik16,
author = {Adam Milik},
title = {On hardware synthesis and implementation of {PLC} programs in FPGAs},
journal = {Microprocess. Microsystems},
volume = {44},
pages = {2--16},
year = {2016}
}
@article{DBLP:journals/tmscs/Mal-SarkarKNGKB16,
author = {Sanchita Mal{-}Sarkar and
Robert Karam and
Seetharam Narasimhan and
Anandaroop Ghosh and
Aswin Raghav Krishna and
Swarup Bhunia},
title = {Design and Validation for {FPGA} Trust under Hardware Trojan Attacks},
journal = {{IEEE} Trans. Multi Scale Comput. Syst.},
volume = {2},
number = {3},
pages = {186--198},
year = {2016}
}
@article{DBLP:journals/tpds/Ortega-Zamorano16,
author = {Francisco Ortega{-}Zamorano and
Marcelo A. Montemurro and
Sergio Alejandro Cannas and
Jos{\'{e}} M. Jerez and
Leonardo Franco},
title = {{FPGA} Hardware Acceleration of Monte Carlo Simulations for the Ising
Model},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {27},
number = {9},
pages = {2618--2627},
year = {2016}
}
@article{DBLP:journals/tpds/WangZLWZ16,
author = {Chao Wang and
Junneng Zhang and
Xi Li and
Aili Wang and
Xuehai Zhou},
title = {Hardware Implementation on {FPGA} for Task-Level Parallel Dataflow
Execution Engine},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {27},
number = {8},
pages = {2303--2315},
year = {2016}
}
@inproceedings{DBLP:conf/apccas/LeeOJLKL16,
author = {Sang Muk Lee and
Jung{-}Hwan Oh and
Ji Hoon Jang and
Seong Mo Lee and
Ji Kwang Kim and
Seung Eun Lee},
title = {Live demonstration: An {FPGA} based hardware compression accelerator
for Hadoop system},
booktitle = {{APCCAS}},
pages = {744--745},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/arc/KellySBWWR16,
author = {Colm Kelly and
Fahad Manzoor Siddiqui and
Burak Bardak and
Yun Wu and
Roger F. Woods and
Karen Rafferty},
title = {{FPGA} Soft-Core Processors, Compiler and Hardware Optimizations Validated
Using {HOG}},
booktitle = {{ARC}},
series = {Lecture Notes in Computer Science},
volume = {9625},
pages = {78--90},
publisher = {Springer},
year = {2016}
}
@inproceedings{DBLP:conf/asap/ChoiLBA16,
author = {Jongsok Choi and
Ruolong Lian and
Stephen Dean Brown and
Jason Helge Anderson},
title = {A unified software approach to specify pipeline and spatial parallelism
in {FPGA} hardware},
booktitle = {{ASAP}},
pages = {75--82},
publisher = {{IEEE} Computer Society},
year = {2016}
}
@inproceedings{DBLP:conf/aspdac/YuanLLY16,
author = {Zhe Yuan and
Yongpan Liu and
Hehe Li and
Huazhong Yang},
title = {{CP-FPGA:} Computation data-aware software/hardware co-design for
nonvolatile FPGAs based on checkpointing techniques},
booktitle = {{ASP-DAC}},
pages = {569--574},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/cd/BarbareschiCM16,
author = {Mario Barbareschi and
Alessandro Cilardo and
Antonino Mazzeo},
title = {Partial {FPGA} bitstream encryption enabling hardware {DRM} in mobile
environments},
booktitle = {Conf. Computing Frontiers},
pages = {443--448},
publisher = {{ACM}},
year = {2016}
}
@inproceedings{DBLP:conf/ches/JarvinenMAL16,
author = {Kimmo J{\"{a}}rvinen and
Andrea Miele and
Reza Azarderakhsh and
Patrick Longa},
title = {Four {\(\mathbb{Q}\)} on {FPGA:} New Hardware Speed Records for Elliptic
Curve Cryptography over Large Prime Characteristic Fields},
booktitle = {{CHES}},
series = {Lecture Notes in Computer Science},
volume = {9813},
pages = {517--537},
publisher = {Springer},
year = {2016}
}
@inproceedings{DBLP:conf/chinacom/TangZ0Z16,
author = {Shaoxian Tang and
Zhifeng Zhang and
Jun Wu and
Hui Zhu},
title = {FPGA-Based Turbo Decoder Hardware Accelerator in Cloud Radio Access
Network {(C-RAN)}},
booktitle = {ChinaCom {(1)}},
series = {Lecture Notes of the Institute for Computer Sciences, Social Informatics
and Telecommunications Engineering},
volume = {209},
pages = {211--220},
publisher = {Springer},
year = {2016}
}
@inproceedings{DBLP:conf/compsac/El-WafaSH16,
author = {Wael Abou El{-}Wafa and
Asmaa G. Seliem and
Hesham F. A. Hamed},
title = {Hardware Acceleration of Smith-Waterman Algorithm for Short Read {DNA}
Alignment Using {FPGA}},
booktitle = {{COMPSAC} Workshops},
pages = {604--605},
publisher = {{IEEE} Computer Society},
year = {2016}
}
@inproceedings{DBLP:conf/conielecomp/Lopez-RamirezLR16,
author = {Misael Lopez{-}Ramirez and
Luis Manuel Ledesma{-}Carrillo and
Carlos Rodriguez{-}Donate and
Eduardo Cabal{-}Yepez and
Homero Miranda{-}Vidales and
Arturo Garcia{-}Perez},
title = {FPGA-based hardware processing unit for time-frequency representation
of a signal through Wigner-Ville distribution},
booktitle = {{CONIELECOMP}},
pages = {162--167},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/dasip/KomorkiewiczTSK16,
author = {Mateusz Komorkiewicz and
Krzysztof Turek and
Pawel Skruch and
Tomasz Kryjak and
Marek Gorgon},
title = {FPGA-based Hardware-in-the-Loop environment using video injection
concept for camera-based systems in automotive applications},
booktitle = {{DASIP}},
pages = {183--190},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/date/Morales-Villanueva16,
author = {Aurelio Morales{-}Villanueva and
Rohit Kumar and
Ann Gordon{-}Ross},
title = {Configuration prefetching and reuse for preemptive hardware multitasking
on partially reconfigurable FPGAs},
booktitle = {{DATE}},
pages = {1505--1508},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/dsd/KitsosSV16,
author = {Paris Kitsos and
Kyriakos Stefanidis and
Artemios G. Voyiatzis},
title = {TERO-Based Detection of Hardware Trojans on {FPGA} Implementation
of the {AES} Algorithm},
booktitle = {{DSD}},
pages = {678--681},
publisher = {{IEEE} Computer Society},
year = {2016}
}
@inproceedings{DBLP:conf/dsd/Lara-NinoMD16,
author = {Carlos Andres Lara{-}Nino and
Miguel Morales{-}Sandoval and
Arturo Diaz{-}Perez},
title = {Novel FPGA-Based Low-Cost Hardware Architecture for the {PRESENT}
Block Cipher},
booktitle = {{DSD}},
pages = {646--650},
publisher = {{IEEE} Computer Society},
year = {2016}
}
@inproceedings{DBLP:conf/dtis/Salvador16,
author = {Rub{\'{e}}n Salvador},
title = {Evolvable Hardware in FPGAs: Embedded tutorial},
booktitle = {{DTIS}},
pages = {1--6},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/fpga/LiNL16,
author = {Bingzhe Li and
M. Hassan Najafi and
David J. Lilja},
title = {Using Stochastic Computing to Reduce the Hardware Requirements for
a Restricted Boltzmann Machine Classifier},
booktitle = {{FPGA}},
pages = {36--41},
publisher = {{ACM}},
year = {2016}
}
@inproceedings{DBLP:conf/fpga/ZhangAC16,
author = {Sizhuo Zhang and
Hari Angepat and
Derek Chiou},
title = {HGum: Messaging Framework for Hardware Accelerators (Abstact Only)},
booktitle = {{FPGA}},
pages = {283},
publisher = {{ACM}},
year = {2016}
}
@inproceedings{DBLP:conf/fpt/KalmsEJ16,
author = {Lester Kalms and
Ahmed Elhossini and
Ben H. H. Juurlink},
title = {{FPGA} based hardware accelerator for {KAZE} feature extraction algorithm},
booktitle = {{FPT}},
pages = {281--284},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/fpt/VeerannaS16,
author = {Nandeesha Veeranna and
Benjamin Carri{\'{o}}n Sch{\"{a}}fer},
title = {Hardware Trojan avoidance and detection for dynamically re-configurable
FPGAs},
booktitle = {{FPT}},
pages = {193--196},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/hotchips/GuoSQYHWY16,
author = {Kaiyuan Guo and
Lingzhi Sui and
Jiantao Qiu and
Song Yao and
Song Han and
Yu Wang and
Huazhong Yang},
title = {From model to {FPGA:} Software-hardware co-design for efficient neural
network acceleration},
booktitle = {Hot Chips Symposium},
pages = {1--27},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/huc/AhmadLC16,
author = {Abdul Mutaal Ahmad and
Paul Lukowicz and
Jingyuan Cheng},
title = {{FPGA} based hardware acceleration of sensor matrix},
booktitle = {UbiComp Adjunct},
pages = {793--802},
publisher = {{ACM}},
year = {2016}
}
@inproceedings{DBLP:conf/ic-nc/HaradaMNI16,
author = {Naoaki Harada and
Naoyuki Matsumoto and
Koji Nakano and
Yasuaki Ito},
title = {A Hardware Sorter for Almost Sorted Sequences, with {FPGA} Implementations},
booktitle = {{CANDAR}},
pages = {565--571},
publisher = {{IEEE} Computer Society},
year = {2016}
}
@inproceedings{DBLP:conf/icacci/ChhabraJS16,
author = {Surbhi Chhabra and
Himanshu Jain and
Sandeep Saini},
title = {{FPGA} based hardware implementation of automatic vehicle license
plate detection system},
booktitle = {{ICACCI}},
pages = {1181--1187},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/icaisc/PrzybylE16,
author = {Andrzej Przybyl and
Meng Joo Er},
title = {The Method of Hardware Implementation of Fuzzy Systems on {FPGA}},
booktitle = {{ICAISC} {(1)}},
series = {Lecture Notes in Computer Science},
volume = {9692},
pages = {284--298},
publisher = {Springer},
year = {2016}
}
@inproceedings{DBLP:conf/iccd/MomeniTSK16,
author = {Amir Momeni and
Hamed Tabkhi and
Gunar Schirner and
David R. Kaeli},
title = {Hardware thread reordering to boost OpenCL throughput on FPGAs},
booktitle = {{ICCD}},
pages = {257--264},
publisher = {{IEEE} Computer Society},
year = {2016}
}
@inproceedings{DBLP:conf/iccp2/VanceaN16,
author = {Cristian{-}Cosmin Vancea and
Sergiu Nedevschi},
title = {FPGA-based stereo vision hardware for generating dense disparity maps},
booktitle = {{ICCP}},
pages = {225--232},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/icdsc/BrenotPF16,
author = {Fran{\c{c}}ois Brenot and
Jonathan Piat and
Philippe Fillatreau},
title = {{FPGA} based hardware acceleration of a {BRIEF} correlator module
for a monocular {SLAM} application},
booktitle = {{ICDSC}},
pages = {184--189},
publisher = {{ACM}},
year = {2016}
}
@inproceedings{DBLP:conf/icm2/GamalEF16,
author = {Mohammed Gamal and
Mohamed El{-}Banna and
Mohammed M. Farag},
title = {Hardware implementation of an {LQR} controller of a drum-type boiler
turbine on {FPGA}},
booktitle = {{ICM}},
pages = {137--140},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/icuimc/JoLJ16,
author = {Byeong{-}Oh Jo and
Sang{-}Jun Lee and
Jae Wook Jeon},
title = {The Development of Hardware Architecture for Real-time Chain Code
based on {FPGA}},
booktitle = {{IMCOM}},
pages = {24:1--24:6},
publisher = {{ACM}},
year = {2016}
}
@inproceedings{DBLP:conf/idt/FarhatFSB16,
author = {Wajdi Farhat and
Hassene Faiedh and
Chokri Souani and
Kamel Besbes},
title = {Real-time hardware/software co-design of a traffic sign recognition
system using Zynq {FPGA}},
booktitle = {{IDT}},
pages = {302--307},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/indocrypt/KozielAK16,
author = {Brian Koziel and
Reza Azarderakhsh and
Mehran Mozaffari Kermani},
title = {Fast Hardware Architectures for Supersingular Isogeny Diffie-Hellman
Key Exchange on {FPGA}},
booktitle = {{INDOCRYPT}},
series = {Lecture Notes in Computer Science},
volume = {10095},
pages = {191--206},
year = {2016}
}
@inproceedings{DBLP:conf/ipas2/AkkadEA16,
author = {Ghattas Akkad and
Moustapha El Hassan and
Rafic Ayoubi},
title = {{FPGA} hardware architecture for stereoscopic image compression based
on block matching, watermarking and hamming code},
booktitle = {{IPAS}},
pages = {1--5},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/ipps/KourfaliS16,
author = {Alexandra Kourfali and
Dirk Stroobandt},
title = {Efficient Hardware Debugging Using Parameterized {FPGA} Reconfiguration},
booktitle = {{IPDPS} Workshops},
pages = {277--282},
publisher = {{IEEE} Computer Society},
year = {2016}
}
@inproceedings{DBLP:conf/isicir/LomuscioCNR16,
author = {Andrea Lomuscio and
Gian Carlo Cardarilli and
Alberto Nannarelli and
Marco Re},
title = {A hardware framework for on-chip {FPGA} acceleration},
booktitle = {{ISIC}},
pages = {1--4},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/isie/MorelloBTCRRJLI16,
author = {Rocco Morello and
Federico Baronti and
X. Tian and
Thomas Chau and
Roberto Di Rienzo and
Roberto Roncella and
B. P. Jeppesen and
W. H. Lin and
T. Ikushima and
Roberto Saletti},
title = {Hardware-in-the-loop simulation of FPGA-based state estimators for
electric vehicle batteries},
booktitle = {{ISIE}},
pages = {280--285},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/isvlsi/YousufG16,
author = {Shaon Yousuf and
Ann Gordon{-}Ross},
title = {An Automated Hardware/Software Co-Design Flow for Partially Reconfigurable
FPGAs},
booktitle = {{ISVLSI}},
pages = {30--35},
publisher = {{IEEE} Computer Society},
year = {2016}
}
@inproceedings{DBLP:conf/mixdes/PetrutAB16,
author = {Patricia Carla Petrut and
Alexandru Amaricai and
Oana Boncalo},
title = {Configurable {FPGA} architecture for hardware-software merge sorting},
booktitle = {{MIXDES}},
pages = {179--182},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/rcar/PengLLLZF16,
author = {Jianqing Peng and
Yunhui Liu and
Congyi Lyu and
Yunhui Li and
Weiguo Zhou and
Kun Fan},
title = {FPGA-based parallel hardware architecture for {SIFT} algorithm},
booktitle = {{RCAR}},
pages = {277--282},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/sas2/EiderKP16,
author = {Markus Eider and
Stefan Kunze and
Rainer Poeschl},
title = {{FPGA} based emulation of multiple 1-wire sensors for hardware in
the loop tests},
booktitle = {{SAS}},
pages = {1--6},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/sbac-pad/KimJG16,
author = {Youngsoo Kim and
Shrikant Jadhav and
Clay S. Gloster Jr.},
title = {Dataflow to Hardware Synthesis Framework on FPGAs},
booktitle = {{SBAC-PAD} (Workshops)},
pages = {91--96},
publisher = {{IEEE} Computer Society},
year = {2016}
}
@inproceedings{DBLP:conf/sies/HarbVPG16,
author = {Naim Harb and
Carlos Valderrama and
Esteban Pelaez and
Alexandre Girardi},
title = {{FPGA} hardware in the loop system for {ERTMS-ETCS} train equipment
testing},
booktitle = {{SIES}},
pages = {55--62},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/ssci/JohnsonHMTTLHMK16,
author = {Anju P. Johnson and
David M. Halliday and
Alan G. Millard and
Andy M. Tyrrell and
Jon Timmis and
Junxiu Liu and
Jim Harkin and
Liam McDaid and
Shvan Karim},
title = {An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network},
booktitle = {{SSCI}},
pages = {1--8},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/trustcom/LiCLSCL16,
author = {Xiaochao Li and
Chunhui Cao and
Pengtao Li and
Shuli Shen and
Yihui Chen and
Lin Li},
title = {Energy-Efficient Hardware Implementation of {LUKS} {PBKDF2} with {AES}
on {FPGA}},
booktitle = {Trustcom/BigDataSE/ISPA},
pages = {402--409},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/vlsi/LiHC16a,
author = {Yanzhe Li and
Kai Huang and
Luc Claesen},
title = {A Novel Hardware-Oriented Stereo Matching Algorithm and Its Architecture
Design in {FPGA}},
booktitle = {VLSI-SoC (Selected Papers)},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {508},
pages = {213--232},
publisher = {Springer},
year = {2016}
}
@article{DBLP:journals/corr/CotretGF16,
author = {Pascal Cotret and
Guy Gogniat and
Martha Johanna Sep{\'{u}}lveda Fl{\'{o}}rez},
title = {Protection of heterogeneous architectures on FPGAs: An approach based
on hardware firewalls},
journal = {CoRR},
volume = {abs/1602.05106},
year = {2016}
}
@article{DBLP:journals/corr/Ortega-Zamorano16,
author = {Francisco Ortega{-}Zamorano and
Marcelo A. Montemurro and
Sergio A. Cannas and
Jos{\'{e}} M. Jerez and
Leonardo Franco},
title = {{FPGA} Hardware Acceleration of Monte Carlo Simulations for the Ising
Model},
journal = {CoRR},
volume = {abs/1602.03016},
year = {2016}
}
@article{DBLP:journals/iacr/JarvinenMAL16,
author = {Kimmo J{\"{a}}rvinen and
Andrea Miele and
Reza Azarderakhsh and
Patrick Longa},
title = {FourQ on {FPGA:} New Hardware Speed Records for Elliptic Curve Cryptography
over Large Prime Characteristic Fields},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {569},
year = {2016}
}
@article{DBLP:journals/iacr/KozielAK16,
author = {Brian Koziel and
Reza Azarderakhsh and
Mehran Mozaffari Kermani},
title = {Fast Hardware Architectures for Supersingular Isogeny Diffie-Hellman
Key Exchange on {FPGA}},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {1044},
year = {2016}
}
@phdthesis{DBLP:phd/hal/Huriaux15,
author = {Christophe Huriaux},
title = {Enhanced {FPGA} Architecture and {CAD} Flow for Efficient Runtime
Hardware Reconfiguration. (Architecture {FPGA} ame'liore'e et flot
de conception pour une reconfiguration mate'rielle en ligne efficace)},
school = {University of Rennes 1, France},
year = {2015}
}
@phdthesis{DBLP:phd/ndltd/Oliveira15e,
author = {Cristiano Bacelar de Oliveira},
title = {{LALP+:} a framework for developing FPGA-based hardware accelerators
{(LALP+:} um framework para o desenvolvimento de aceleradores de hardware
em FPGAs)},
school = {University of S{\~{a}}o Paulo, Brazil},
year = {2015}
}
@article{DBLP:journals/esl/KhaleghiAAS15,
author = {Behnam Khaleghi and
Ali Ahari and
Hossein Asadi and
Siavash Bayat Sarmadi},
title = {FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion
Using Dummy Logic},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {7},
number = {2},
pages = {46--50},
year = {2015}
}
@article{DBLP:journals/ieiceee/GuoDLW15,
author = {Song Guo and
Yong Dou and
Yuanwu Lei and
Guiming Wu},
title = {A deeply-pipelined FPGA-based SpMV accelerator with a hardware-friendly
storage scheme},
journal = {{IEICE} Electron. Express},
volume = {12},
number = {11},
pages = {20150161},
year = {2015}
}
@article{DBLP:journals/ieicet/YazawaYTDYYF15,
author = {Yoshifumi Yazawa and
Tsutomu Yoshimi and
Teruyasu Tsuzuki and
Tomomi Dohi and
Yuji Yamauchi and
Takayoshi Yamashita and
Hironobu Fujiyoshi},
title = {{FPGA} Hardware with Target-Reconfigurable Object Detector},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {98-D},
number = {9},
pages = {1637--1645},
year = {2015}
}
@article{DBLP:journals/ijcat/HamdaouiSM15,
author = {Fay{\c{c}}al Hamdaoui and
Anis Sakly and
Abdellatif Mtibaa},
title = {{FPGA} hardware architecture of correlation-based {MRI} images classification
using {XSG}},
journal = {Int. J. Comput. Appl. Technol.},
volume = {52},
number = {1},
pages = {77--85},
year = {2015}
}
@article{DBLP:journals/ijguc/Zhu15,
author = {Shi{-}hai Zhu},
title = {Hardware implementation based on {FPGA} of semaphore management in
{\(\mu\)}C/OS-II real-time operating system},
journal = {Int. J. Grid Util. Comput.},
volume = {6},
number = {3/4},
pages = {192--199},
year = {2015}
}
@article{DBLP:journals/ijon/TanR15,
author = {Yong Tat Tan and
Bakhtiar Affendi Rosdi},
title = {FPGA-based hardware accelerator for the prediction of protein secondary
class via fuzzy K-nearest neighbors with Lempel-Ziv complexity based
distance measure},
journal = {Neurocomputing},
volume = {148},
pages = {409--419},
year = {2015}
}
@article{DBLP:journals/ijpp/SukhwaniTMDBAD15,
author = {Bharat Sukhwani and
Mathew Thoennes and
Hong Min and
Parijat Dube and
Bernard Brezzo and
Sameh W. Asaad and
Donna Dillenberger},
title = {A Hardware/Software Approach for Database Query Acceleration with
FPGAs},
journal = {Int. J. Parallel Program.},
volume = {43},
number = {6},
pages = {1129--1159},
year = {2015}
}
@article{DBLP:journals/jce/VliegenMKSV15,
author = {Jo Vliegen and
Nele Mentens and
Dirk Koch and
Dries Schellekens and
Ingrid Verbauwhede},
title = {Practical feasibility evaluation and improvement of a pay-per-use
licensing scheme for hardware {IP} cores in Xilinx FPGAs},
journal = {J. Cryptogr. Eng.},
volume = {5},
number = {2},
pages = {113--122},
year = {2015}
}
@article{DBLP:journals/jcsci/JuniorOJ15,
author = {S{\'{e}}rgio Bimbi Junior and
Vitor Chaves de Oliveira and
Gunnar Bedicks Junior},
title = {Software Defined Radio Implementation of a {QPSK} Modulator/Demodulator
in an Extensive Hardware Platform Based on FPGAs Xilinx {ZYNQ}},
journal = {J. Comput. Sci.},
volume = {11},
number = {4},
pages = {598--611},
year = {2015}
}
@article{DBLP:journals/jicce/ChooCM15,
author = {Chang Choo and
Young{-}Uk Chang and
Il{-}Young Moon},
title = {FPGA-Based Hardware Accelerator for Feature Extraction in Automatic
Speech Recognition},
journal = {J. Inform. and Commun. Convergence Engineering},
volume = {13},
number = {3},
year = {2015}
}
@article{DBLP:journals/jrtip/Rodriguez-Gomez15,
author = {Rafael Rodr{\'{\i}}guez{-}G{\'{o}}mez and
Enrique J. Fernandez{-}Sanchez and
Javier D{\'{\i}}az and
Eduardo Ros Vidal},
title = {Codebook hardware implementation on {FPGA} for background subtraction},
journal = {J. Real Time Image Process.},
volume = {10},
number = {1},
pages = {43--57},
year = {2015}
}
@article{DBLP:journals/mam/AysuS15,
author = {Aydin Aysu and
Patrick Schaumont},
title = {Hardware/software co-design of physical unclonable function based
authentications on FPGAs},
journal = {Microprocess. Microsystems},
volume = {39},
number = {7},
pages = {589--597},
year = {2015}
}
@article{DBLP:journals/mam/DammakBBNA15,
author = {Bouthaina Dammak and
Mouna Baklouti and
Rachid Benmansour and
Sma{\"{\i}}l Niar and
Mohamed Abid},
title = {Hardware resource utilization optimization in FPGA-based Heterogeneous
MPSoC architectures},
journal = {Microprocess. Microsystems},
volume = {39},
number = {8},
pages = {1108--1118},
year = {2015}
}
@article{DBLP:journals/tc/TangB15,
author = {Yi Tang and
Neil W. Bergmann},
title = {A Hardware Scheduler Based on Task Queues for FPGA-Based Embedded
Real-Time Systems},
journal = {{IEEE} Trans. Computers},
volume = {64},
number = {5},
pages = {1254--1267},
year = {2015}
}
@article{DBLP:journals/tcbb/FernandezVLN15,
author = {Edward B. Fernandez and
Jason R. Villarreal and
Stefano Lonardi and
Walid A. Najjar},
title = {{FHAST:} FPGA-Based Acceleration of Bowtie in Hardware},
journal = {{IEEE} {ACM} Trans. Comput. Biol. Bioinform.},
volume = {12},
number = {5},
pages = {973--981},
year = {2015}
}
@article{DBLP:journals/tci/QasaimehSS15,
author = {Murad Qasaimeh and
Assim Sagahyroon and
Tamer Shanableh},
title = {FPGA-Based Parallel Hardware Architecture for Real-Time Image Classification},
journal = {{IEEE} Trans. Computational Imaging},
volume = {1},
number = {1},
pages = {56--70},
year = {2015}
}
@article{DBLP:journals/tie/JimenezLUBND15,
author = {{\'{O}}scar Jim{\'{e}}nez and
Oscar Luc{\'{\i}}a and
Isidoro Urriza and
Luis Angel Barragan and
Denis Navarro and
Venkata Dinavahi},
title = {Implementation of an FPGA-Based Online Hardware-in-the-Loop Emulator
Using High-Level Synthesis Tools for Resonant Power Converters Applied
to Induction Heating Appliances},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {62},
number = {4},
pages = {2206--2214},
year = {2015}
}
@article{DBLP:journals/vlsisp/0001DIM15,
author = {Michael R. Smith and
Dongcheng Deng and
Syed Islam and
James Miller},
title = {Enhancing Hardware Assisted Test Insertion Capabilities on Embedded
Processors using an FPGA-based Agile Test Support Co-processor},
journal = {J. Signal Process. Syst.},
volume = {79},
number = {3},
pages = {285--298},
year = {2015}
}
@inproceedings{DBLP:conf/IEEEssd/AnaneA15a,
author = {Mohamed Anane and
Nadjia Anane},
title = {{SHA-2} hardware core for virtex-5 {FPGA}},
booktitle = {{SSD}},
pages = {1--5},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/IEEEssd/KahriMBM15,
author = {Fatma Kahri and
Hassen Mestiri and
Belgacem Bouallegue and
Mohsen Machhout},
title = {Efficient {FPGA} hardware implementation of secure hash function SHA-256/Blake-256},
booktitle = {{SSD}},
pages = {1--5},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/acsac/LiDP15,
author = {Letitia W. Li and
Guillaume Duc and
Renaud Pacalet},
title = {Hardware-assisted Memory Tracing on New SoCs Embedding {FPGA} Fabrics},
booktitle = {{ACSAC}},
pages = {461--470},
publisher = {{ACM}},
year = {2015}
}
@inproceedings{DBLP:conf/arc/CharitopoulosKP15,
author = {George Charitopoulos and
Iosif Koidis and
Kyprianos Papadimitriou and
Dionisios N. Pnevmatikatos},
title = {Hardware Task Scheduling for Partially Reconfigurable FPGAs},
booktitle = {{ARC}},
series = {Lecture Notes in Computer Science},
volume = {9040},
pages = {487--498},
publisher = {Springer},
year = {2015}
}
@inproceedings{DBLP:conf/asicon/ZhangCW15,
author = {Yangjie Zhang and
Wei Cao and
Lingli Wang},
title = {Implementation of high performance hardware architecture of face recognition
algorithm based on local binary pattern on {FPGA}},
booktitle = {{ASICON}},
pages = {1--4},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/cis/QuWZ15,
author = {Kaige Qu and
Liji Wu and
Xiangmin Zhang},
title = {A Novel Detection Algorithm for Ring Oscillator Network Based Hardware
Trojan Detection with Tactful {FPGA} Implementation},
booktitle = {{CIS}},
pages = {299--302},
publisher = {{IEEE} Computer Society},
year = {2015}
}
@inproceedings{DBLP:conf/cisis-spain/EpeldeMLM15,
author = {Gorka Epelde and
Andoni Mujika and
Peter Leskovsk{\'{y}} and
Alessandro De Mauro},
title = {Public Access Architecture Design of an FPGA-Hardware-Based Nervous
System Emulation Remote Lab},
booktitle = {{CISIS-ICEUTE}},
series = {Advances in Intelligent Systems and Computing},
volume = {369},
pages = {559--569},
publisher = {Springer},
year = {2015}
}
@inproceedings{DBLP:conf/date/KainthKNVT15,
author = {Meha Kainth and
Lekshmi Krishnan and
Chaitra Narayana and
Sandesh Gubbi Virupaksha and
Russell Tessier},
title = {Hardware-assisted code obfuscation for {FPGA} soft microprocessors},
booktitle = {{DATE}},
pages = {127--132},
publisher = {{ACM}},
year = {2015}
}
@inproceedings{DBLP:conf/etfa/GrimmJNH15,
author = {Tom{\'{a}}s Grimm and
Benedikt Jan{\ss}en and
Osvaldo Navarro and
Michael H{\"{u}}bner},
title = {The value of FPGAs as reconfigurable hardware enabling Cyber-Physical
Systems},
booktitle = {{ETFA}},
pages = {1--8},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/fccm/SalamiAS15,
author = {Behzad Salami and
Oriol Arcas{-}Abella and
Nehir S{\"{o}}nmez},
title = {{HATCH:} Hash Table Caching in Hardware for Efficient Relational Join
on {FPGA}},
booktitle = {{FCCM}},
pages = {163},
publisher = {{IEEE} Computer Society},
year = {2015}
}
@inproceedings{DBLP:conf/fpga/BymaTXBLC15,
author = {Stuart Byma and
Naif Tarafdar and
Talia Xu and
Hadi Bannazadeh and
Alberto Leon{-}Garcia and
Paul Chow},
title = {Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware},
booktitle = {{FPGA}},
pages = {94--97},
publisher = {{ACM}},
year = {2015}
}
@inproceedings{DBLP:conf/fpga/ChackoSPKD15,
author = {James Chacko and
Cem Sahin and
Douglas Pfiel and
Nagarajan Kandasamy and
Kapil R. Dandekar},
title = {Rapid Prototyping of Wireless Physical Layer Modules Using Flexible
Software/Hardware Design Flow},
booktitle = {{FPGA}},
pages = {32--35},
publisher = {{ACM}},
year = {2015}
}
@inproceedings{DBLP:conf/fpga/FlemingTCG15,
author = {Shane T. Fleming and
David B. Thomas and
George A. Constantinides and
Dan R. Ghica},
title = {System-level Linking of Synthesised Hardware and Compiled Software
Using a Higher-order Type System},
booktitle = {{FPGA}},
pages = {214--217},
publisher = {{ACM}},
year = {2015}
}
@inproceedings{DBLP:conf/fpga/GarciaCORB15,
author = {Gerardo Soria Garc{\'{\i}}a and
Adrian Pedroza de{-}la{-}Cr{\'{u}}z and
Susana Ortega{-}Cisneros and
Juan Jos{\'{e}} Raygoza{-}Panduro and
Eduardo Bayro{-}Corrochano},
title = {A Hardware Implementation of a Unit for Geometric Algebra Operations
With Parallel Memory Arrays (Abstract Only)},
booktitle = {{FPGA}},
pages = {272},
publisher = {{ACM}},
year = {2015}
}
@inproceedings{DBLP:conf/fpga/JaicS15,
author = {Keerthan Jaic and
Melissa C. Smith},
title = {Enhancing Hardware Design Flows with MyHDL},
booktitle = {{FPGA}},
pages = {28--31},
publisher = {{ACM}},
year = {2015}
}
@inproceedings{DBLP:conf/fpga/KingHA15,
author = {Myron King and
Jamey Hicks and
John Ankcorn},
title = {Software-Driven Hardware Development},
booktitle = {{FPGA}},
pages = {13--22},
publisher = {{ACM}},
year = {2015}
}
@inproceedings{DBLP:conf/fpga/PapadopoulosTKT15,
author = {Martinianos Papadopoulos and
Christos Ttofis and
Christos Kyrkou and
Theocharis Theocharides},
title = {Real-Time Obstacle Avoidance for Mobile Robots via Stereoscopic Vision
Using Reconfigurable Hardware (Abstract Only)},
booktitle = {{FPGA}},
pages = {262},
publisher = {{ACM}},
year = {2015}
}
@inproceedings{DBLP:conf/fpga/TakasuTAK15,
author = {Ryota Takasu and
Yoichi Tomioka and
Takashi Aoki and
Hitoshi Kitazawa},
title = {An {FPGA} Implementation of Multi-stream Tracking Hardware using 2D
{SIMD} Array (Abstract Only)},
booktitle = {{FPGA}},
pages = {268},
publisher = {{ACM}},
year = {2015}
}
@inproceedings{DBLP:conf/fpgaworld/MalazgirtSYCU15,
author = {Gorker Alp Malazgirt and
Nehir S{\"{o}}nmez and
Arda Yurdakul and
Adri{\'{a}}n Cristal and
Osman S. Unsal},
title = {High Level Synthesis Based Hardware Accelerator Design for Processing
{SQL} Queries},
booktitle = {FPGAworld},
pages = {27--32},
publisher = {{ACM}},
year = {2015}
}
@inproceedings{DBLP:conf/fpl/LiangSWZ15,
author = {Hao Liang and
Sharad Sinha and
Rakesh Warrier and
Wei Zhang},
title = {Static hardware task placement on multi-context {FPGA} using hybrid
genetic algorithm},
booktitle = {{FPL}},
pages = {1--8},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/fpt/ChoiBA15,
author = {Jongsok Choi and
Stephen Dean Brown and
Jason Helge Anderson},
title = {Resource and memory management techniques for the high-level synthesis
of software threads into parallel {FPGA} hardware},
booktitle = {{FPT}},
pages = {152--159},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/host/BloomNSNL15,
author = {Gedare Bloom and
Bhagirath Narahari and
Rahul Simha and
Ali Namazi and
Renato Levy},
title = {{FPGA} SoC architecture and runtime to prevent hardware Trojans from
leaking secrets},
booktitle = {{HOST}},
pages = {48--51},
publisher = {{IEEE} Computer Society},
year = {2015}
}
@inproceedings{DBLP:conf/icce-tw/MuzammilASK15,
author = {Muhammad Muzammil and
I. Ali and
M. Sharif and
K. A. Khalil},
title = {An efficient {FPGA} architecture for hardware realization of hexagonal
based motion estimation algorithm},
booktitle = {{ICCE-TW}},
pages = {422--423},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/iccsce/AyatHB15,
author = {Sayed Omid Ayat and
Mohamed Khalil Hani and
Rabia Bakhteri},
title = {OpenCL-based hardware-software co-design methodology for image processing
implementation on heterogeneous {FPGA} platform},
booktitle = {{ICCSCE}},
pages = {36--41},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/icit2/Calvo-GallegoSJ15,
author = {Elisa Calvo{-}Gallego and
Santiago S{\'{a}}nchez{-}Solano and
Piedad Brox Jim{\'{e}}nez},
title = {Hardware implementation of a background substraction algorithm in
FPGA-based platforms},
booktitle = {{ICIT}},
pages = {1688--1693},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/icsenst/NakayamaSYI15,
author = {Masashi Nakayama and
Naoki Shigekawa and
Takashi Yokouchi and
Shunsuke Ishimitsu},
title = {Frame-by-frame speech recognition as hardware decoding on {FPGA} devices},
booktitle = {{ICST}},
pages = {785--788},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/ipps/Morales-Villanueva15,
author = {Aurelio Morales{-}Villanueva and
Ann Gordon{-}Ross},
title = {Partial Region and Bitstream Cost Models for Hardware Multitasking
on Partially Reconfigurable FPGAs},
booktitle = {{IPDPS} Workshops},
pages = {90--96},
publisher = {{IEEE} Computer Society},
year = {2015}
}
@inproceedings{DBLP:conf/iscas/BenacerHK15a,
author = {Imad Benacer and
Aicha Hamissi and
Abdelhakim Khouas},
title = {Hardware design and {FPGA} implementation for road plane extraction
based on V-disparity approach},
booktitle = {{ISCAS}},
pages = {2053--2056},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/ispass/HoGNNMAFCS15,
author = {Chen{-}Han Ho and
Venkatraman Govindaraju and
Tony Nowatzki and
Ranjini Nagaraju and
Zachary Marzec and
Preeti Agarwal and
Chris Frericks and
Ryan Cofell and
Karthikeyan Sankaralingam},
title = {Performance evaluation of a DySER {FPGA} prototype system spanning
the compiler, microarchitecture, and hardware implementation},
booktitle = {{ISPASS}},
pages = {203--214},
publisher = {{IEEE} Computer Society},
year = {2015}
}
@inproceedings{DBLP:conf/ispdc/MatsumotoNI15,
author = {Naoyuki Matsumoto and
Koji Nakano and
Yasuaki Ito},
title = {Optimal Parallel Hardware K-Sorter and Top K-Sorter, with {FPGA} Implementations},
booktitle = {{ISPDC}},
pages = {138--147},
publisher = {{IEEE} Computer Society},
year = {2015}
}
@inproceedings{DBLP:conf/isspit/CardarilliCNPR15,
author = {Gian Carlo Cardarilli and
Leonardo Di Carlo and
Alberto Nannarelli and
Federico Maria Pandolfi and
Marco Re},
title = {A framework for dynamically-loaded hardware library {(HLL)} in {FPGA}
acceleration},
booktitle = {{ISSPIT}},
pages = {291--296},
publisher = {{IEEE} Computer Society},
year = {2015}
}
@inproceedings{DBLP:conf/iwst/SangLFLB15,
author = {Le Xuan Sang and
Lo{\"{\i}}c Lagadec and
Luc Fabresse and
Jannik Laval and
Noury Bouraqadi},
title = {A Meta Model Supporting Both Hardware and Smalltalk-Based Execution
of Fpga Circuits},
booktitle = {{IWST}},
pages = {6:1--6:14},
publisher = {{ACM}},
year = {2015}
}
@inproceedings{DBLP:conf/lascas/SanchezPML15,
author = {Luis Sanchez and
Giancarlo Patino and
V{\'{\i}}ctor Murray and
James Lyke},
title = {Hardware implementation of a FPGA-based universal link for {LVDS}
communications},
booktitle = {{LASCAS}},
pages = {1--4},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/mixdes/MatogaKGZP15,
author = {Lukasz Matoga and
Arkadiusz Koczor and
Michal Golek and
Pawel Zadek and
Piotr Penkala},
title = {Modular FPGA-based hardware platform for emulation},
booktitle = {{MIXDES}},
pages = {402--408},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/mmar/MohammediKMH15,
author = {Amine Mohammedi and
Nadir Kabache and
Samir Moulahoum and
Hamza Houassine},
title = {{FPGA} hardware in the loop validation of direct torque control for
induction motor},
booktitle = {{MMAR}},
pages = {812--816},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/ner/JindalSDCD15,
author = {Utkarsh Jindal and
Mehak Sood and
Abhijit Das and
Shubhajit Roy Chowdhury and
Anirban Dutta},
title = {Near infra-red spectroscopy combined with transcranial direct current
stimulation in FPGA-based hardware for point of care testing of cerebral
vascular status - {A} stroke study},
booktitle = {{NER}},
pages = {1040--1043},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/reconfig/ContrerasCML15,
author = {Luis Contreras and
S{\'{e}}rgio Cruz and
Jos{\'{e}} Maur{\'{\i}}cio S. T. Motta and
Carlos H. Llanos},
title = {{FPGA} implementation of the {EKF} algorithm for localization in mobile
robotics using a unified hardware module approach},
booktitle = {ReConFig},
pages = {1--6},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/reconfig/JaeschkeIZHP15,
author = {Timo Jaeschke and
Patrick Imberg and
Michael Zapke and
Michael H{\"{u}}bner and
Nils Pohl},
title = {Scalable modular hardware platform for {FPGA} based industrial radar
flowmeters},
booktitle = {ReConFig},
pages = {1--6},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/reconfig/RodriguezVT15,
author = {Alfonso Rodr{\'{\i}}guez and
Juan Valverde and
Eduardo de la Torre},
title = {Design of OpenCL-compatible multithreaded hardware accelerators with
dynamic support for embedded FPGAs},
booktitle = {ReConFig},
pages = {1--7},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/rivp/KachouriA15,
author = {Rostom Kachouri and
Mohamed Akil},
title = {Hardware design to accelerate {PNG} encoder for binary mask compression
on {FPGA}},
booktitle = {Real-Time Image and Video Processing},
series = {{SPIE} Proceedings},
volume = {9400},
pages = {940003},
publisher = {{SPIE}},
year = {2015}
}
@inproceedings{DBLP:conf/siot/BreierH15,
author = {Jakub Breier and
Wei He},
title = {Multiple Fault Attack on {PRESENT} with a Hardware Trojan Implementation
in {FPGA}},
booktitle = {SIoT},
pages = {58--64},
publisher = {{IEEE} Computer Society},
year = {2015}
}
@inproceedings{DBLP:conf/socc/GargALS15,
author = {Kratika Garg and
Yan Lin Aung and
Siew Kei Lam and
Thambipillai Srikanthan},
title = {KnapSim - Run-time efficient hardware-software partitioning technique
for FPGAs},
booktitle = {SoCC},
pages = {64--69},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/vlsi/KhanKBK15,
author = {Asim Khan and
Muhammad Umar Karim Khan and
Muhammad Bilal and
Chong{-}Min Kyung},
title = {Hardware architecture and optimization of sliding window based pedestrian
detection on {FPGA} for high resolution images by varying local features},
booktitle = {VLSI-SoC},
pages = {142--148},
publisher = {{IEEE}},
year = {2015}
}
@inproceedings{DBLP:conf/vtc/TadzaTL15,
author = {Nina Tadza and
John S. Thompson and
David I. Laurenson},
title = {Power Performance Analysis of the Iterative-MIMO Adaptive Switching
Algorithm Detector on the {FPGA} Hardware},
booktitle = {{VTC} Spring},
pages = {1--5},
publisher = {{IEEE}},
year = {2015}
}
@incollection{DBLP:series/sfsc/MhadhbiLOS15,
author = {Im{\`{e}}ne Mhadhbi and
Nabil Litayem and
Slim Ben Othman and
Slim Ben Saoud},
title = {Impact of Hardware/Software Partitioning and MicroBlaze {FPGA} Configurations
on the Embedded Systems Performances},
booktitle = {Complex System Modelling and Control Through Intelligent Soft Computations},
series = {Studies in Fuzziness and Soft Computing},
volume = {319},
pages = {711--744},
publisher = {Springer},
year = {2015}
}
@article{DBLP:journals/corr/ChangMC15,
author = {Andre Xian Ming Chang and
Berin Martini and
Eugenio Culurciello},
title = {Recurrent Neural Networks Hardware Implementation on {FPGA}},
journal = {CoRR},
volume = {abs/1511.05552},
year = {2015}
}
@article{DBLP:journals/corr/MollerKMZ15,
author = {Konrad M{\"{o}}ller and
Martin Kumm and
Charles{-}Frederic M{\"{u}}ller and
Peter Zipf},
title = {Model-based Hardware Design for FPGAs using Folding Transformations
based on Subcircuits},
journal = {CoRR},
volume = {abs/1508.06811},
year = {2015}
}
@article{DBLP:journals/iacr/BrinciKMRB15,
author = {Riadh Brinci and
Walid Khmiri and
Mefteh Mbarek and
Abdellatif Ben Rabaa and
Ammar Bouall{\`{e}}gue},
title = {Efficient Hardware Design for Computing Pairings Using Few {FPGA}
In-built DSPs},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {116},
year = {2015}
}
@article{DBLP:journals/asc/JuangJ14,
author = {Chia{-}Feng Juang and
Wen{-}Sheng Jang},
title = {A type-2 neural fuzzy system learned through type-1 fuzzy rules and
its FPGA-based hardware implementation},
journal = {Appl. Soft Comput.},
volume = {18},
pages = {302--313},
year = {2014}
}
@article{DBLP:journals/ieicet/LeCIP14,
author = {Duc{-}Hung Le and
Tran Bao Thuong Cao and
Katsumi Inoue and
Cong{-}Kha Pham},
title = {A CAM-Based Information Detection Hardware System for Fast Image Matching
on {FPGA}},
journal = {{IEICE} Trans. Electron.},
volume = {97-C},
number = {1},
pages = {65--76},
year = {2014}
}
@article{DBLP:journals/ijdsn/MalikTSL14,
author = {Abdul Waheed Malik and
Benny Th{\"{o}}rnberg and
Muhammad Imran and
Najeem Lawal},
title = {Hardware Architecture for Real-Time Computation of Image Component
Feature Descriptors on a {FPGA}},
journal = {Int. J. Distributed Sens. Networks},
volume = {10},
year = {2014}
}
@article{DBLP:journals/ijrc/JaquenodVS14,
author = {Guillermo A. Jaquenod and
Javier Valls and
Javier Siman},
title = {Efficient {FPGA} Hardware Reuse in a Multiplierless Decimation Chain},
journal = {Int. J. Reconfigurable Comput.},
volume = {2014},
pages = {546264:1--546264:5},
year = {2014}
}
@article{DBLP:journals/ijrc/TippettsLLA14,
author = {Beau J. Tippetts and
Dah{-}Jye Lee and
Kirt D. Lillywhite and
James K. Archibald},
title = {Hardware-Efficient Design of Real-Time Profile Shape Matching Stereo
Vision Algorithm on {FPGA}},
journal = {Int. J. Reconfigurable Comput.},
volume = {2014},
pages = {945926:1--945926:12},
year = {2014}
}
@article{DBLP:journals/jcp/ShengLLX14,
author = {Yingying Sheng and
Yan Liu and
Renfa Li and
Xiongren Xiao},
title = {A Communication-aware Scheduling Algorithm for Hardware Task Scheduling
Model on FPGA-based Reconfigurable Systems},
journal = {J. Comput.},
volume = {9},
number = {11},
pages = {2552--2558},
year = {2014}
}
@article{DBLP:journals/mam/Jain-MendonS14,
author = {Shweta Jain{-}Mendon and
Ron Sass},
title = {A hardware-software co-design approach for implementing sparse matrix
vector multiplication on FPGAs},
journal = {Microprocess. Microsystems},
volume = {38},
number = {8},
pages = {873--888},
year = {2014}
}
@article{DBLP:journals/mam/KliemV14,
author = {Daniel Kliem and
Sven{-}Ole Voigt},
title = {Scalability evaluation of an FPGA-based multi-core architecture with
hardware-enforced domain partitioning},
journal = {Microprocess. Microsystems},
volume = {38},
number = {8},
pages = {845--859},
year = {2014}
}
@article{DBLP:journals/mj/GosheblaghM14,
author = {Reza Omidi Gosheblagh and
Karim Mohammadi},
title = {Hybrid time and hardware redundancy to mitigate {SEU} effects on SRAM-FPGAs:
Case study over the MicroLAN protocol},
journal = {Microelectron. J.},
volume = {45},
number = {7},
pages = {870--879},
year = {2014}
}
@article{DBLP:journals/tcas/AtBOSY14,
author = {Nuray At and
Jean{-}Luc Beuchat and
Eiji Okamoto and
Ismail San and
Teppei Yamazaki},
title = {Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and
Skein on {FPGA}},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {61-I},
number = {2},
pages = {485--498},
year = {2014}
}
@article{DBLP:journals/tifs/ZhangC14,
author = {Li Zhang and
Chip{-}Hong Chang},
title = {A Pragmatic Per-Device Licensing Scheme for Hardware {IP} Cores on
SRAM-Based FPGAs},
journal = {{IEEE} Trans. Inf. Forensics Secur.},
volume = {9},
number = {11},
pages = {1893--1905},
year = {2014}
}
@article{DBLP:journals/tii/WangSD14,
author = {Wentao Wang and
Zhuoxuan Shen and
Venkata Dinavahi},
title = {Physics-Based Device-Level Power Electronic Circuit Hardware Emulation
on {FPGA}},
journal = {{IEEE} Trans. Ind. Informatics},
volume = {10},
number = {4},
pages = {2166--2179},
year = {2014}
}
@article{DBLP:journals/vlsisp/JainPCFM14,
author = {Abhishek Kumar Jain and
Khoa Dang Pham and
Jin Cui and
Suhaib A. Fahmy and
Douglas L. Maskell},
title = {Virtualized Execution and Management of Hardware Tasks on a Hybrid
{ARM-FPGA} Platform},
journal = {J. Signal Process. Syst.},
volume = {77},
number = {1-2},
pages = {61--76},
year = {2014}
}
@inproceedings{DBLP:conf/ahs/DumitriuKK14,
author = {Victor Dumitriu and
Lev Kirischian and
Valeri Kirischian},
title = {Decentralized run-time recovery mechanism for transient and permanent
hardware faults for space-borne FPGA-based computing systems},
booktitle = {{AHS}},
pages = {47--54},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/ahs/LopezVTR14,
author = {Blanca L{\'{o}}pez and
Juan Valverde and
Eduardo de la Torre and
Teresa Riesgo},
title = {Power-aware multi-objective evolvable hardware system on an {FPGA}},
booktitle = {{AHS}},
pages = {61--68},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/cases/JohnsonSCMG14,
author = {Anju P. Johnson and
Sayandeep Saha and
Rajat Subhra Chakraborty and
Debdeep Mukhopadhyay and
Sezer G{\"{o}}ren},
title = {Fault attack on {AES} via hardware Trojan insertion by dynamic partial
reconfiguration of {FPGA} over ethernet},
booktitle = {{WESS}},
pages = {1:1--1:8},
publisher = {{ACM}},
year = {2014}
}
@inproceedings{DBLP:conf/cse/LiFLW14,
author = {Han Li and
Yuzhuo Fu and
Ting Liu and
Jiafang Wang},
title = {Fast Protocol Decoding in Parallel with {FPGA} Hardware},
booktitle = {{CSE}},
pages = {1669--1673},
publisher = {{IEEE} Computer Society},
year = {2014}
}
@inproceedings{DBLP:conf/cvpr/EibensteinerKS14,
author = {Florian Eibensteiner and
J{\"{u}}rgen Kogler and
Josef Scharinger},
title = {A High-Performance Hardware Architecture for a Frameless Stereo Vision
Algorithm Implemented on a {FPGA} Platform},
booktitle = {{CVPR} Workshops},
pages = {637--644},
publisher = {{IEEE} Computer Society},
year = {2014}
}
@inproceedings{DBLP:conf/dasip/HindborgSJK14,
author = {Andreas Erik Hindborg and
Pascal Schleuniger and
Nicklas Bo Jensen and
Sven Karlsson},
title = {Hardware realization of an {FPGA} processor - Operating system call
offload and experiences},
booktitle = {{DASIP}},
pages = {1--8},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/ddecs/Malik14,
author = {Peter Mal{\'{\i}}k},
title = {Dedicated hardware architecture for object tracking preprocessing
implemented in {FPGA}},
booktitle = {{DDECS}},
pages = {250--253},
publisher = {{IEEE} Computer Society},
year = {2014}
}
@inproceedings{DBLP:conf/ewdts/YanovskayaYK14,
author = {Olga Yanovskaya and
Max Yanovsky and
Vyacheslav S. Kharchenko},
title = {The concept of green Cloud infrastructure based on distributed computing
and hardware accelerator within {FPGA} as a Service},
booktitle = {{EWDTS}},
pages = {1--4},
publisher = {{IEEE} Computer Society},
year = {2014}
}
@inproceedings{DBLP:conf/fccm/BymaSBLC14,
author = {Stuart Byma and
J. Gregory Steffan and
Hadi Bannazadeh and
Alberto Leon{-}Garcia and
Paul Chow},
title = {FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with
OpenStack},
booktitle = {{FCCM}},
pages = {109--116},
publisher = {{IEEE} Computer Society},
year = {2014}
}
@inproceedings{DBLP:conf/fpga/CasperO14,
author = {Jared Casper and
Kunle Olukotun},
title = {Hardware acceleration of database operations},
booktitle = {{FPGA}},
pages = {151--160},
publisher = {{ACM}},
year = {2014}
}
@inproceedings{DBLP:conf/fpga/ShilaV14,
author = {Devu Manikantan Shila and
Vivek Venugopal},
title = {Design, implementation and security analysis of hardware trojan threats
in {FPGA} (abstract only)},
booktitle = {{FPGA}},
pages = {247},
publisher = {{ACM}},
year = {2014}
}
@inproceedings{DBLP:conf/fpl/BlanchardonCMA14,
author = {Adrien Blanchardon and
Roselyne Chotin{-}Avot and
Habib Mehrez and
Emna Amouri},
title = {Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster
{FPGA} using hardware redundancy},
booktitle = {{FPL}},
pages = {1--4},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/fpl/BlockM14,
author = {Henry Block and
Tsutomu Maruyama},
title = {An {FPGA} hardware acceleration of the indirect calculation of tree
lengths method for phylogenetic tree reconstruction},
booktitle = {{FPL}},
pages = {1--4},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/fpl/Pietras14,
author = {Marcin Pietras},
title = {Hardware conversion of neural networks simulation models for neural
processing accelerator implemented as FPGA-based SoC},
booktitle = {{FPL}},
pages = {1--4},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/fpl/PohlSK14,
author = {Matthias Pohl and
Michael Schaeferling and
Gundolf Kiefer},
title = {An efficient FPGA-based hardware framework for natural feature extraction
and related Computer Vision tasks},
booktitle = {{FPL}},
pages = {1--8},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/fpl/Takamaeda-YamazakiK14,
author = {Shinya Takamaeda{-}Yamazaki and
Kenji Kise},
title = {flipSyrup: Cycle-accurate hardware simulation framework on abstract
{FPGA} platforms},
booktitle = {{FPL}},
pages = {1--4},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/fpt/Kojima14,
author = {Akira Kojima},
title = {{FPGA} implementation of Blokus Duo player using hardware/software
co-design},
booktitle = {{FPT}},
pages = {378--381},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/fuzzIEEE/SchrieberB14,
author = {Matthew D. Schrieber and
Mohammad Biglarbegian},
title = {Hardware implementation of a novel inference engine for interval type-2
fuzzy control on {FPGA}},
booktitle = {{FUZZ-IEEE}},
pages = {640--646},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/glvlsi/Mal-SarkarKGB14,
author = {Sanchita Mal{-}Sarkar and
Aswin Raghav Krishna and
Anandaroop Ghosh and
Swarup Bhunia},
title = {Hardware trojan attacks in {FPGA} devices: threat analysis and effective
counter measures},
booktitle = {{ACM} Great Lakes Symposium on {VLSI}},
pages = {287--292},
publisher = {{ACM}},
year = {2014}
}
@inproceedings{DBLP:conf/host/SollKMH14,
author = {Oliver Soll and
Thomas Korak and
Michael Muehlberghuber and
Michael Hutter},
title = {EM-based detection of hardware trojans on FPGAs},
booktitle = {{HOST}},
pages = {84--87},
publisher = {{IEEE} Computer Society},
year = {2014}
}
@inproceedings{DBLP:conf/hpec/HoareS14,
author = {Raymond R. Hoare and
Denis Smetana},
title = {Accelerating {SAR} processing on {COTS} {FPGA} hardware using C-to-gates
design tools},
booktitle = {{HPEC}},
pages = {1--6},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/icacci/Neelam14,
author = {Sapta Girish Neelam},
title = {Hardware-efficient {FPGA} implementation of symbol {\&} carrier
synchronization for 16-QAM},
booktitle = {{ICACCI}},
pages = {630--634},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/icc/ShilaV14,
author = {Devu Manikantan Shila and
Vivek Venugopal},
title = {Design, implementation and security analysis of Hardware Trojan Threats
in {FPGA}},
booktitle = {{ICC}},
pages = {719--724},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/iccS/BodiscoDKBH14,
author = {Timothy Bodisco and
Jason D'Netto and
Neil Kelson and
Jasmine Banks and
Ross Hayward},
title = {Computation of {ECG} Signal Features Using {MCMC} Modelling in Software
and {FPGA} Reconfigurable Hardware},
booktitle = {{ICCS}},
series = {Procedia Computer Science},
volume = {29},
pages = {2442--2448},
publisher = {Elsevier},
year = {2014}
}
@inproceedings{DBLP:conf/iccS/WarneKH14,
author = {David J. Warne and
Neil A. Kelson and
Ross F. Hayward},
title = {Comparison of High Level {FPGA} Hardware Design for Solving Tri-diagonal
Linear Systems},
booktitle = {{ICCS}},
series = {Procedia Computer Science},
volume = {29},
pages = {95--101},
publisher = {Elsevier},
year = {2014}
}
@inproceedings{DBLP:conf/icce-tw/LinF14,
author = {Kuen{-}Chih Lin and
Wai{-}Chi Fang},
title = {A highly integrated hardware design implemented on {FPGA} for a wireless
healthcare monitoring system},
booktitle = {{ICCE-TW}},
pages = {187--188},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/icecsys/TarawnehR14,
author = {Ghaith Tarawneh and
Jenny C. A. Read},
title = {An FPGA-based hardware accelerator for simulating spatiotemporal neurons},
booktitle = {{ICECS}},
pages = {618--621},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/icm2/HannachiRJAM14,
author = {Marwa Hannachi and
Hassan Rabah and
Slavisa Jovanovic and
Abdessalem Ben Abdelali and
Abdellatif Mtibaa},
title = {Efficient relocation of variable-sized hardware tasks for FPGA-based
adaptive systems},
booktitle = {{ICM}},
pages = {224--227},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/iecon/SchmittRJB14,
author = {Alexander Schmitt and
Jan Richter and
Uli Jurkewitz and
Michael Braun},
title = {FPGA-based real-time simulation of nonlinear permanent magnet synchronous
machines for power hardware-in-the-loop emulation systems},
booktitle = {{IECON}},
pages = {3763--3769},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/ijcnn/RenRCMZ14,
author = {Xiaowei Ren and
Pengju Ren and
Badong Chen and
Tai Min and
Nanning Zheng},
title = {Hardware implementation of {KLMS} algorithm using {FPGA}},
booktitle = {{IJCNN}},
pages = {2276--2281},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/iros/HoneggerOP14,
author = {Dominik Honegger and
Helen Oleynikova and
Marc Pollefeys},
title = {Real-time and low latency embedded computer vision hardware based
on a combination of {FPGA} and mobile {CPU}},
booktitle = {{IROS}},
pages = {4930--4935},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/iscas/SirkunanOSHM14,
author = {Jeevan Sirkunan and
Chia Yee Ooi and
Nasir Shaikh{-}Husin and
Yuan Wen Hau and
Muhammad Nadzir Marsono},
title = {Hardware transactional memory on multi-processor {FPGA} platform},
booktitle = {{ISCAS}},
pages = {2744--2747},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/ised/0001BMR14,
author = {Sudip Ghosh and
Arijit Biswas and
Santi P. Maity and
Hafizur Rahaman},
title = {Design of a Low Complexity and Fast Hardware Architecture for Digital
Image Watermarking in {FWHT} Domain on {FPGA}},
booktitle = {{ISED}},
pages = {68--72},
publisher = {{IEEE} Computer Society},
year = {2014}
}
@inproceedings{DBLP:conf/isie/RajeshRGS14,
author = {P. Rajesh and
S. Rajasekar and
Rajesh Gupta and
Paulson Samuel},
title = {Solar array system simulation using {FPGA} with hardware co-simulation},
booktitle = {{ISIE}},
pages = {2291--2296},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/ispec/TangLCP14,
author = {Shaohua Tang and
Bo Lv and
Guomin Chen and
Zhiniang Peng},
title = {Efficient Hardware Implementation of {MQ} Asymmetric Cipher {PMI+}
on FPGAs},
booktitle = {{ISPEC}},
series = {Lecture Notes in Computer Science},
volume = {8434},
pages = {187--201},
publisher = {Springer},
year = {2014}
}
@inproceedings{DBLP:conf/jckbse/AndreevDEZSA14,
author = {Andrey Andreev and
Evgueni Doukhnitch and
Vitaly Egunov and
Dmitriy Zharikov and
Oleg Shapovalov and
Sergey Artuh},
title = {Evaluation of Hardware Implementations of CORDIC-Like Algorithms in
{FPGA} Using OpenCL Kernels},
booktitle = {{JCKBSE}},
series = {Communications in Computer and Information Science},
volume = {466},
pages = {228--242},
publisher = {Springer},
year = {2014}
}
@inproceedings{DBLP:conf/nabic/MachadoWM14,
author = {Pedro Machado and
John J. Wade and
T. Martin McGinnity},
title = {Si elegans: {FPGA} hardware emulation of C. elegans nematode nervous
system},
booktitle = {NaBIC},
pages = {65--71},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/neurotechnix/KrewerCCM14,
author = {Finn Krewer and
Aedan Coffey and
Frank Callaly and
Fearghal Morgan},
title = {Neuron Models in {FPGA} Hardware - {A} Route from High Level Descriptions
to Hardware Implementations},
booktitle = {{NEUROTECHNIX}},
pages = {177--183},
publisher = {SciTePress},
year = {2014}
}
@inproceedings{DBLP:conf/norchip/ToftN14,
author = {Jakob Kenn Toft and
Alberto Nannarelli},
title = {Energy efficient {FPGA} based hardware accelerators for financial
applications},
booktitle = {{NORCHIP}},
pages = {1--6},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/patmos/HesselbarthBB14,
author = {Sebastian Hesselbarth and
Tim Baumgart and
Holger Blume},
title = {Hardware-assisted power estimation for design-stage processors using
{FPGA} emulation},
booktitle = {{PATMOS}},
pages = {1--8},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/reconfig/DingH14,
author = {Hongyuan Ding and
Miaoqing Huang},
title = {A unified OpenCL-flavor programming model with scalable hybrid hardware
platform on FPGAs},
booktitle = {ReConFig},
pages = {1--7},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/reconfig/LuoFFDLK14,
author = {Pei Luo and
Yunsi Fei and
Xin Fang and
A. Adam Ding and
Miriam Leeser and
David R. Kaeli},
title = {Power analysis attack on hardware implementation of MAC-Keccak on
FPGAs},
booktitle = {ReConFig},
pages = {1--7},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/recosoc/YingHH14,
author = {Haoyuan Ying and
Thomas Hollstein and
Klaus Hofmann},
title = {A hardware/software co-design reconfigurable Network-on-Chip {FPGA}
emulation method},
booktitle = {ReCoSoC},
pages = {1--8},
publisher = {{IEEE}},
year = {2014}
}
@inproceedings{DBLP:conf/sbac-pad/SilvaS14,
author = {Antonio Carlos Fernandes da Silva and
Jorge Luiz e Silva},
title = {The ChipCflow: {A} Tool to Generate Hardware Accelerators Using a
Static Dataflow Machine Designed for a {FPGA}},
booktitle = {{SBAC-PAD} (Workshops)},
pages = {90--95},
publisher = {{IEEE} Computer Society},
year = {2014}
}
@inproceedings{DBLP:conf/vlsid/KhurshidM14,
author = {Burhan Khurshid and
Roohie Naaz Mir},
title = {A Hardware Intensive Approach for Efficient Implementation of Numerical
Integration for {FPGA} Platforms},
booktitle = {{VLSID}},
pages = {312--317},
publisher = {{IEEE} Computer Society},
year = {2014}
}
@article{DBLP:journals/corr/MiyajimaTA14,
author = {Takaaki Miyajima and
David B. Thomas and
Hideharu Amano},
title = {An Automatic Mixed Software Hardware Pipeline Builder for {CPU-FPGA}
Platforms},
journal = {CoRR},
volume = {abs/1408.4969},
year = {2014}
}
@article{DBLP:journals/corr/VidanagamachchiDRN14,
author = {S. M. Vidanagamachchi and
S. D. Dewasurendra and
Roshan G. Ragel and
M. Niranjan},
title = {Tile optimization for area in {FPGA} based hardware acceleration of
peptide identification},
journal = {CoRR},
volume = {abs/1403.7296},
year = {2014}
}
@article{DBLP:journals/iacr/LuoFFDLK14,
author = {Pei Luo and
Yunsi Fei and
Xin Fang and
A. Adam Ding and
Miriam Leeser and
David R. Kaeli},
title = {Power Analysis Attack on Hardware Implementation of MAC-Keccak on
FPGAs},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {854},
year = {2014}
}
@phdthesis{DBLP:phd/basesearch/Choi13a,
author = {Yuk{-}Ming Choi},
title = {A run-time hardware task execution framework for FPGA-accelerated
heterogeneous cluster},
school = {University of Hong Kong},
year = {2013}
}
@phdthesis{DBLP:phd/dnb/Schmidt13,
author = {Michael Schmidt},
title = {Evaluierung gitterbasierter Pfadplanungs-Algorithmen f{\"{u}}r
die Hardwarebeschleunigung mit FPGAs},
school = {University of Erlangen-Nuremberg},
year = {2013}
}
@phdthesis{DBLP:phd/hal/Trabelsi13,
author = {Chiraz Trabelsi},
title = {Contr{\^{o}}le mat{\'{e}}riel des syst{\`{e}}mes partiellement
reconfigurables sur {FPGA} : de la mod{\'{e}}lisation {\`{a}}
l'impl{\'{e}}mentation. (Hardware Control of partially reconfigurable
FPGA-systems: from modeling to implementation)},
school = {Lille University of Science and Technology, France},
year = {2013}
}
@article{DBLP:journals/caee/Guzman-RamirezG13,
author = {Enrique Guzm{\'{a}}n{-}Ram{\'{\i}}rez and
Iv{\'{a}}n A. Garc{\'{\i}}a},
title = {Using the project-based learning approach for incorporating an FPGA-based
integrated hardware/software tool for implementing and evaluating
image processing algorithms into graduate level courses},
journal = {Comput. Appl. Eng. Educ.},
volume = {21},
number = {{S1}},
pages = {E73--E88},
year = {2013}
}
@article{DBLP:journals/candie/Santiago-PerezORM13,
author = {J. Jesus de Santiago{-}Perez and
Roque Alfredo Osornio{-}Rios and
Ren{\'{e}} de Jes{\'{u}}s Romero{-}Troncoso and
Luis Morales{-}Velazquez},
title = {FPGA-based hardware {CNC} interpolator of Bezier, splines, B-splines
and {NURBS} curves for industrial applications},
journal = {Comput. Ind. Eng.},
volume = {66},
number = {4},
pages = {925--932},
year = {2013}
}
@article{DBLP:journals/computing/NambiarBHM13,
author = {Vishnu P. Nambiar and
Sathivellu Balakrishnan and
Mohamed Khalil Hani and
Muhammad N. Marsono},
title = {{HW/SW} co-design of reconfigurable hardware-based genetic algorithm
in FPGAs applicable to a variety of problems},
journal = {Computing},
volume = {95},
number = {9},
pages = {863--896},
year = {2013}
}
@article{DBLP:journals/dt/ChakrabortySPN13,
author = {Rajat Subhra Chakraborty and
Indrasish Saha and
Ayan Palchaudhuri and
Gowtham Kumar Naik},
title = {Hardware Trojan Insertion by Direct Modification of {FPGA} Configuration
Bitstream},
journal = {{IEEE} Des. Test},
volume = {30},
number = {2},
pages = {45--54},
year = {2013}
}
@article{DBLP:journals/esl/CristoFGPM13,
author = {Alejandro Cristo and
Kevin Fisher and
J. Anthony Gualtieri and
Rosa M. P{\'{e}}rez and
Pablo Mart{\'{\i}}nez},
title = {Optimization of Processor-to-Hardware Module Communications on Spaceborne
Hybrid FPGA-based Architectures},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {5},
number = {4},
pages = {77--80},
year = {2013}
}
@article{DBLP:journals/ijrc/IturbeBHEAM13,
author = {Xabier Iturbe and
Khaled Benkrid and
Chuan Hong and
Ali Ebrahim and
Tughrul Arslan and
Imanol Martinez},
title = {Runtime Scheduling, Allocation, and Execution of Real-Time Hardware
Tasks onto Xilinx FPGAs Subject to Fault Occurrence},
journal = {Int. J. Reconfigurable Comput.},
volume = {2013},
pages = {905057:1--905057:32},
year = {2013}
}
@article{DBLP:journals/ijrc/JozwikHETT13,
author = {Krzysztof Jozwik and
Shinya Honda and
Masato Edahiro and
Hiroyuki Tomiyama and
Hiroaki Takada},
title = {Rainbow: An Operating System for Software-Hardware Multitasking on
Dynamically Partially Reconfigurable FPGAs},
journal = {Int. J. Reconfigurable Comput.},
volume = {2013},
pages = {789134:1--789134:40},
year = {2013}
}
@article{DBLP:journals/integration/PapadopoulosKPT13,
author = {Agathoklis Papadopoulos and
Ioannis Kirmitzoglou and
Vasilis J. Promponas and
Theocharis Theocharides},
title = {FPGA-based hardware acceleration for local complexity analysis of
massive genomic data},
journal = {Integr.},
volume = {46},
number = {3},
pages = {230--239},
year = {2013}
}
@article{DBLP:journals/jcsc/BarkalovTMS13,
author = {Alexander Barkalov and
Larysa Titarenko and
Raisa Malcheva and
Kyryll Soldatov},
title = {Hardware Reduction in FPGA-Based Moore {FSM}},
journal = {J. Circuits Syst. Comput.},
volume = {22},
number = {3},
year = {2013}
}
@article{DBLP:journals/jnw/NiuWZGZ13,
author = {Xiaoxia Niu and
Yanxia Wu and
Bowei Zhang and
Guochang Gu and
Guoyin Zhang},
title = {Rapid FPGA-based Delay Estimation for the Hardware/Software Partitioning},
journal = {J. Networks},
volume = {8},
number = {5},
pages = {1183--1190},
year = {2013}
}
@article{DBLP:journals/mam/GultekinS13,
author = {Gokhan Koray Gultekin and
Afsar Saranli},
title = {An {FPGA} based high performance optical flow hardware design for
computer vision applications},
journal = {Microprocess. Microsystems},
volume = {37},
number = {3},
pages = {270--286},
year = {2013}
}
@article{DBLP:journals/mcs/BahriIMB13,
author = {Imen Bahri and
Lahoucine Idkhajine and
Eric Monmasson and
Mohamed El Amine Benkhelifa},
title = {Optimal hardware/software partitioning of a system on chip FPGA-based
sensorless {AC} drive current controller},
journal = {Math. Comput. Simul.},
volume = {90},
pages = {145--161},
year = {2013}
}
@article{DBLP:journals/sensors/BenrekiaAB13,
author = {Fay{\c{c}}al Benrekia and
Mokhtar Attari and
Mounir Bouhedda},
title = {Gas Sensors Characterization and Multilayer Perceptron {(MLP)} Hardware
Implementation for Gas Identification Using a Field Programmable Gate
Array {(FPGA)}},
journal = {Sensors},
volume = {13},
number = {3},
pages = {2967--2985},
year = {2013}
}
@article{DBLP:journals/sensors/BiasizzoN13,
author = {Anton Biasizzo and
Franc Novak},
title = {Hardware Accelerated Compression of {LIDAR} Data Using {FPGA} Devices},
journal = {Sensors},
volume = {13},
number = {5},
pages = {6405--6422},
year = {2013}
}
@article{DBLP:journals/tii/BahriIMB13,
author = {Imen Bahri and
Lahoucine Idkhajine and
Eric Monmasson and
Mohamed El Amine Benkhelifa},
title = {Hardware/Software Codesign Guidelines for System on Chip FPGA-Based
Sensorless {AC} Drive Applications},
journal = {{IEEE} Trans. Ind. Informatics},
volume = {9},
number = {4},
pages = {2165--2176},
year = {2013}
}
@article{DBLP:journals/tii/BroxSTBM13,
author = {Mar{\'{\i}}a Brox and
Santiago S{\'{a}}nchez{-}Solano and
Ernesto del Toro and
Piedad Brox and
Francisco Jose Moreno{-}Velo},
title = {{CAD} Tools for Hardware Implementation of Embedded Fuzzy Systems
on FPGAs},
journal = {{IEEE} Trans. Ind. Informatics},
volume = {9},
number = {3},
pages = {1635--1644},
year = {2013}
}
@article{DBLP:journals/vlsisp/WojcikowskiZPKS13,
author = {Marek W{\'{o}}jcikowski and
Robert Zaglewski and
Bogdan Pankiewicz and
Miron Klosowski and
Stanislaw Szczepanski},
title = {Hardware-Software Implementation of a Sensor Network for City Traffic
Monitoring Using the {FPGA-} and ASIC-Based Sensor Nodes},
journal = {J. Signal Process. Syst.},
volume = {71},
number = {1},
pages = {57--73},
year = {2013}
}
@inproceedings{DBLP:conf/ant/KambaleDK13,
author = {Vianney Kambale and
Karim Djouani and
Anish Mathew Kurien},
title = {Toward an {FPGA} Hardware Implementation of the Alamouti 4x2 Space-time
Block Coding},
booktitle = {{ANT/SEIT}},
series = {Procedia Computer Science},
volume = {19},
pages = {602--608},
publisher = {Elsevier},
year = {2013}
}
@inproceedings{DBLP:conf/arc/Morales-VillanuevaG13,
author = {Aurelio Morales{-}Villanueva and
Ann Gordon{-}Ross},
title = {{HTR:} On-Chip Hardware Task Relocation for Partially Reconfigurable
FPGAs},
booktitle = {{ARC}},
series = {Lecture Notes in Computer Science},
volume = {7806},
pages = {185--196},
publisher = {Springer},
year = {2013}
}
@inproceedings{DBLP:conf/asap/SchmidtF13,
author = {Andrew G. Schmidt and
Matthew French},
title = {Fast lossless image compression with Radiation Hardening by hardware/software
co-design on platform FPGAs},
booktitle = {{ASAP}},
pages = {103--106},
publisher = {{IEEE} Computer Society},
year = {2013}
}
@inproceedings{DBLP:conf/codes/WangBP13,
author = {Wei Wang and
Miodrag Bolic and
Jonathan Parri},
title = {pvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized
environment},
booktitle = {{CODES+ISSS}},
pages = {10:1--10:9},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/dsd/IvanA13,
author = {Teodor Ivan and
El Mostapha Aboulhamid},
title = {An Efficient Hardware Implementation of a {SAT} Problem Solver on
{FPGA}},
booktitle = {{DSD}},
pages = {209--216},
publisher = {{IEEE} Computer Society},
year = {2013}
}
@inproceedings{DBLP:conf/dsd/Morales-SandovalD13,
author = {Miguel Morales{-}Sandoval and
Arturo Diaz{-}Perez},
title = {Compact FPGA-Based Hardware Architectures for GF(2m) Multipliers},
booktitle = {{DSD}},
pages = {649--652},
publisher = {{IEEE} Computer Society},
year = {2013}
}
@inproceedings{DBLP:conf/dsd/VelegalatiSK13,
author = {Rajesh Velegalati and
Kinjal Shah and
Jens{-}Peter Kaps},
title = {Glitch Detection in Hardware Implementations on FPGAs Using Delay
Based Sampling Techniques},
booktitle = {{DSD}},
pages = {947--954},
publisher = {{IEEE} Computer Society},
year = {2013}
}
@inproceedings{DBLP:conf/fccm/Morales-VillanuevaG13,
author = {Aurelio Morales{-}Villanueva and
Ann Gordon{-}Ross},
title = {On-chip Context Save and Restore of Hardware Tasks on Partially Reconfigurable
FPGAs},
booktitle = {{FCCM}},
pages = {61--64},
publisher = {{IEEE} Computer Society},
year = {2013}
}
@inproceedings{DBLP:conf/fccm/ZhangLLCCZB13,
author = {Jiliang Zhang and
Yaping Lin and
Yongqiang Lu and
Ray C. C. Cheung and
Wenjie Che and
Qiang Zhou and
Jinian Bian},
title = {Binding Hardware IPs to Specific {FPGA} Device via Inter-twining the
{PUF} Response with the {FSM} of Sequential Circuits},
booktitle = {{FCCM}},
pages = {227},
publisher = {{IEEE} Computer Society},
year = {2013}
}
@inproceedings{DBLP:conf/fpga/BaiFLR13,
author = {Yu Bai and
Abigail Fuentes{-}Rivera and
Mingjie Lin and
Mike Riera},
title = {Exploiting algorithmic-level memory parallelism in distributed logic-memory
architecture through hardware-assisted dynamic graph (abstract only)},
booktitle = {{FPGA}},
pages = {273},
publisher = {{ACM}},
year = {2013}
}
@inproceedings{DBLP:conf/fpga/DaigneaultD13,
author = {Marc{-}Andr{\'{e}} Daigneault and
Jean{-}Pierre David},
title = {Hardware description and synthesis of control-intensive reconfigurable
dataflow architectures (abstract only)},
booktitle = {{FPGA}},
pages = {274--275},
publisher = {{ACM}},
year = {2013}
}
@inproceedings{DBLP:conf/fpga/DengZ13,
author = {Wenjuan Deng and
Yiqun Zhu},
title = {A memory-efficient hardware architecture for real-time feature detection
of the {SIFT} algorithm (abstract only)},
booktitle = {{FPGA}},
pages = {273},
publisher = {{ACM}},
year = {2013}
}
@inproceedings{DBLP:conf/fpga/HariaP13,
author = {Swapnil Haria and
Viktor K. Prasanna},
title = {AutoMapper: an automated tool for optimal hardware resource allocation
for networking applications on {FPGA} (abstract only)},
booktitle = {{FPGA}},
pages = {274},
publisher = {{ACM}},
year = {2013}
}
@inproceedings{DBLP:conf/fpga/OngLA13,
author = {Soon Ee Ong and
Siaw Chen Lee and
Noohul Basheer Zain Ali},
title = {Hardware implemented real-time operating system (abstract only)},
booktitle = {{FPGA}},
pages = {266},
publisher = {{ACM}},
year = {2013}
}
@inproceedings{DBLP:conf/fpga/VenugopalS13,
author = {Vivek Venugopal and
Devu Manikantan Shila},
title = {Hardware acceleration of {TEA} and {XTEA} algorithms on FPGA, {GPU}
and multi-core processors (abstract only)},
booktitle = {{FPGA}},
pages = {270},
publisher = {{ACM}},
year = {2013}
}
@inproceedings{DBLP:conf/fpga/WangLZMC13,
author = {Chao Wang and
Xi Li and
Xuehai Zhou and
Jim Martin and
Ray C. C. Cheung},
title = {Genome sequencing using mapreduce on {FPGA} with multiple hardware
accelerators (abstract only)},
booktitle = {{FPGA}},
pages = {266},
publisher = {{ACM}},
year = {2013}
}
@inproceedings{DBLP:conf/fpl/ChenZL13,
author = {Yi{-}Chung Chen and
Wei Zhang and
Hai (Helen) Li},
title = {A hardware security scheme for RRAM-based {FPGA}},
booktitle = {{FPL}},
pages = {1--4},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/fpl/YaoLSC13,
author = {Yuan Yao and
Zhongyong Lu and
Qingsong Shi and
Wenzhi Chen},
title = {{FPGA} based hardware-software co-designed dynamic binary translation
system},
booktitle = {{FPL}},
pages = {1--4},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/fpl/ZemcikJMMH13a,
author = {Pavel Zemc{\'{\i}}k and
Roman Jur{\'{a}}nek and
Petr Musil and
Martin Musil and
Michal Hradis},
title = {High performance {FPGA} object detector: Hardware prototype},
booktitle = {{FPL}},
pages = {1},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/fpt/BlockM13,
author = {Henry Block and
Tsutomu Maruyama},
title = {A hardware acceleration of a phylogenetic tree reconstruction with
maximum parsimony algorithm using {FPGA}},
booktitle = {{FPT}},
pages = {318--321},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/fpt/ChoiBA13,
author = {Jongsok Choi and
Stephen Dean Brown and
Jason Helge Anderson},
title = {From software threads to parallel hardware in high-level synthesis
for FPGAs},
booktitle = {{FPT}},
pages = {270--277},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/fpt/FanWCZWW13,
author = {Xitian Fan and
Chenlu Wu and
Wei Cao and
Xuegong Zhou and
Shengye Wang and
Lingli Wang},
title = {Implementation of high performance hardware architecture of OpenSURF
algorithm on {FPGA}},
booktitle = {{FPT}},
pages = {152--159},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/icaisc/KluskaH13,
author = {Jacek Kluska and
Zbigniew Hajduk},
title = {Hardware Implementation of {P1-TS} Fuzzy Rule-Based Systems on {FPGA}},
booktitle = {{ICAISC} {(1)}},
series = {Lecture Notes in Computer Science},
volume = {7894},
pages = {282--293},
publisher = {Springer},
year = {2013}
}
@inproceedings{DBLP:conf/icecsys/OhataSOMOCIIAMK13,
author = {Katsuki Ohata and
Yukitoshi Sanada and
Tetsuro Ogaki and
Kento Matsuyama and
Takanori Ohira and
Satoshi Chikuda and
Masaki Igarashi and
Masayuki Ikebe and
Tetsuya Asai and
Masato Motomura and
Tadahiro Kuroda},
title = {Hardware-oriented stereo vision algorithm based on 1-D guided filtering
and its {FPGA} implementation},
booktitle = {{ICECS}},
pages = {169--172},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/icpads/IbrahimTIBY13,
author = {Muhammad Nasir Ibrahim and
Chen Kean Tack and
Mariani Idroas and
Siti Noormaya Bilmas and
Zuraimi Yahya},
title = {Hardware Implementation of Math Module Based on {CORDIC} Algorithm
Using {FPGA}},
booktitle = {{ICPADS}},
pages = {628--632},
publisher = {{IEEE} Computer Society},
year = {2013}
}
@inproceedings{DBLP:conf/icpp/KnodelGLNS13,
author = {Oliver Knodel and
Andy Georgi and
Patrick Lehmann and
Wolfgang E. Nagel and
Rainer G. Spallek},
title = {Integration of a Highly Scalable, Multi-FPGA-Based Hardware Accelerator
in Common Cluster Infrastructures},
booktitle = {{ICPP}},
pages = {893--900},
publisher = {{IEEE} Computer Society},
year = {2013}
}
@inproceedings{DBLP:conf/iecon/AraujoLAMG13,
author = {Jos{\'{e}} {\'{A}}ngel Araujo and
Jes{\'{u}}s L{\'{a}}zaro and
Armando Astarloa and
Naiara Moreira and
Alain Garc{\'{\i}}a},
title = {Memory requirements analysis for {PRP} and {HSR} hardware implementations
on FPGAs},
booktitle = {{IECON}},
pages = {2297--2302},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/iecon/DagbagiHINMS13,
author = {Mohamed Dagbagi and
Asma Hemdani and
Lahoucine Idkhajine and
Mohamed Wissem Naouar and
Eric Monmasson and
Ilhem Slama{-}Belkhodja},
title = {FPGA-based Real-Time Hardware-In-the-Loop validation of a 3-phase
{PWM} rectifier controller},
booktitle = {{IECON}},
pages = {5374--5379},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/iecon/Khalil-HaniL13,
author = {Mohamed Khalil Hani and
Yee Hui Lee},
title = {{FPGA} embedded hardware system for finger vein biometric recognition},
booktitle = {{IECON}},
pages = {2273--2278},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/ieeehpcs/WernerGLP13,
author = {Stefan Werner and
Sven Groppe and
Volker Linnemann and
Thilo Pionteck},
title = {Hardware-accelerated join processing in large Semantic Web databases
with FPGAs},
booktitle = {{HPCS}},
pages = {131--138},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/iolts/YangHH0GLL13,
author = {Enshan Yang and
Keheng Huang and
Yu Hu and
Xiaowei Li and
Jian Gong and
Hongjin Liu and
Bo Liu},
title = {{HHC:} Hierarchical hardware checkpointing to accelerate fault recovery
for SRAM-based FPGAs},
booktitle = {{IOLTS}},
pages = {193--198},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/ipps/GallegoMOSTR13,
author = {Angel Gallego and
Javier Mora and
Andr{\'{e}}s Otero and
Rub{\'{e}}n Salvador and
Eduardo de la Torre and
Teresa Riesgo},
title = {A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing
Arrays},
booktitle = {{IPDPS} Workshops},
pages = {182--191},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/isie/GomesGPSCMT13,
author = {Tiago Gomes and
Paulo Garcia and
Sandro Pinto and
Filipe Salgado and
Jorge Cabral and
Jo{\~{a}}o Monteiro and
Adriano Tavares},
title = {Hardware-software extensions to a softcore processor for FPGA-based
adaptive {PID} control},
booktitle = {{ISIE}},
pages = {1--4},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/ispacs/ZhangJ13,
author = {Lijun Zhang and
Ying Jiang},
title = {A low-hardware consumption {FPGA} based configurable {LDPC} decoder},
booktitle = {{ISPACS}},
pages = {221--224},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/mixdes/KryjakKG13,
author = {Tomasz Kryjak and
Mateusz Komorkiewicz and
Marek Gorgon},
title = {Hardware implementation of the {PBAS} foreground detection method
in {FPGA}},
booktitle = {{MIXDES}},
pages = {479--484},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/mse/SchmadeckeLBB13,
author = {Ingo Schm{\"{a}}decke and
Christian Leibold and
Hans{-}Peter Br{\"{u}}ckner and
Holger Blume},
title = {Project-organized education: From {FPGA} prototyping to {ASIC} design:
Consecutive microelectronic education in designing application-specific
hardware},
booktitle = {{MSE}},
pages = {9--12},
publisher = {{IEEE} Computer Society},
year = {2013}
}
@inproceedings{DBLP:conf/npc/ZhangQQWZ13,
author = {Youhui Zhang and
Peng Qu and
Ziqiang Qian and
Hongwei Wang and
Weimin Zheng},
title = {Software/Hardware Hybrid Network-on-Chip Simulation on {FPGA}},
booktitle = {{NPC}},
series = {Lecture Notes in Computer Science},
volume = {8147},
pages = {167--178},
publisher = {Springer},
year = {2013}
}
@inproceedings{DBLP:conf/recosoc/HempelHPH13,
author = {Gerald Hempel and
Jan Hoyer and
Thilo Pionteck and
Christian Hochberger},
title = {Register allocation for high-level synthesis of hardware accelerators
targeting FPGAs},
booktitle = {ReCoSoC},
pages = {1--6},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/sbcci/DiasMP13,
author = {Wanderson Roger Azevedo Dias and
Edward David Moreno and
Isaac Nattan Palmeira},
title = {A new code compression algorithm and its decompressor in FPGA-based
hardware},
booktitle = {{SBCCI}},
pages = {1--6},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/siu/Aykenar13,
author = {Mehmet Burak Aykenar},
title = {Analysis of {FPGA} based recursive and non-recursive digital filters
according to hardware cost and performance},
booktitle = {{SIU}},
pages = {1--4},
publisher = {{IEEE}},
year = {2013}
}
@inproceedings{DBLP:conf/tsp/BeleanBB13,
author = {Bogdan Belean and
Monica Borda and
Adrian Bot},
title = {{FPGA} based hardware architectures for iterative algorithms implementations},
booktitle = {{TSP}},
pages = {751--754},
publisher = {{IEEE}},
year = {2013}
}
@article{DBLP:journals/iacr/AtBOSY13,
author = {Nuray At and
Jean{-}Luc Beuchat and
Eiji Okamoto and
Ismail San and
Teppei Yamazaki},
title = {Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and
Skein on {FPGA}},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {113},
year = {2013}
}
@article{DBLP:journals/iacr/TangLCP13,
author = {Shaohua Tang and
Bo Lv and
Guomin Chen and
Zhiniang Peng},
title = {Efficient Hardware Implementation of {MQ} Asymmetric Cipher {PMI+}
on FPGAs},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {878},
year = {2013}
}
@phdthesis{DBLP:phd/basesearch/Matei12,
author = {Elena Matei},
title = {Hardware accelerated {H.264} blocks for processing multiple high definition
streams in real-time: novel architecture and realization on {FPGA}
platform},
school = {Ghent University, Belgium},
year = {2012}
}
@article{DBLP:journals/cai/SakellariouB12,
author = {Christos Sakellariou and
Peter J. Bentley},
title = {Describing the FPGA-Based Hardware Architecture of Systemic Computation
(HAoS)},
journal = {Comput. Informatics},
volume = {31},
number = {3},
pages = {485},
year = {2012}
}
@article{DBLP:journals/dafes/HentatiEANA12,
author = {Manel Hentati and
Samya Elaoud and
Yassine Aoudni and
Jean{-}Fran{\c{c}}ois Nezan and
Mohamed Abid},
title = {An efficient Resource Management to optimize the placement of hardware
task on {FPGA} in the {RVC} framework},
journal = {Des. Autom. Embed. Syst.},
volume = {16},
number = {4},
pages = {363--380},
year = {2012}
}
@article{DBLP:journals/ieicet/JozwikTHT12,
author = {Krzysztof Jozwik and
Hiroyuki Tomiyama and
Shinya Honda and
Hiroaki Takada},
title = {A Novel Framework for Effective Preemptive Hardware Multitasking on
FPGAs},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {95-D},
number = {2},
pages = {345--353},
year = {2012}
}
@article{DBLP:journals/ieicet/KanetaYMAM12,
author = {Yusaku Kaneta and
Shingo Yoshizawa and
Shin{-}ichi Minato and
Hiroki Arimura and
Yoshikazu Miyanaga},
title = {A Dynamically Reconfigurable FPGA-Based Pattern Matching Hardware
for Subclasses of Regular Expressions},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {95-D},
number = {7},
pages = {1847--1857},
year = {2012}
}
@article{DBLP:journals/ieicet/LeISP12,
author = {Duc{-}Hung Le and
Katsumi Inoue and
Masahiro Sowa and
Cong{-}Kha Pham},
title = {An FPGA-Based Information Detection Hardware System Employing Multi-Match
Content Addressable Memory},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {95-A},
number = {10},
pages = {1708--1717},
year = {2012}
}
@article{DBLP:journals/ijrc/SchaeferlingHK12,
author = {Michael Schaeferling and
Ulrich Hornung and
Gundolf Kiefer},
title = {Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based
System Designs Accelerated by {FPGA} Logic},
journal = {Int. J. Reconfigurable Comput.},
volume = {2012},
pages = {368351:1--368351:16},
year = {2012}
}
@article{DBLP:journals/ijrc/SchmidtSFS12,
author = {Andrew G. Schmidt and
Neil Steiner and
Matthew French and
Ron Sass},
title = {HwPMI: An Extensible Performance Monitoring Infrastructure for Improving
Hardware Design and Productivity on FPGAs},
journal = {Int. J. Reconfigurable Comput.},
volume = {2012},
pages = {162404:1--162404:12},
year = {2012}
}
@article{DBLP:journals/isjgp/SanA12,
author = {Ismail San and
Nuray At},
title = {Compact Keccak Hardware Architecture for Data Integrity and Authentication
on FPGAs},
journal = {Inf. Secur. J. {A} Glob. Perspect.},
volume = {21},
number = {5},
pages = {231--242},
year = {2012}
}
@article{DBLP:journals/sigarch/SanoK12,
author = {Kentaro Sano and
Yoshiaki Kono},
title = {FPGA-based Connect6 solver with hardware-accelerated move refinement},
journal = {{SIGARCH} Comput. Archit. News},
volume = {40},
number = {5},
pages = {4--9},
year = {2012}
}
@article{DBLP:journals/tcas/BrucknerLZBMO12,
author = {Timon Br{\"{u}}ckner and
Matthias Lorenz and
Christoph Zorn and
Joachim Becker and
Wolfgang Mathis and
Maurits Ortmanns},
title = {Hardware-Accelerated Simulation Environment for {CT} Sigma-Delta Modulators
Using an {FPGA}},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {59-II},
number = {8},
pages = {471--475},
year = {2012}
}
@article{DBLP:journals/tgrs/BesirisTFT12,
author = {Dimitrios Besiris and
Vassilis Tsagaris and
Nikolaos Fragoulis and
Christos Theoharatos},
title = {An FPGA-Based Hardware Implementation of Configurable Pixel-Level
Color Image Fusion},
journal = {{IEEE} Trans. Geosci. Remote. Sens.},
volume = {50},
number = {2},
pages = {362--373},
year = {2012}
}
@article{DBLP:journals/tifs/MaesSV12,
author = {Roel Maes and
Dries Schellekens and
Ingrid Verbauwhede},
title = {A Pay-per-Use Licensing Scheme for Hardware {IP} Cores in Recent SRAM-Based
FPGAs},
journal = {{IEEE} Trans. Inf. Forensics Secur.},
volume = {7},
number = {1},
pages = {98--108},
year = {2012}
}
@article{DBLP:journals/tii/AlecsaCO12,
author = {Bogdan Alecsa and
Marcian N. Cirstea and
Alexandru Onea},
title = {Simulink Modeling and Design of an Efficient Hardware-Constrained
FPGA-Based {PMSM} Speed Controller},
journal = {{IEEE} Trans. Ind. Informatics},
volume = {8},
number = {3},
pages = {554--562},
year = {2012}
}
@article{DBLP:journals/tits/McDonaldEPP12,
author = {Gregor J. McDonald and
Jonathan S. Ellis and
Richard W. Penney and
Richard W. Price},
title = {Real-Time Vehicle Identification Performance Using {FPGA} Correlator
Hardware},
journal = {{IEEE} Trans. Intell. Transp. Syst.},
volume = {13},
number = {4},
pages = {1891--1895},
year = {2012}
}
@inproceedings{DBLP:conf/aciids/KasikPNPK12,
author = {Vladimir Kasik and
Marek Penhaker and
Vil{\'{e}}m Nov{\'{a}}k and
Radka Pustkova and
Frantisek Kutalek},
title = {Bio-inspired Genetic Algorithms on {FPGA} Evolvable Hardware},
booktitle = {{ACIIDS} {(2)}},
series = {Lecture Notes in Computer Science},
volume = {7197},
pages = {439--447},
publisher = {Springer},
year = {2012}
}
@inproceedings{DBLP:conf/csndsp/NekoueiTKM12,
author = {Farzad Nekouei and
Neda Zargar Talebi and
Yousef Seifi Kavian and
Ali Mahani},
title = {{FPGA} implementation of {LMS} self correcting adaptive filter {(SCAF)}
and hardware analysis},
booktitle = {{CSNDSP}},
pages = {1--5},
publisher = {{IEEE}},
year = {2012}
}
@inproceedings{DBLP:conf/dasip/CorreHDHL12,
author = {Youenn Corre and
Van{-}Trinh Hoang and
Jean{-}Philippe Diguet and
Dominique Heller and
Lo{\"{\i}}c Lagadec},
title = {HLS-based fast design space exploration of ad hoc hardware accelerators:
{A} key tool for MPSoC synthesis on {FPGA}},
booktitle = {{DASIP}},
pages = {1--8},
publisher = {{IEEE}},
year = {2012}
}
@inproceedings{DBLP:conf/date/TtofisT12,
author = {Christos Ttofis and
Theocharis Theocharides},
title = {Towards accurate hardware stereo correspondence: {A} real-time {FPGA}
implementation of a segmentation-based adaptive support weight algorithm},
booktitle = {{DATE}},
pages = {703--708},
publisher = {{IEEE}},
year = {2012}
}
@inproceedings{DBLP:conf/dsd/MavroidisMPLLTS12,
author = {Iakovos Mavroidis and
Ioannis Mavroidis and
Ioannis Papaefstathiou and
Luciano Lavagno and
Mihai T. Lazarescu and
Eduardo de la Torre and
Florian Sch{\"{a}}fer},
title = {{FASTCUDA:} Open Source {FPGA} Accelerator {\&} Hardware-Software
Codesign Toolset for {CUDA} Kernels},
booktitle = {{DSD}},
pages = {343--348},
publisher = {{IEEE} Computer Society},
year = {2012}
}
@inproceedings{DBLP:conf/etfa/GacKP12,
author = {Konrad Gac and
Grzegorz Karpiel and
Maciej Petko},
title = {{FPGA} based hardware accelerator for calculations of the parallel
robot inverse kinematics},
booktitle = {{ETFA}},
pages = {1--4},
publisher = {{IEEE}},
year = {2012}
}
@inproceedings{DBLP:conf/fpl/ChoiR12,
author = {Jungwook Choi and
Rob A. Rutenbar},
title = {Hardware implementation of {MRF} map inference on an {FPGA} platform},
booktitle = {{FPL}},
pages = {209--216},
publisher = {{IEEE}},
year = {2012}
}
@inproceedings{DBLP:conf/fpl/CzajkowskiADFKNWYS12,
author = {Tomasz S. Czajkowski and
Utku Aydonat and
Dmitry Denisenko and
John Freeman and
Michael Kinsner and
David Neto and
Jason Wong and
Peter Yiannacouras and
Deshanand P. Singh},
title = {From opencl to high-performance hardware on {FPGAS}},
booktitle = {{FPL}},
pages = {531--534},
publisher = {{IEEE}},
year = {2012}
}
@inproceedings{DBLP:conf/fpl/PilatoCDOSS12,
author = {Christian Pilato and
Andrea Cazzaniga and
Gianluca Durelli and
Andr{\'{e}}s Otero and
Donatella Sciuto and
Marco D. Santambrogio},
title = {On the automatic integration of hardware accelerators into FPGA-based
embedded systems},
booktitle = {{FPL}},
pages = {607--610},
publisher = {{IEEE}},
year = {2012}
}
@inproceedings{DBLP:conf/fpl/ZhengCP12,
author = {Jason Xin Zheng and
Ethan Chen and
Miodrag Potkonjak},
title = {A Benign Hardware Trojan on FPGA-based embedded systems},
booktitle = {{FPL}},
pages = {464--470},
publisher = {{IEEE}},
year = {2012}
}
@inproceedings{DBLP:conf/fpt/BrousseauR12,
author = {Braiden Brousseau and
Jonathan Rose},
title = {An energy-efficient, fast {FPGA} hardware architecture for OpenCV-Compatible
object detection},
booktitle = {{FPT}},
pages = {166--173},
publisher = {{IEEE}},
year = {2012}
}
@inproceedings{DBLP:conf/healthcom/SchwarzGPS12,
author = {Leandro Schwarz and
Humberto Remigio Gamba and
Fabio Cabral Pacheco and
Miguel Antonio Sovierzoski},
title = {Pupil detection in hardware using {FPGA}},
booktitle = {Healthcom},
pages = {361--364},
publisher = {{IEEE}},
year = {2012}
}
@inproceedings{DBLP:conf/hoti/LockwoodGMBEV12,
author = {John W. Lockwood and
Adwait Gupte and
Nishit Mehta and
Michaela Blott and
Tom English and
Kees A. Vissers},
title = {A Low-Latency Library in {FPGA} Hardware for High-Frequency Trading
{(HFT)}},
booktitle = {Hot Interconnects},
pages = {9--16},
publisher = {{IEEE} Computer Society},
year = {2012}
}
@inproceedings{DBLP:conf/hpcc/WangFCH12,
author = {Xun Wang and
Degui Feng and
Tianzhou Chen and
Tongsen Hu},
title = {Migration between Software and Hardware Task on Preemptive Multitasking
{CPU/FPGA} Hybrid Architecture},
booktitle = {{HPCC-ICESS}},
pages = {1329--1336},
publisher = {{IEEE} Computer Society},
year = {2012}
}
@inproceedings{DBLP:conf/icacci/BaskaranR12,
author = {Saambhavi Baskaran and
Pachamuthu Rajalakshmi},
title = {Hardware-software co-design of {AES} on {FPGA}},
booktitle = {{ICACCI}},
pages = {1118--1122},
publisher = {{ACM}},
year = {2012}
}
@inproceedings{DBLP:conf/icann/BeulerTBPB12,
author = {Marcel Beuler and
Aubin Tchaptchet and
Werner Bonath and
Svetlana Postnova and
Hans Albert Braun},
title = {Real-Time Simulations of Synchronization in a Conductance-Based Neuronal
Network with a Digital {FPGA} Hardware-Core},
booktitle = {{ICANN} {(1)}},
series = {Lecture Notes in Computer Science},
volume = {7552},
pages = {97--104},
publisher = {Springer},
year = {2012}
}
@inproceedings{DBLP:conf/icecsys/BucekKLZ12,
author = {Jir{\'{\i}} Bucek and
Pavel Kubal{\'{\i}}k and
R{\'{o}}bert L{\'{o}}rencz and
Tom{\'{a}}s Zahradnick{\'{y}}},
title = {Dedicated hardware implementation of a linear congruence solver in
{FPGA}},
booktitle = {{ICECS}},
pages = {689--692},
publisher = {{IEEE}},
year = {2012}
}
@inproceedings{DBLP:conf/icecsys/MahdiSKTP12,
author = {Ahmed Mahdi and
Panagiotis Sakellariou and
Nikos Kanistras and
Ioannis Tsatsaragkos and
Vassilis Paliouras},
title = {Hardware design and verification techniques for Giga-bit Forward-Error
Correction systems on FPGAs},
booktitle = {{ICECS}},
pages = {89--92},
publisher = {{IEEE}},
year = {2012}
}
@inproceedings{DBLP:conf/icics/MaXLJLY12,
author = {Yuan Ma and
Luning Xia and
Jingqiang Lin and
Jiwu Jing and
Zongbin Liu and
Xingjie Yu},
title = {Hardware Performance Optimization and Evaluation of {SM3} Hash Algorithm
on {FPGA}},
booktitle = {{ICICS}},
series = {Lecture Notes in Computer Science},
volume = {7618},
pages = {105--118},
publisher = {Springer},
year = {2012}
}
@inproceedings{DBLP:conf/iwcmc/GroleatAV12,
author = {Tristan Groleat and
Matthieu Arzel and
Sandrine Vaton},
title = {Hardware acceleration of SVM-based traffic classification on {FPGA}},
booktitle = {{IWCMC}},
pages = {443--449},
publisher = {{IEEE}},
year = {2012}
}
@inproceedings{DBLP:conf/new2an/YinLH12,
author = {Dong Yin and
Ge Li and
Kedi Huang},
title = {Scalable MapReduce Framework on {FPGA} Accelerated Commodity Hardware},
booktitle = {{NEW2AN}},
series = {Lecture Notes in Computer Science},
volume = {7469},
pages = {280--294},
publisher = {Springer},
year = {2012}
}
@inproceedings{DBLP:conf/nips/NiuNSS12,
author = {Chuanxin Minos Niu and
Sirish K. Nandyala and
Won Joon Sohn and
Terence D. Sanger},
title = {Multi-scale Hyper-time Hardware Emulation of Human Motor Nervous System
Based on Spiking Neurons using {FPGA}},
booktitle = {{NIPS}},
pages = {37--45},
year = {2012}
}
@inproceedings{DBLP:conf/norchip/HegnerSN12,
author = {Jonas Stenbaek Hegner and
Joakim Sindholt and
Alberto Nannarelli},
title = {Design of power efficient {FPGA} based hardware accelerators for financial
applications},
booktitle = {{NORCHIP}},
pages = {1--4},
publisher = {{IEEE}},
year = {2012}
}
@inproceedings{DBLP:conf/pdes/PopescuGB12,
author = {Silvana Oana Popescu and
Aurel Gontean and
Georgeta Budura},
title = {Hardware Co-simulation of the {BPSK} and {QPSK} systems on {FPGA}},
booktitle = {PDeS},
pages = {299--304},
publisher = {International Federation of Automatic Control},
year = {2012}
}
@inproceedings{DBLP:conf/peccs/AmaricaiB12,
author = {Alexandru Amaricai and
Oana Boncalo},
title = {Automatic Generation of {FPGA} Hardware Accelerators for Graphics
Applications},
booktitle = {{PECCS}},
pages = {383--386},
publisher = {SciTePress},
year = {2012}
}
@inproceedings{DBLP:conf/peccs/FischerR12,
author = {Bennet Fischer and
Ra{\'{u}}l Rojas},
title = {Image Processing Framework for FPGAs - Introducing a Plug-and-play
Computer Vision Framework for Fast Integration of Algorithms in Reconfigurable
Hardware},
booktitle = {{PECCS}},
pages = {295--300},
publisher = {SciTePress},
year = {2012}
}
@inproceedings{DBLP:conf/samos/Blume12,
author = {Holger Blume},
title = {Special session on "FPGA-based emulation of hardware architectures"},
booktitle = {{ICSAMOS}},
pages = {276},
publisher = {{IEEE}},
year = {2012}
}
@inproceedings{DBLP:conf/samos/BorlenghiAWKALM12,
author = {Filippo Borlenghi and
Dominik Auras and
Ernst Martin Witte and
Torsten Kempf and
Gerd Ascheid and
Rainer Leupers and
Heinrich Meyr},
title = {An FPGA-accelerated testbed for hardware component development in
{MIMO} wireless communication systems},
booktitle = {{ICSAMOS}},
pages = {278--285},
publisher = {{IEEE}},
year = {2012}
}
@inproceedings{DBLP:conf/secrypt/AthanasiouCBMTG12,
author = {George Athanasiou and
Chara I. Chalkou and
D. Bardis and
Harris E. Michail and
George Theodoridis and
Costas E. Goutis},
title = {High-throughput Hardware Architectures of the {JH} Round-three {SHA-3}
Candidate - An {FPGA} Design and Implementation Approach},
booktitle = {{SECRYPT}},
pages = {126--135},
publisher = {SciTePress},
year = {2012}
}
@inproceedings{DBLP:conf/vlsi-dat/LiangHPR12,
author = {Guixuan Liang and
Danping He and
Jorge Portilla and
Teresa Riesgo},
title = {A hardware in the loop design methodology for {FPGA} system and its
application to complex functions},
booktitle = {{VLSI-DAT}},
pages = {1--4},
publisher = {{IEEE}},
year = {2012}
}
@phdthesis{DBLP:phd/ethos/Hashmi11,
author = {Adeel Hashmi},
title = {Hardware Acceleration of Network Intrusion Detection System Using
{FPGA}},
school = {Manchester Metropolitan University, {UK}},
year = {2011}
}
@article{DBLP:journals/cj/LiuCMC11,
author = {Qiang Liu and
George A. Constantinides and
Konstantinos Masselos and
Peter Y. K. Cheung},
title = {Compiling C-like Languages to {FPGA} Hardware: Some Novel Approaches
Targeting Data Memory Organization},
journal = {Comput. J.},
volume = {54},
number = {1},
pages = {1--10},
year = {2011}
}
@article{DBLP:journals/eswa/AhmadiMASK11,
author = {Ali Ahmadi and
Hans J{\"{u}}rgen Mattausch and
Md. Anwarul Abedin and
Mahmoud Saeidi and
Tetsushi Koide},
title = {An associative memory-based learning model with an efficient hardware
implementation in {FPGA}},
journal = {Expert Syst. Appl.},
volume = {38},
number = {4},
pages = {3499--3513},
year = {2011}
}
@article{DBLP:journals/ijnc/BoKNI11,
author = {Bo Song and
Kensuke Kawakami and
Koji Nakano and
Yasuaki Ito},
title = {An {RSA} Encryption Hardware Algorithm using a Single {DSP} Block
and a Single Block {RAM} on the {FPGA}},
journal = {Int. J. Netw. Comput.},
volume = {1},
number = {2},
pages = {277--289},
year = {2011}
}
@article{DBLP:journals/mam/HuongNK11,
author = {Giang Nguyen Huong and
Yeoul Na and
Seon Wook Kim},
title = {Applying frame layout to hardware design in {FPGA} for seamless support
of cross calls in {CPU-FPGA} coupling architecture},
journal = {Microprocess. Microsystems},
volume = {35},
number = {5},
pages = {462--472},
year = {2011}
}
@article{DBLP:journals/mam/LegatBN11,
author = {Uros Legat and
Anton Biasizzo and
Franc Novak},
title = {A compact {AES} core with on-line error-detection for {FPGA} applications
with modest hardware resources},
journal = {Microprocess. Microsystems},
volume = {35},
number = {4},
pages = {405--416},
year = {2011}
}
@article{DBLP:journals/tie/LeeSLHC11,
author = {Ming{-}Huan Lee and
Kuo{-}Kai Shyu and
Po{-}Lei Lee and
Chien{-}Ming Huang and
Yun{-}Jen Chiu},
title = {Hardware Implementation of {EMD} Using {DSP} and {FPGA} for Online
Signal Processing},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {58},
number = {6},
pages = {2473--2481},
year = {2011}
}
@article{DBLP:journals/tie/SudhaM11,
author = {N. Sudha and
A. R. Mohan},
title = {Hardware-Efficient Image-Based Robotic Path Planning in a Dynamic
Environment and Its {FPGA} Implementation},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {58},
number = {5},
pages = {1907--1920},
year = {2011}
}
@article{DBLP:journals/trets/BergeronPFD11,
author = {Etienne Bergeron and
Louis{-}David Perron and
Marc Feeley and
Jean{-}Pierre David},
title = {Logarithmic-Time {FPGA} Bitstream Analysis: {A} Step Towards {JIT}
Hardware Compilation},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {2},
pages = {12:1--12:27},
year = {2011}
}
@inproceedings{DBLP:conf/3pgcic/PereraL11,
author = {Darshika G. Perera and
Kin Fun Li},
title = {FPGA-Based Reconfigurable Hardware for Compute Intensive Data Mining
Applications},
booktitle = {3PGCIC},
pages = {100--108},
publisher = {{IEEE} Computer Society},
year = {2011}
}
@inproceedings{DBLP:conf/ahs/CancareBBCS11,
author = {Fabio Cancare and
Sheetal Bhandari and
Davide B. Bartolini and
Matteo Carminati and
Marco D. Santambrogio},
title = {A bird's eye view of FPGA-based Evolvable Hardware},
booktitle = {{AHS}},
pages = {169--175},
publisher = {{IEEE}},
year = {2011}
}
@inproceedings{DBLP:conf/asap/AldhamABC11,
author = {Mark Aldham and
Jason Helge Anderson and
Stephen Dean Brown and
Andrew Canis},
title = {Low-cost hardware profiling of run-time and energy in {FPGA} embedded
processors},
booktitle = {{ASAP}},
pages = {61--68},
publisher = {{IEEE} Computer Society},
year = {2011}
}
@inproceedings{DBLP:conf/ccece/AjamiD11,
author = {Raouf Ajami and
Anh Dinh},
title = {Design a hardware network firewall on {FPGA}},
booktitle = {{CCECE}},
pages = {674--678},
publisher = {{IEEE}},
year = {2011}
}
@inproceedings{DBLP:conf/dft/KermaniR11,
author = {Mehran Mozaffari Kermani and
Arash Reyhani{-}Masoleh},
title = {Reliable Hardware Architectures for the Third-Round {SHA-3} Finalist
Grostl Benchmarked on {FPGA} Platform},
booktitle = {{DFT}},
pages = {325--331},
publisher = {{IEEE} Computer Society},
year = {2011}
}
@inproceedings{DBLP:conf/embc/MountneyOS11,
author = {John Mountney and
Iyad Obeid and
Dennis Silage},
title = {Modular particle filtering {FPGA} hardware architecture for brain
machine interfaces},
booktitle = {{EMBC}},
pages = {4617--4620},
publisher = {{IEEE}},
year = {2011}
}
@inproceedings{DBLP:conf/embc/WangHZZ0CCZ11,
author = {Dong Wang and
Yaoyao Hao and
Xiaoping Zhu and
Ting Zhao and
Yiwen Wang and
Yaowu Chen and
Weidong Chen and
Xiaoxiang Zheng},
title = {{FPGA} implementation of hardware processing modules as coprocessors
in brain-machine interfaces},
booktitle = {{EMBC}},
pages = {4613--4616},
publisher = {{IEEE}},
year = {2011}
}
@inproceedings{DBLP:conf/emeit/ShiJG11,
author = {Yunfeng Shi and
Chuan Jin and
Feng Gao},
title = {The solution of ethernet based on hardware protocol stack {W5300}
and {FPGA}},
booktitle = {{EMEIT}},
pages = {1328--1331},
publisher = {{IEEE}},
year = {2011}
}
@inproceedings{DBLP:conf/ets/LegatBN11,
author = {Uros Legat and
Anton Biasizzo and
Franc Novak},
title = {{FPGA} Soft Error Recovery Mechanism with Small Hardware Overhead},
booktitle = {{ETS}},
pages = {207},
publisher = {{IEEE} Computer Society},
year = {2011}
}
@inproceedings{DBLP:conf/eurocon/PohronskaK11,
author = {Maria Pohronska and
Tibor Krajcovic},
title = {{FPGA} implementation of multiple hardware watchdog timers for enhancing
real-time systems security},
booktitle = {{EUROCON}},
pages = {1--4},
publisher = {{IEEE}},
year = {2011}
}
@inproceedings{DBLP:conf/fpga/LiuMHGH11,
author = {Ling Liu and
Oleksii Morozov and
Yuxing Han and
J{\"{u}}rg Gutknecht and
Patrick R. Hunziker},
title = {Automatic SoC design flow on many-core processors: a software hardware
co-design approach for FPGAs},
booktitle = {{FPGA}},
pages = {37--40},
publisher = {{ACM}},
year = {2011}
}
@inproceedings{DBLP:conf/fpl/IturbeBATM11,
author = {Xabier Iturbe and
Khaled Benkrid and
Tughrul Arslan and
Raul Torrego and
Imanol Martinez},
title = {Methods and Mechanisms for Hardware Multitasking: Executing and Synchronizing
Fully Relocatable Hardware Tasks in Xilinx FPGAs},
booktitle = {{FPL}},
pages = {295--300},
publisher = {{IEEE} Computer Society},
year = {2011}
}
@inproceedings{DBLP:conf/fpt/MarconiM11,
author = {Thomas Marconi and
Tulika Mitra},
title = {A novel online hardware task scheduling and placement algorithm for
3D partially reconfigurable FPGAs},
booktitle = {{FPT}},
pages = {1--6},
publisher = {{IEEE}},
year = {2011}
}
@inproceedings{DBLP:conf/gecco/BarenoBNT11,
author = {Carlos Iv{\'{a}}n Camargo Bare{\~{n}}o and
Cesar Augusto Pedraza Bonilla and
Luis Fernado Ni{\~{n}}o and
Jos{\'{e}} Ignacio Martinez Torre},
title = {Intrinsic evolvable hardware for combinatorial synthesis based on
SoC+FPGA and {GPU} platforms},
booktitle = {{GECCO} (Companion)},
pages = {189--190},
publisher = {{ACM}},
year = {2011}
}
@inproceedings{DBLP:conf/hvc/SimkovaLK11,
author = {Marcela Simkov{\'{a}} and
Ondrej Leng{\'{a}}l and
Michal Kajan},
title = {{HAVEN:} An Open Framework for FPGA-Accelerated Functional Verification
of Hardware},
booktitle = {Haifa Verification Conference},
series = {Lecture Notes in Computer Science},
volume = {7261},
pages = {247--253},
publisher = {Springer},
year = {2011}
}
@inproceedings{DBLP:conf/iccd/RillingGHMWJZ11,
author = {Justin Rilling and
David Graziano and
Jamin Hitchcock and
Tim Meyer and
Xinying Wang and
Phillip H. Jones and
Joseph Zambreno},
title = {Circumventing a ring oscillator approach to FPGA-based hardware Trojan
detection},
booktitle = {{ICCD}},
pages = {289--292},
publisher = {{IEEE} Computer Society},
year = {2011}
}
@inproceedings{DBLP:conf/icdsp/AbbaszadehAD11,
author = {Asgar Abbaszadeh and
Anasystem Azerbaijan and
Khosrov Dabbagh{-}Sadeghipour},
title = {A new hardware efficient reconfigurable fir filter architecture suitable
for {FPGA} applications},
booktitle = {{DSP}},
pages = {1--4},
publisher = {{IEEE}},
year = {2011}
}
@inproceedings{DBLP:conf/icecsys/PossaSV11,
author = {Paulo Da Cunha Possa and
David Schaillie and
Carlos Valderrama},
title = {FPGA-based hardware acceleration: {A} CPU/accelerator interface exploration},
booktitle = {{ICECS}},
pages = {374--377},
publisher = {{IEEE}},
year = {2011}
}
@inproceedings{DBLP:conf/icumt/GomesMP11a,
author = {Otavio de Souza Martins Gomes and
Robson L. Moreno and
Tales Cleber Pimenta},
title = {A fast cryptography pipelined hardware developed in {FPGA} with {VHDL}},
booktitle = {{ICUMT}},
pages = {1--6},
publisher = {{IEEE}},
year = {2011}
}
@inproceedings{DBLP:conf/isocc/JozwikTEHT11,
author = {Krzysztof Jozwik and
Hiroyuki Tomiyama and
Masato Edahiro and
Shinya Honda and
Hiroaki Takada},
title = {Hardware multitasking in dynamically partially reconfigurable FPGA-based
embedded systems},
booktitle = {{ISOCC}},
pages = {183--186},
publisher = {{IEEE}},
year = {2011}
}
@inproceedings{DBLP:conf/ispacs/YamamotoORH11,
author = {Kota Yamamoto and
Yoshiro Oba and
Zuiko Rikuhashi and
Hiroomi Hikawa},
title = {Automatic generation of hardware self-organizing map for {FPGA} implementation},
booktitle = {{ISPACS}},
pages = {1--6},
publisher = {{IEEE}},
year = {2011}
}
@inproceedings{DBLP:conf/mbmv/KubaM11,
author = {Matthias Kuba and
Zekeriya Mansuroglu},
title = {Untersuchung von Methoden zur Hardwarebeschleunigung eines FPGA-basierten
Java-Systems mit Soft-IP Prozessor},
booktitle = {{MBMV}},
pages = {155--162},
publisher = {OFFIS-Institut f{\"{u}}r Informatik},
year = {2011}
}
@inproceedings{DBLP:conf/memics/SakellariouB11,
author = {Christos Sakellariou and
Peter J. Bentley},
title = {Introducing the FPGA-Based Hardware Architecture of Systemic Computation
(HAoS)},
booktitle = {{MEMICS}},
series = {Lecture Notes in Computer Science},
volume = {7119},
pages = {179--190},
publisher = {Springer},
year = {2011}
}
@inproceedings{DBLP:conf/mse/Wang11,
author = {Xiaofang (Maggie) Wang},
title = {Using FPGA-based configurable processors in teaching hardware/software
co-design of embedded multiprocessor systems},
booktitle = {{MSE}},
pages = {114--117},
publisher = {{IEEE} Computer Society},
year = {2011}
}
@inproceedings{DBLP:conf/networking/PloszMKT11,
author = {S{\'{a}}ndor Pl{\'{o}}sz and
Istv{\'{a}}n Moldov{\'{a}}n and
L{\'{a}}szl{\'{o}} K{\'{a}}ntor and
Tuan Anh Trinh},
title = {Characterization of Power-Aware Reconfiguration in FPGA-Based Networking
Hardware},
booktitle = {Networking Workshops},
series = {Lecture Notes in Computer Science},
volume = {6827},
pages = {281--290},
publisher = {Springer},
year = {2011}
}
@inproceedings{DBLP:conf/norchip/BorupDN11,
author = {Nicolas Borup and
Jonas Dindorp and
Alberto Nannarelli},
title = {{FPGA} implementation of decimal processors for hardware acceleration},
booktitle = {{NORCHIP}},
pages = {1--4},
publisher = {{IEEE}},
year = {2011}
}
@inproceedings{DBLP:conf/paap/ChuongALSL11,
author = {Lieu My Chuong and
Yan Lin Aung and
Siew Kei Lam and
Thambipillai Srikanthan and
Chai{-}Soon Lim},
title = {Automatic Compilation of {C} Applications for FPGA-Based Hardware
Acceleration},
booktitle = {{PAAP}},
pages = {223--227},
publisher = {{IEEE} Computer Society},
year = {2011}
}
@inproceedings{DBLP:conf/peccs/OuniBMM11,
author = {Bassem Ouni and
Ikbel Belaid and
Fabrice Muller and
Maher Benjemaa},
title = {Placement of Hardware Tasks on {FPGA} using the Bees Algorithm},
booktitle = {{PECCS}},
pages = {498--505},
publisher = {SciTePress},
year = {2011}
}
@inproceedings{DBLP:conf/pqcrypto/TangYDCC11,
author = {Shaohua Tang and
Haibo Yi and
Jintai Ding and
Huan Chen and
Guomin Chen},
title = {High-Speed Hardware Implementation of Rainbow Signature on FPGAs},
booktitle = {PQCrypto},
series = {Lecture Notes in Computer Science},
volume = {7071},
pages = {228--243},
publisher = {Springer},
year = {2011}
}
@inproceedings{DBLP:conf/reconfig/IturbeBAHM11,
author = {Xabier Iturbe and
Khaled Benkrid and
Tughrul Arslan and
Chuan Hong and
Imanol Martinez},
title = {Empty Resource Compaction Algorithms for Real-Time Hardware Tasks
Placement on Partially Reconfigurable FPGAs Subject to Fault Ocurrence},
booktitle = {ReConFig},
pages = {27--34},
publisher = {{IEEE} Computer Society},
year = {2011}
}
@inproceedings{DBLP:conf/reconfig/JozwikTEHT11,
author = {Krzysztof Jozwik and
Hiroyuki Tomiyama and
Masato Edahiro and
Shinya Honda and
Hiroaki Takada},
title = {Rainbow: An {OS} Extension for Hardware Multitasking on Dynamically
Partially Reconfigurable FPGAs},
booktitle = {ReConFig},
pages = {416--421},
publisher = {{IEEE} Computer Society},
year = {2011}
}
@inproceedings{DBLP:conf/reconfig/SalmanRK11,
author = {Ahmad Salman and
Marcin Rogawski and
Jens{-}Peter Kaps},
title = {Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration
on Xilinx FPGAs},
booktitle = {ReConFig},
pages = {242--248},
publisher = {{IEEE} Computer Society},
year = {2011}
}
@inproceedings{DBLP:conf/reconfig/SchmidtS11,
author = {Andrew G. Schmidt and
Ron Sass},
title = {Improving {FPGA} Design and Evaluation Productivity with a Hardware
Performance Monitoring Infrastructure},
booktitle = {ReConFig},
pages = {422--427},
publisher = {{IEEE} Computer Society},
year = {2011}
}
@inproceedings{DBLP:conf/retis/BasuRDS11,
author = {Abhishek Basu and
Abhik Roy and
Tirtha Shankar Das and
Subir Kumar Sarkar},
title = {On the implementation of {QIM} {FPGA} hardware},
booktitle = {ReTIS},
pages = {287--292},
publisher = {{IEEE}},
year = {2011}
}
@article{DBLP:journals/iacr/TangYCCD11,
title = {High-speed Hardware Implementation of Rainbow Signatures on FPGAs},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {155},
year = {2011},
note = {Withdrawn.}
}
@phdthesis{DBLP:phd/ethos/McKechnie10,
author = {Paul Edward McKechnie},
title = {Validation and verification of the interconnection of hardware intellectual
property blocks for FPGA-based packet processing systems},
school = {University of Glasgow, {UK}},
year = {2010}
}
@article{DBLP:journals/ijmssc/KhoaPBN10,
author = {Dang Le Khoa and
Nguyen Huu Phuong and
Le Nguyen Binh and
Duc Nhan Nguyen},
title = {Simulink Model and FPGA-based {OFDM} Communication System: a simulation
and Hardware Integrated Platform},
journal = {Int. J. Model. Simul. Sci. Comput.},
volume = {1},
number = {3},
year = {2010}
}
@article{DBLP:journals/ijns/JohnstonPMM10,
author = {Simon Johnston and
Girijesh Prasad and
Liam P. Maguire and
T. Martin McGinnity},
title = {An {FPGA} Hardware/Software Co-Design towards Evolvable Spiking Neural
Networks for Robotics Application},
journal = {Int. J. Neural Syst.},
volume = {20},
number = {6},
pages = {447--461},
year = {2010}
}
@article{DBLP:journals/ijrc/BelaidMM10,
author = {Ikbel Belaid and
Fabrice Muller and
Maher Benjemaa},
title = {New Three-Level Resource Management Enhancing Quality of Offline Hardware
Task Placement on {FPGA}},
journal = {Int. J. Reconfigurable Comput.},
volume = {2010},
pages = {980762:1--980762:20},
year = {2010}
}
@article{DBLP:journals/jbcb/XiaDL10,
author = {Fei Xia and
Yong Dou and
Guo{-}Qing Lei},
title = {Fpqrna: Hardware-Accelerated Qrna Package for noncoding {RNA} Gene
Detecting on {FPGA}},
journal = {J. Bioinform. Comput. Biol.},
volume = {8},
number = {4},
pages = {743--761},
year = {2010}
}
@article{DBLP:journals/mva/JinCKJ10,
author = {Seunghun Jin and
Jung Uk Cho and
Key Ho Kwon and
Jae Wook Jeon},
title = {A dedicated hardware architecture for real-time auto-focusing using
an {FPGA}},
journal = {Mach. Vis. Appl.},
volume = {21},
number = {5},
pages = {727--734},
year = {2010}
}
@article{DBLP:journals/todaes/YuanGHLJ10,
author = {Mingxuan Yuan and
Zonghua Gu and
Xiuqiang He and
Xue Liu and
Lei Jiang},
title = {Hardware/software partitioning and pipelined scheduling on runtime
reconfigurable FPGAs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {15},
number = {2},
pages = {13:1--13:41},
year = {2010}
}
@article{DBLP:journals/vlsisp/DerrienQ10,
author = {Steven Derrien and
Patrice Quinton},
title = {Hardware Acceleration of {HMMER} on FPGAs},
journal = {J. Signal Process. Syst.},
volume = {58},
number = {1},
pages = {53--67},
year = {2010}
}
@inproceedings{DBLP:conf/ches/GajHR10,
author = {Kris Gaj and
Ekawat Homsirikamol and
Marcin Rogawski},
title = {Fair and Comprehensive Methodology for Comparing Hardware Performance
of Fourteen Round Two {SHA-3} Candidates Using FPGAs},
booktitle = {{CHES}},
series = {Lecture Notes in Computer Science},
volume = {6225},
pages = {264--278},
publisher = {Springer},
year = {2010}
}
@inproceedings{DBLP:conf/csndsp/NumanIM10,
author = {Mostafa Wasiuddin Numan and
Mohammad Tariqul Islam and
Norbahiah Misran},
title = {An efficient FPGA-based hardware implementation of {MIMO} wireless
systems},
booktitle = {{CSNDSP}},
pages = {152--156},
publisher = {{IEEE}},
year = {2010}
}
@inproceedings{DBLP:conf/csreaESA/HannaH10,
author = {Darrin M. Hanna and
Richard E. Haskell},
title = {FPGA-based Hybrid Systems in Forth: a Forth Core and Reconfigurable
Hardware from Forth},
booktitle = {{ESA}},
pages = {168--171},
publisher = {{CSREA} Press},
year = {2010}
}
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