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@inproceedings{DBLP:conf/isscc/OhCBKKRPKCSLSHC20,
  author       = {Chi{-}Sung Oh and
                  Ki Chul Chun and
                  Young{-}Yong Byun and
                  Yong{-}Ki Kim and
                  So{-}Young Kim and
                  Yesin Ryu and
                  Jaewon Park and
                  Sinho Kim and
                  Sang{-}uhn Cha and
                  Dong{-}Hak Shin and
                  Jungyu Lee and
                  Jong{-}Pil Son and
                  Byung{-}Kyu Ho and
                  Seong{-}Jin Cho and
                  Beomyong Kil and
                  Sungoh Ahn and
                  Baekmin Lim and
                  Yong{-}Sik Park and
                  Kijun Lee and
                  Myung{-}Kyu Lee and
                  Seungduk Baek and
                  Junyong Noh and
                  Jae{-}Wook Lee and
                  Seungseob Lee and
                  Sooyoung Kim and
                  Bo{-}Tak Lim and
                  Seouk{-}Kyu Choi and
                  Jin{-}Guk Kim and
                  Hye{-}In Choi and
                  Hyuk{-}Jun Kwon and
                  Jun Jin Kong and
                  Kyomin Sohn and
                  Nam Sung Kim and
                  Kwang{-}Il Park and
                  Jung{-}Bae Lee},
  title        = {22.1 {A} 1.1V 16GB 640GB/s {HBM2E} {DRAM} with a Data-Bus Window-Extension
                  Technique and a Synergetic On-Die {ECC} Scheme},
  booktitle    = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
                  2020, San Francisco, CA, USA, February 16-20, 2020},
  pages        = {330--332},
  publisher    = {{IEEE}},
  year         = {2020},
  url          = {https://doi.org/10.1109/ISSCC19947.2020.9063110},
  doi          = {10.1109/ISSCC19947.2020.9063110},
  timestamp    = {Mon, 11 Jan 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/OhCBKKRPKCSLSHC20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hpca/ChaOSHPJCJSCAK17,
  author       = {Sang{-}uhn Cha and
                  Seongil O and
                  Hyunsung Shin and
                  Sangjoon Hwang and
                  Kwang{-}Il Park and
                  Seong{-}Jin Jang and
                  Joo{-}Sun Choi and
                  Gyo{-}Young Jin and
                  Young Hoon Son and
                  Hyunyoon Cho and
                  Jung Ho Ahn and
                  Nam Sung Kim},
  title        = {Defect Analysis and Cost-Effective Resilience Architecture for Future
                  {DRAM} Devices},
  booktitle    = {2017 {IEEE} International Symposium on High Performance Computer Architecture,
                  {HPCA} 2017, Austin, TX, USA, February 4-8, 2017},
  pages        = {61--72},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/HPCA.2017.30},
  doi          = {10.1109/HPCA.2017.30},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hpca/ChaOSHPJCJSCAK17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/wsc/AhnP17,
  author       = {Ki Uhn Ahn and
                  Cheol{-}Soo Park},
  title        = {Artificial neural network models for building energy prediction},
  booktitle    = {2017 Winter Simulation Conference, {WSC} 2017, Las Vegas, NV, USA,
                  December 3-6, 2017},
  pages        = {2708--2716},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/WSC.2017.8247996},
  doi          = {10.1109/WSC.2017.8247996},
  timestamp    = {Wed, 16 Oct 2019 14:14:56 +0200},
  biburl       = {https://dblp.org/rec/conf/wsc/AhnP17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}