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@article{DBLP:journals/tcad/AgrawalD90,
author = {Prathima Agrawal and
William J. Dally},
title = {A hardware logic simulation system},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {1},
pages = {19--29},
year = {1990},
url = {https://doi.org/10.1109/43.45853},
doi = {10.1109/43.45853},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AgrawalD90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AgrawalRS90,
author = {Prathima Agrawal and
Scott H. Robinson and
Thomas G. Szymanski},
title = {Automatic modeling of switch-level networks using partial orders {[MOS}
circuits]},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {7},
pages = {696--707},
year = {1990},
url = {https://doi.org/10.1109/43.55209},
doi = {10.1109/43.55209},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AgrawalRS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Al-KhaliliZA90,
author = {Asim J. Al{-}Khalili and
Yong Zhu and
Dhamin Al{-}Khalili},
title = {A module generator for optimized {CMOS} buffers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {10},
pages = {1028--1046},
year = {1990},
url = {https://doi.org/10.1109/43.62730},
doi = {10.1109/43.62730},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Al-KhaliliZA90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Axelrad90,
author = {Valery Axelrad},
title = {Fourier method modeling of semiconductor devices},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {11},
pages = {1225--1237},
year = {1990},
url = {https://doi.org/10.1109/43.62760},
doi = {10.1109/43.62760},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Axelrad90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Ayres90,
author = {Ronald F. Ayres},
title = {Completely automatic completion of {VLSI} designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {2},
pages = {194--202},
year = {1990},
url = {https://doi.org/10.1109/43.46786},
doi = {10.1109/43.46786},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Ayres90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BenkoskiMCM90,
author = {Jacques Benkoski and
E. Vanden Meersch and
Luc J. M. Claesen and
Hugo De Man},
title = {Timing verification using statically sensitizable paths},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {10},
pages = {10723--10784},
year = {1990},
url = {https://doi.org/10.1109/43.62737},
doi = {10.1109/43.62737},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BenkoskiMCM90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BergnerK90,
author = {Wolfgang Bergner and
Roland Kircher},
title = {SITAR-an efficient 3-D simulator for optimization of nonplanar trench
structures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {11},
pages = {1184--1188},
year = {1990},
url = {https://doi.org/10.1109/43.62755},
doi = {10.1109/43.62755},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BergnerK90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BhattacharyaH90,
author = {Debashis Bhattacharya and
John P. Hayes},
title = {Designing for high-level test generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {7},
pages = {752--766},
year = {1990},
url = {https://doi.org/10.1109/43.55212},
doi = {10.1109/43.55212},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BhattacharyaH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Biswas90,
author = {Nripendra N. Biswas},
title = {On covering distant minterms by the camp algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {7},
pages = {786--789},
year = {1990},
url = {https://doi.org/10.1109/43.55215},
doi = {10.1109/43.55215},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Biswas90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BoothW90,
author = {Richard Booth and
Marvin White},
title = {Simulation of a {MOS} transistor with spatially nonuniform channel
parameters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {12},
pages = {1354--1357},
year = {1990},
url = {https://doi.org/10.1109/43.62780},
doi = {10.1109/43.62780},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BoothW90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BrambillaD90,
author = {Angelo Brambilla and
Enrico Dallago},
title = {A circuit-level simulation model of {PNPN} devices},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {12},
pages = {1254--1264},
year = {1990},
url = {https://doi.org/10.1109/43.62770},
doi = {10.1109/43.62770},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BrambillaD90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BraunsBSPA90,
author = {Gregory T. Brauns and
R. J. Bishop and
Michael Steer and
John J. Paulos and
Sasan H. Ardalan},
title = {Table-based modeling of delta-sigma modulators using {ZSIM}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {2},
pages = {142--150},
year = {1990},
url = {https://doi.org/10.1109/43.46780},
doi = {10.1109/43.46780},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BraunsBSPA90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BrewerG90,
author = {Forrest Brewer and
Daniel D. Gajski},
title = {Chippe: a system for constraint driven behavioral synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {7},
pages = {681--695},
year = {1990},
url = {https://doi.org/10.1109/43.55208},
doi = {10.1109/43.55208},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/BrewerG90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChakradharBA90,
author = {Srimat T. Chakradhar and
Michael L. Bushnell and
Vishwani D. Agrawal},
title = {Toward massively parallel automatic test generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {9},
pages = {981--994},
year = {1990},
url = {https://doi.org/10.1109/43.59074},
doi = {10.1109/43.59074},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChakradharBA90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChakravartyR90,
author = {Sreejit Chakravarty and
S. S. Ravi},
title = {Computing optimal test sequences from complete test sets for stuck-open
faults in {CMOS} circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {3},
pages = {329--331},
year = {1990},
url = {https://doi.org/10.1109/43.46808},
doi = {10.1109/43.46808},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChakravartyR90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChanK90,
author = {Pak K. Chan and
Kevin Karplus},
title = {Computing signal delay in general {RC} networks by tree/link partitioning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {8},
pages = {898--902},
year = {1990},
url = {https://doi.org/10.1109/43.57781},
doi = {10.1109/43.57781},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChanK90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengDD90,
author = {D. Y. Cheng and
J. T. Deutsch and
Robert W. Dutton},
title = {'Defensive programming' in the rapid development of a parallel scientific
program},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {6},
pages = {665--669},
year = {1990},
url = {https://doi.org/10.1109/43.55196},
doi = {10.1109/43.55196},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChengDD90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChiangSW90,
author = {Charles C. Chiang and
Majid Sarrafzadeh and
Chak{-}Kuen Wong},
title = {Global routing based on Steiner min-max trees},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {12},
pages = {1318--1325},
year = {1990},
url = {https://doi.org/10.1109/43.62776},
doi = {10.1109/43.62776},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChiangSW90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChinS90,
author = {Shiu{-}Kai Chin and
Edward P. Stabler},
title = {Synthesis of arithmetic hardware using hardware metafunctions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {8},
pages = {793--803},
year = {1990},
url = {https://doi.org/10.1109/43.57787},
doi = {10.1109/43.57787},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChinS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChowdhuryB90,
author = {S. Chowdhury and
Javed Sabir Barkatullah},
title = {Estimation of maximum currents in {MOS} {IC} logic circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {6},
pages = {642--654},
year = {1990},
url = {https://doi.org/10.1109/43.55194},
doi = {10.1109/43.55194},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChowdhuryB90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CohoonRS90,
author = {James P. Cohoon and
Dana S. Richards and
Jeffrey S. Salowe},
title = {An optimal Steiner tree algorithm for a net whose terminals lie on
the perimeter of a rectangle},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {4},
pages = {398--407},
year = {1990},
url = {https://doi.org/10.1109/43.45871},
doi = {10.1109/43.45871},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CohoonRS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongL90,
author = {Jason Cong and
C. L. Liu},
title = {Over-the-cell channel routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {4},
pages = {408--418},
year = {1990},
url = {https://doi.org/10.1109/43.45872},
doi = {10.1109/43.45872},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongL90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DamianiOFER90,
author = {Maurizio Damiani and
Piero Olivo and
Michele Favalli and
Silvia Ercolani and
Bruno Ricc{\`{o}}},
title = {Aliasing in signature analysis testing with multiple input shift registers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {12},
pages = {1344--1353},
year = {1990},
url = {https://doi.org/10.1109/43.62779},
doi = {10.1109/43.62779},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DamianiOFER90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DekkerBT90,
author = {Rob Dekker and
Frans P. M. Beenker and
Loek Thijssen},
title = {A realistic fault model and test algorithms for static random access
memories},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {6},
pages = {567--572},
year = {1990},
url = {https://doi.org/10.1109/43.55188},
doi = {10.1109/43.55188},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DekkerBT90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DembaULG90,
author = {Stephen R. Demba and
Ernst G. Ulrich and
Karen Panetta Lentz and
David Giramma},
title = {Experiences with concurrent fault simulation of diagnostic programs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {6},
pages = {621--628},
year = {1990},
url = {https://doi.org/10.1109/43.55192},
doi = {10.1109/43.55192},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DembaULG90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DemjanenkoU90,
author = {Michael Demjanenko and
Shambhu J. Upadhyaya},
title = {Yield enhancement of field programmable logic arrays by inherent component
redundancy},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {8},
pages = {876--884},
year = {1990},
url = {https://doi.org/10.1109/43.57784},
doi = {10.1109/43.57784},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DemjanenkoU90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DengS90,
author = {An{-}Chang Deng and
Yan{-}Chyuan Shiau},
title = {Generic linear {RC} delay modeling for digital {CMOS} circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {4},
pages = {367--376},
year = {1990},
url = {https://doi.org/10.1109/43.45868},
doi = {10.1109/43.45868},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DengS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Dervisoglu90,
author = {Bulent I. Dervisoglu},
title = {Application of scan hardware and software for debug and diagnostics
in a workstation environment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {6},
pages = {612--620},
year = {1990},
url = {https://doi.org/10.1109/43.55191},
doi = {10.1109/43.55191},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Dervisoglu90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DevadasM90,
author = {Srinivas Devadas and
Hi{-}Keung Tony Ma},
title = {Easily testable PLA-based finite state machines},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {6},
pages = {604--611},
year = {1990},
url = {https://doi.org/10.1109/43.55190},
doi = {10.1109/43.55190},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DevadasM90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DevadasMNS90,
author = {Srinivas Devadas and
Hi{-}Keung Tony Ma and
A. Richard Newton and
Alberto L. Sangiovanni{-}Vincentelli},
title = {Irredundant sequential machines via optimal logic synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {1},
pages = {8--18},
year = {1990},
url = {https://doi.org/10.1109/43.45852},
doi = {10.1109/43.45852},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DevadasMNS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Drusinsky-Yoresh90,
author = {Doron Drusinsky{-}Yoresh},
title = {Symbolic cover minimization of fully {I/O} specified finite state
machines},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {7},
pages = {779--781},
year = {1990},
url = {https://doi.org/10.1109/43.55214},
doi = {10.1109/43.55214},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Drusinsky-Yoresh90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DuboisPT90,
author = {Pierre{-}Fran{\c{c}}ois Dubois and
Alain Puissochet and
Anne{-}Marie Tagant},
title = {A general and flexible switchbox router: {CARIOCA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {12},
pages = {1307--1317},
year = {1990},
url = {https://doi.org/10.1109/43.62775},
doi = {10.1109/43.62775},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DuboisPT90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Ferguson90,
author = {F. Joel Ferguson},
title = {Detection of multiple faults in {MOS} circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {9},
pages = {1009--1014},
year = {1990},
url = {https://doi.org/10.1109/43.59077},
doi = {10.1109/43.59077},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Ferguson90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FujiwaraI90,
author = {Hideo Fujiwara and
Tomoo Inoue},
title = {Optimal granularity of test generation in a distributed system},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {8},
pages = {885--892},
year = {1990},
url = {https://doi.org/10.1109/43.57783},
doi = {10.1109/43.57783},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FujiwaraI90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FukudaSKN90,
author = {Sanae Fukuda and
Naoyuki Shigyo and
Koichi Kato and
Shin Nakamura},
title = {A {ULSI} 2-D capacitance simulator for complex structures based on
actual processes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {1},
pages = {39--47},
year = {1990},
url = {https://doi.org/10.1109/43.45855},
doi = {10.1109/43.45855},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FukudaSKN90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Gannett90,
author = {Joel W. Gannett},
title = {{SHORTFINDER:} a graphical {CAD} tool for locating net-to-net shorts
in {VLSI} chip layouts},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {6},
pages = {669--674},
year = {1990},
url = {https://doi.org/10.1109/43.55197},
doi = {10.1109/43.55197},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Gannett90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GoossensRVM90,
author = {Gert Goossens and
Jan M. Rabaey and
Joos Vandewalle and
Hugo De Man},
title = {An efficient microcode compiler for application specific {DSP} processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {9},
pages = {925--937},
year = {1990},
url = {https://doi.org/10.1109/43.59069},
doi = {10.1109/43.59069},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GoossensRVM90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Groeneveld90,
author = {Patrick Groeneveld},
title = {A multiple layer contour-based gridless channel router},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {12},
pages = {1278--1288},
year = {1990},
url = {https://doi.org/10.1109/43.62773},
doi = {10.1109/43.62773},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Groeneveld90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HeminkMK90,
author = {Gertjan J. Hemink and
Berend W. Meijer and
Hans G. Kerkhoff},
title = {Testability analysis of analog systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {6},
pages = {573--583},
year = {1990},
url = {https://doi.org/10.1109/43.55186},
doi = {10.1109/43.55186},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HeminkMK90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HoSVW90,
author = {Jan{-}Ming Ho and
Majid Sarrafzadeh and
Gopalakrishnan Vijayan and
Chak{-}Kuen Wong},
title = {Pad minimization for planar routing of multiple power nets},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {4},
pages = {419--426},
year = {1990},
url = {https://doi.org/10.1109/43.45873},
doi = {10.1109/43.45873},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HoSVW90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HoSVW90a,
author = {Jan{-}Ming Ho and
Majid Sarrafzadeh and
Gopalakrishnan Vijayan and
Chak{-}Kuen Wong},
title = {Layer assignment for multichip modules},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {12},
pages = {1272--1277},
year = {1990},
url = {https://doi.org/10.1109/43.62772},
doi = {10.1109/43.62772},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HoSVW90a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HoVW90,
author = {Jan{-}Ming Ho and
Gopalakrishnan Vijayan and
Chak{-}Kuen Wong},
title = {New algorithms for the rectilinear Steiner tree problem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {2},
pages = {185--193},
year = {1990},
url = {https://doi.org/10.1109/43.46785},
doi = {10.1109/43.46785},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HoVW90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HoppeNSS90,
author = {Bernhard Hoppe and
Gerd Neuendorf and
Doris Schmitt{-}Landsiedel and
J. Will Specks},
title = {Optimization of high-speed {CMOS} logic circuits with analytical models
for signal delay, chip area, and dynamic power dissipation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {3},
pages = {236--247},
year = {1990},
url = {https://doi.org/10.1109/43.46799},
doi = {10.1109/43.46799},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HoppeNSS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsiaoF90,
author = {Pei{-}Yung Hsiao and
Wu{-}Shiung Feng},
title = {Using a multiple storage quad tree on a hierarchical {VLSI} compaction
scheme},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {5},
pages = {522--536},
year = {1990},
url = {https://doi.org/10.1109/43.55182},
doi = {10.1109/43.55182},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsiaoF90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuC90,
author = {Yu Hen Hu and
Sao{-}Jie Chen},
title = {{GM} Plan: a gate matrix layout algorithm based on artificial intelligence
planning techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {8},
pages = {836--845},
year = {1990},
url = {https://doi.org/10.1109/43.57791},
doi = {10.1109/43.57791},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuC90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangSL90,
author = {Wei{-}Kang Huang and
Yinan N. Shen and
Fabrizio Lombardi},
title = {New approaches for the repairs of memories with redundancy by row/column
deletion for yield enhancement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {3},
pages = {323--328},
year = {1990},
url = {https://doi.org/10.1109/43.46807},
doi = {10.1109/43.46807},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangSL90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HwangHLH90,
author = {Chi{-}Yi Hwang and
Yung{-}Chin Hsieh and
Youn{-}Long Lin and
Yu{-}Chin Hsu},
title = {A fast transistor-chaining algorithm for {CMOS} cell layout},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {7},
pages = {781--786},
year = {1990},
url = {https://doi.org/10.1109/43.55207},
doi = {10.1109/43.55207},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HwangHLH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HwangOI90,
author = {TingTing Hwang and
Robert Michael Owens and
Mary Jane Irwin},
title = {Exploiting communication complexity for multilevel logic synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {10},
pages = {1017--1027},
year = {1990},
url = {https://doi.org/10.1109/43.62729},
doi = {10.1109/43.62729},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HwangOI90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IshiuraIY90,
author = {Nagisa Ishiura and
Masayuki Ito and
Shuzo Yajima},
title = {Dynamic two-dimensional parallel simulation technique for high-speed
fault simulation on a vector processor},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {8},
pages = {868--875},
year = {1990},
url = {https://doi.org/10.1109/43.57785},
doi = {10.1109/43.57785},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IshiuraIY90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IsmailA90,
author = {Razali Ismail and
Gehan A. J. Amaratunga},
title = {Adaptive meshing schemes for simulating dopant diffusion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {3},
pages = {276--289},
year = {1990},
url = {https://doi.org/10.1109/43.46803},
doi = {10.1109/43.46803},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IsmailA90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IwasakiA90,
author = {Kazuhiko Iwasaki and
Fumio Arakawa},
title = {An analysis of the aliasing probability of multiple-input signature
registers in the case of a 2\({}^{\mbox{m}}\)-ary symmetric channel},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {4},
pages = {427--438},
year = {1990},
url = {https://doi.org/10.1109/43.45874},
doi = {10.1109/43.45874},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IwasakiA90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IyengarRW90,
author = {Vijay S. Iyengar and
Barry K. Rosen and
John A. Waicukauski},
title = {On computing the sizes of detected delay faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {3},
pages = {299--312},
year = {1990},
url = {https://doi.org/10.1109/43.46805},
doi = {10.1109/43.46805},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IyengarRW90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JainPB90,
author = {Navneet K. Jain and
V. C. Prasad and
A. B. Bhattacharyya},
title = {Delay time sensitivity in nonlinear monotone {RC} trees},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {5},
pages = {554--560},
year = {1990},
url = {https://doi.org/10.1109/43.55176},
doi = {10.1109/43.55176},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JainPB90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Jha90,
author = {Niraj K. Jha},
title = {Strong fault-secure and strongly self-checking domino-CMOS implementations
of totally self-checking circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {3},
pages = {332--336},
year = {1990},
url = {https://doi.org/10.1109/43.46809},
doi = {10.1109/43.46809},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Jha90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Kaufmann90,
author = {Michael Kaufmann},
title = {A linear-time algorithm for routing in a convex grid},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {2},
pages = {180--184},
year = {1990},
url = {https://doi.org/10.1109/43.46784},
doi = {10.1109/43.46784},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Kaufmann90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KohSG90,
author = {Han Young Koh and
Carlo H. S{\'{e}}quin and
Paul R. Gray},
title = {{OPASYN:} a compiler for {CMOS} operational amplifiers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {2},
pages = {113--125},
year = {1990},
url = {https://doi.org/10.1109/43.46777},
doi = {10.1109/43.46777},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KohSG90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Kuo90,
author = {Yue{-}Sun Kuo},
title = {Representing large cell maps},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {11},
pages = {1238--1241},
year = {1990},
url = {https://doi.org/10.1109/43.62761},
doi = {10.1109/43.62761},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Kuo90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeS90,
author = {Sunggu Lee and
Kang G. Shin},
title = {Design for test using partial parallel scan},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {2},
pages = {203--211},
year = {1990},
url = {https://doi.org/10.1109/43.46787},
doi = {10.1109/43.46787},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Lewis90,
author = {David M. Lewis},
title = {Device model approximation using 2\({}^{\mbox{N}}\) trees},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {1},
pages = {30--38},
year = {1990},
url = {https://doi.org/10.1109/43.45854},
doi = {10.1109/43.45854},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Lewis90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiRS90,
author = {Wing Ning Li and
Sudhakar M. Reddy and
Sartaj Sahni},
title = {Long and short covering edges in combination logic circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {12},
pages = {1245--1253},
year = {1990},
url = {https://doi.org/10.1109/43.62769},
doi = {10.1109/43.62769},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiRS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiS90,
author = {Wing Ning Li and
Sartaj Sahni},
title = {Pull up transistor folding},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {5},
pages = {512--521},
year = {1990},
url = {https://doi.org/10.1109/43.55181},
doi = {10.1109/43.55181},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinHT90,
author = {Youn{-}Long Lin and
Yu{-}Chin Hsu and
Fur{-}Shing Tsai},
title = {Hybrid routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {2},
pages = {151--157},
year = {1990},
url = {https://doi.org/10.1109/43.46781},
doi = {10.1109/43.46781},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinHT90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinN90,
author = {Bill Lin and
A. Richard Newton},
title = {A circuit disassembly technique for synthesizing symbolic layouts
from mask descriptions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {9},
pages = {959--969},
year = {1990},
url = {https://doi.org/10.1109/43.59072},
doi = {10.1109/43.59072},
timestamp = {Mon, 01 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinN90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LingB90,
author = {Nam Ling and
Magdy A. Bayoumi},
title = {Systolic temporal arithmetic: a new formalism for specification and
verification of systolic arrays},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {8},
pages = {804--820},
year = {1990},
url = {https://doi.org/10.1109/43.57788},
doi = {10.1109/43.57788},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LingB90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiouTL90,
author = {W. T. Liou and
Jimmy J. M. Tan and
Richard C. T. Lee},
title = {Minimum rectangular partition problem for simple rectilinear polygons},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {7},
pages = {720--733},
year = {1990},
url = {https://doi.org/10.1109/43.55205},
doi = {10.1109/43.55205},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiouTL90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LloydDPS90,
author = {Peter Lloyd and
Heinz K. Dirks and
E. James Prendergast and
Kishore Singhal},
title = {Technology {CAD} for competitive products},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {11},
pages = {1209--1216},
year = {1990},
url = {https://doi.org/10.1109/43.62758},
doi = {10.1109/43.62758},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LloydDPS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Lugli90,
author = {Paolo Lugli},
title = {The Monte Carlo method for semiconductor device and process modeling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {11},
pages = {1164--1176},
year = {1990},
url = {https://doi.org/10.1109/43.62753},
doi = {10.1109/43.62753},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Lugli90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaamariR90,
author = {Fadi Maamari and
Janusz Rajski},
title = {A method of fault simulation based on stem regions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {2},
pages = {212--220},
year = {1990},
url = {https://doi.org/10.1109/43.46788},
doi = {10.1109/43.46788},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaamariR90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaldonadoW90,
author = {Clifford D. Maldonado and
Ross A. Williams},
title = {A transient analytical model for predicting the redistribution of
injected interstitials},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {8},
pages = {846--855},
year = {1990},
url = {https://doi.org/10.1109/43.57792},
doi = {10.1109/43.57792},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaldonadoW90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaoC90,
author = {Weiwei Mao and
Michael D. Ciletti},
title = {{DYTEST:} a self-learning algorithm using dynamic testability measures
to accelerate test generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {8},
pages = {893--898},
year = {1990},
url = {https://doi.org/10.1109/43.57782},
doi = {10.1109/43.57782},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaoC90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MarpleSH90,
author = {David Marple and
Michiel Smulders and
Henk Hegen},
title = {Tailor: a layout system based on trapezoidal corner stitching},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {1},
pages = {66--90},
year = {1990},
url = {https://doi.org/10.1109/43.45858},
doi = {10.1109/43.45858},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MarpleSH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaziaszH90,
author = {Robert L. Maziasz and
John P. Hayes},
title = {Layout optimization of static {CMOS} functional cells},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {7},
pages = {708--719},
year = {1990},
url = {https://doi.org/10.1109/43.55210},
doi = {10.1109/43.55210},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaziaszH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/McFarlandK90,
author = {Michael C. McFarland and
Thaddeus J. Kowalski},
title = {Incorporating bottom-up design into hardware synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {9},
pages = {938--950},
year = {1990},
url = {https://doi.org/10.1109/43.59070},
doi = {10.1109/43.59070},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/McFarlandK90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MehlhornN90,
author = {Kurt Mehlhorn and
Stefan N{\"{a}}her},
title = {A faster compaction algorithm with automatic jog insertion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {2},
pages = {158--166},
year = {1990},
url = {https://doi.org/10.1109/43.46782},
doi = {10.1109/43.46782},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MehlhornN90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MehlhornR90,
author = {Kurt Mehlhorn and
Wolfgang R{\"{u}}lling},
title = {Compaction on the torus {[VLSI} layout]},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {4},
pages = {389--397},
year = {1990},
url = {https://doi.org/10.1109/43.45870},
doi = {10.1109/43.45870},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MehlhornR90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Molitor90,
author = {Paul Molitor},
title = {Constrained via minimization for systolic arrays},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {5},
pages = {537--542},
year = {1990},
url = {https://doi.org/10.1109/43.55183},
doi = {10.1109/43.55183},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Molitor90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MurrayH90,
author = {Brian T. Murray and
John P. Hayes},
title = {Hierarchical test generation using precomputed tests for modules},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {6},
pages = {594--603},
year = {1990},
url = {https://doi.org/10.1109/43.55189},
doi = {10.1109/43.55189},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MurrayH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NajmBYH90,
author = {Farid N. Najm and
Richard Burch and
Ping Yang and
Ibrahim N. Hajj},
title = {Probabilistic simulation for reliability analysis of {CMOS} {VLSI}
circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {4},
pages = {439--450},
year = {1990},
url = {https://doi.org/10.1109/43.45875},
doi = {10.1109/43.45875},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NajmBYH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NajmH90,
author = {Farid N. Najm and
Ibrahim N. Hajj},
title = {The complexity of fault detection in {MOS} {VLSI} circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {9},
pages = {995--1001},
year = {1990},
url = {https://doi.org/10.1109/43.59075},
doi = {10.1109/43.59075},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NajmH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NathanBA90,
author = {Arokia Nathan and
Henry Baltes and
Walter Allegretto},
title = {Review of physical models for numerical simulation of semiconductor
microsensors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {11},
pages = {1198--1208},
year = {1990},
url = {https://doi.org/10.1109/43.62757},
doi = {10.1109/43.62757},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NathanBA90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OdentCM90,
author = {Patrick Odent and
Luc J. M. Claesen and
Hugo De Man},
title = {Acceleration of relaxation-based circuit simulation using a multiprocessor
system},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {10},
pages = {1063--1072},
year = {1990},
url = {https://doi.org/10.1109/43.62732},
doi = {10.1109/43.62732},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OdentCM90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OkumuraST90,
author = {Makiko Okumura and
Tsutomu Sugawara and
Hiroshi Tanimoto},
title = {An efficient small signal frequency analysis method of nonlinear circuits
with two frequency excitations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {3},
pages = {225--235},
year = {1990},
url = {https://doi.org/10.1109/43.46798},
doi = {10.1109/43.46798},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OkumuraST90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OstermanP90,
author = {Michael D. Osterman and
Michael G. Pecht},
title = {Placement for reliability and routability of convectively cooled PWBs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {7},
pages = {734--744},
year = {1990},
url = {https://doi.org/10.1109/43.55206},
doi = {10.1109/43.55206},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OstermanP90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PapachristouP90,
author = {Christos A. Papachristou and
Anil L. Pandya},
title = {A design scheme for PLA-based control tables with reduced area and
time-delay cost},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {5},
pages = {453--472},
year = {1990},
url = {https://doi.org/10.1109/43.55178},
doi = {10.1109/43.55178},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PapachristouP90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ParkerS90,
author = {Anthony E. Parker and
David J. Skellern},
title = {An improved {FET} model for computer simulators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {5},
pages = {551--553},
year = {1990},
url = {https://doi.org/10.1109/43.55175},
doi = {10.1109/43.55175},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ParkerS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PasslackUE90,
author = {Matthias Passlack and
Manfred Uhle and
Horst Elschner},
title = {Analysis of propagation delays in high-speed {VLSI} circuits using
a distributed line model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {8},
pages = {821--826},
year = {1990},
url = {https://doi.org/10.1109/43.57789},
doi = {10.1109/43.57789},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PasslackUE90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PatilB90,
author = {Srinivas Patil and
Prithviraj Banerjee},
title = {A parallel branch and bound algorithm for test generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {3},
pages = {313--322},
year = {1990},
url = {https://doi.org/10.1109/43.46806},
doi = {10.1109/43.46806},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PatilB90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PauwW90,
author = {Wim De Pauw and
Ludo Weyten},
title = {Multiple storage adaptive multi-trees},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {3},
pages = {248--252},
year = {1990},
url = {https://doi.org/10.1109/43.46800},
doi = {10.1109/43.46800},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PauwW90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PillageR90,
author = {Lawrence T. Pillage and
Ronald A. Rohrer},
title = {Asymptotic waveform evaluation for timing analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {4},
pages = {352--366},
year = {1990},
url = {https://doi.org/10.1109/43.45867},
doi = {10.1109/43.45867},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PillageR90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RankW90,
author = {Ernst Rank and
Ulrich Weinert},
title = {A simulation system for diffusive oxidation of silicon: a two-dimensional
finite element approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {5},
pages = {543--550},
year = {1990},
url = {https://doi.org/10.1109/43.55174},
doi = {10.1109/43.55174},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RankW90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RorrisOMLPS90,
author = {E. Rorris and
R. R. O'Brien and
F. F. Morehead and
R. F. Lever and
J. P. Peng and
G. R. Srinivasan},
title = {A new approach to the simulation of the coupled point defects and
impurity diffusion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {10},
pages = {1113--1122},
year = {1990},
url = {https://doi.org/10.1109/43.62735},
doi = {10.1109/43.62735},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RorrisOMLPS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Rose90,
author = {Jonathan Rose},
title = {Parallel global routing for standard cells},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {10},
pages = {1085--1095},
year = {1990},
url = {https://doi.org/10.1109/43.62733},
doi = {10.1109/43.62733},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Rose90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RoseKW90,
author = {Jonathan Rose and
Wolfgang Klebsch and
J{\"{u}}rgen Wolf},
title = {Temperature measurement and equilibrium dynamics of simulated annealing
placements},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {3},
pages = {253--259},
year = {1990},
url = {https://doi.org/10.1109/43.46801},
doi = {10.1109/43.46801},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RoseKW90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Roussel-RagotD90,
author = {Pierre Roussel{-}Ragot and
G{\'{e}}rard Dreyfus},
title = {A problem independent parallel implementation of simulated annealing:
models and experiments},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {8},
pages = {827--835},
year = {1990},
url = {https://doi.org/10.1109/43.57790},
doi = {10.1109/43.57790},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Roussel-RagotD90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RuanVB90,
author = {Genhong Ruan and
Jir{\'{\i}} Vlach and
James A. Barby},
title = {Logic simulation with current-limited switches},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {2},
pages = {133--141},
year = {1990},
url = {https://doi.org/10.1109/43.46779},
doi = {10.1109/43.46779},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RuanVB90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SaabR90,
author = {Youssef Saab and
Vasant B. Rao},
title = {Fast effective heuristics for the graph bisectioning problem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {1},
pages = {91--98},
year = {1990},
url = {https://doi.org/10.1109/43.45859},
doi = {10.1109/43.45859},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SaabR90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SakallahYG90,
author = {Karem A. Sakallah and
Yao{-}Tsung Yen and
Steve S. Greenberg},
title = {A first-order charge conserving {MOS} capacitance model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {1},
pages = {99--108},
year = {1990},
url = {https://doi.org/10.1109/43.45860},
doi = {10.1109/43.45860},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SakallahYG90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SalehW90,
author = {Resve A. Saleh and
Jacob K. White},
title = {Accelerating relaxation algorithms for circuit simulation using waveform-Newton
and step-size refinement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {9},
pages = {951--958},
year = {1990},
url = {https://doi.org/10.1109/43.59071},
doi = {10.1109/43.59071},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SalehW90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Schroeder90,
author = {Dietmar Schroeder},
title = {Three-dimensional nonequilibrium interface conditions for electron
transport at band edge discontinuities},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {11},
pages = {1136--1140},
year = {1990},
url = {https://doi.org/10.1109/43.62750},
doi = {10.1109/43.62750},
timestamp = {Mon, 07 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Schroeder90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SerraSMM90,
author = {Micaela Serra and
Terry Slater and
Jon C. Muzio and
D. Michael Miller},
title = {The analysis of one-dimensional linear cellular automata and their
aliasing properties},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {7},
pages = {767--778},
year = {1990},
url = {https://doi.org/10.1109/43.55213},
doi = {10.1109/43.55213},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SerraSMM90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShahookarM90,
author = {Khushro Shahookar and
Pinaki Mazumder},
title = {A genetic approach to standard cell placement using meta-genetic parameter
optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {5},
pages = {500--511},
year = {1990},
url = {https://doi.org/10.1109/43.55180},
doi = {10.1109/43.55180},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShahookarM90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShawkiSE90,
author = {Tarek Shawki and
Georges Salmer and
Osman El{-}Sayed},
title = {2-D simulation of degenerate hot electron transport in MODFETs including
{DX} center trapping},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {11},
pages = {1150--1163},
year = {1990},
url = {https://doi.org/10.1109/43.62752},
doi = {10.1109/43.62752},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShawkiSE90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShererSB90,
author = {Adam D. Sherer and
Bob S. Stanojevich and
Robert J. Bowman},
title = {{SMALS:} a novel database for two-dimensional object location},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {1},
pages = {57--65},
year = {1990},
url = {https://doi.org/10.1109/43.45857},
doi = {10.1109/43.45857},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShererSB90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShinSS90,
author = {Hyunchul Shin and
Alberto L. Sangiovanni{-}Vincentelli and
Carlo H. S{\'{e}}quin},
title = {'Zone-refining' techniques for {IC} layout compaction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {2},
pages = {167--179},
year = {1990},
url = {https://doi.org/10.1109/43.46783},
doi = {10.1109/43.46783},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShinSS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SilbermanS90,
author = {Gabriel M. Silberman and
Ilan Y. Spillinger},
title = {Using functional fault simulation and the difference fault model to
estimate implementation fault coverage},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {12},
pages = {1335--1343},
year = {1990},
url = {https://doi.org/10.1109/43.62778},
doi = {10.1109/43.62778},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SilbermanS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Simoudis90,
author = {Evangelos Simoudis},
title = {Learning redesign knowledge circuit redesign},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {10},
pages = {1047--1062},
year = {1990},
url = {https://doi.org/10.1109/43.62731},
doi = {10.1109/43.62731},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Simoudis90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/StallmannHL90,
author = {Matthias F. M. Stallmann and
Thomas A. Hughes and
Wentai Liu},
title = {Unconstrained via minimization for topological multilayer routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {9},
pages = {970--980},
year = {1990},
url = {https://doi.org/10.1109/43.59073},
doi = {10.1109/43.59073},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/StallmannHL90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/StarkH90,
author = {Don Stark and
Mark Horowitz},
title = {Techniques for calculating currents and voltages in {VLSI} power supply
networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {2},
pages = {126--132},
year = {1990},
url = {https://doi.org/10.1109/43.46778},
doi = {10.1109/43.46778},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/StarkH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/StornettaHH90,
author = {W. Scott Stornetta and
Bernardo A. Huberman and
Tad Hogg},
title = {Scaling theory for fault stealing algorithms in large systolic arrays},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {3},
pages = {290--298},
year = {1990},
url = {https://doi.org/10.1109/43.46804},
doi = {10.1109/43.46804},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/StornettaHH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SwinkelsH90,
author = {Godfried M. Swinkels and
Louis J. Hafer},
title = {Schematic generation with an expert system},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {12},
pages = {1289--1306},
year = {1990},
url = {https://doi.org/10.1109/43.62774},
doi = {10.1109/43.62774},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SwinkelsH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TakanoYD90,
author = {Chiaki Takano and
Zhiping Yu and
Robert W. Dutton},
title = {A nonequilibrium one-dimensional quantum-mechanical simulation for
AlGaAs/GaAs {HEMT} structures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {11},
pages = {1217--1224},
year = {1990},
url = {https://doi.org/10.1109/43.62759},
doi = {10.1109/43.62759},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TakanoYD90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TaniguchiSH90,
author = {Kenji Taniguchi and
Yoshiaki Shibata and
Chihiro Hamaguchi},
title = {Process modeling and simulation: boundary conditions for point defect-based
impurity diffusion model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {11},
pages = {1177--1183},
year = {1990},
url = {https://doi.org/10.1109/43.62754},
doi = {10.1109/43.62754},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TaniguchiSH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ThurnerLS90,
author = {Martin Thurner and
Philipp Lindorfer and
Siegfried Selberherr},
title = {Numerical treatment of nonrectangular field-oxide for 3-D {MOSFET}
simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {11},
pages = {1189--1197},
year = {1990},
url = {https://doi.org/10.1109/43.62756},
doi = {10.1109/43.62756},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ThurnerLS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ThurnerS90,
author = {Martin Thurner and
Siegfried Selberherr},
title = {Three-dimensional effects due to the field oxide in {MOS} devices
analyzed with {MINIMOS} 5},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {8},
pages = {856--867},
year = {1990},
url = {https://doi.org/10.1109/43.57786},
doi = {10.1109/43.57786},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ThurnerS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/UshioNKKU90,
author = {Shintaro Ushio and
Kenji Nishi and
Shigeki Kuroda and
Kazuhiko Kai and
Jun Ueda},
title = {A fast three-dimensional process simulator {OPUS/3D} with access to
two-dimensional simulation results},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {7},
pages = {745--751},
year = {1990},
url = {https://doi.org/10.1109/43.55211},
doi = {10.1109/43.55211},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/UshioNKKU90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ValainisKLS90,
author = {John Valainis and
Sinan Kaptanoglu and
Erwin Liu and
Roberto Suaya},
title = {Two-dimensional {IC} layout compaction based on topological design
rule checking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {3},
pages = {260--275},
year = {1990},
url = {https://doi.org/10.1109/43.46802},
doi = {10.1109/43.46802},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ValainisKLS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VenkateswaranM90,
author = {Raja Venkateswaran and
Pinaki Mazumder},
title = {A hexagonal array machine for multilayer wire routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {10},
pages = {1096--1112},
year = {1990},
url = {https://doi.org/10.1109/43.62734},
doi = {10.1109/43.62734},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VenkateswaranM90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Vijayan90,
author = {Gopalakrishnan Vijayan},
title = {Partitioning logic on graph structures to minimize routing cost},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {12},
pages = {1326--1334},
year = {1990},
url = {https://doi.org/10.1109/43.62777},
doi = {10.1109/43.62777},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Vijayan90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VillaS90,
author = {Tiziano Villa and
Alberto L. Sangiovanni{-}Vincentelli},
title = {{NOVA:} state assignment of finite state machines for optimal two-level
logic implementation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {9},
pages = {905--924},
year = {1990},
url = {https://doi.org/10.1109/43.59068},
doi = {10.1109/43.59068},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VillaS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Wachutka90,
author = {Gerhard K. M. Wachutka},
title = {Rigorous thermodynamic treatment of heat generation and conduction
in semiconductor device modeling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {11},
pages = {1141--1149},
year = {1990},
url = {https://doi.org/10.1109/43.62751},
doi = {10.1109/43.62751},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Wachutka90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WalkerN90,
author = {Duncan M. Hank Walker and
D. S. Nydick},
title = {{DVLASIC:} catastrophic fault yield simulation in a distributed processing
environment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {6},
pages = {655--664},
year = {1990},
url = {https://doi.org/10.1109/43.55195},
doi = {10.1109/43.55195},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WalkerN90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangMH90,
author = {Taoyun Wang and
Joseph R. Mautz and
Roger F. Harrington},
title = {The excess capacitance of a microstrip via in a dielectric substrate},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {1},
pages = {48--56},
year = {1990},
url = {https://doi.org/10.1109/43.45856},
doi = {10.1109/43.45856},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangMH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Weise90,
author = {Daniel Weise},
title = {Multilevel verification of {MOS} circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {4},
pages = {341--351},
year = {1990},
url = {https://doi.org/10.1109/43.45866},
doi = {10.1109/43.45866},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Weise90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WeyC90,
author = {Chin{-}Long Wey and
Tsin{-}Yuan Chang},
title = {An efficient output phase assignment for {PLA} minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {1},
pages = {1--7},
year = {1990},
url = {https://doi.org/10.1109/43.45851},
doi = {10.1109/43.45851},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WeyC90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WilkenS90,
author = {Kent D. Wilken and
John Paul Shen},
title = {Continuous signature monitoring: low-cost concurrent detection of
processor control errors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {6},
pages = {629--641},
year = {1990},
url = {https://doi.org/10.1109/43.55193},
doi = {10.1109/43.55193},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WilkenS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WilseyD90,
author = {Philip A. Wilsey and
Subrata Dasgupta},
title = {A formal model of computer architectures for digital system design
environments},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {5},
pages = {473--486},
year = {1990},
url = {https://doi.org/10.1109/43.55179},
doi = {10.1109/43.55179},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WilseyD90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuS90,
author = {San{-}Yuan Wu and
Sartaj Sahni},
title = {Covering rectilinear polygons by rectangles},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {4},
pages = {377--388},
year = {1990},
url = {https://doi.org/10.1109/43.45869},
doi = {10.1109/43.45869},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuS90a,
author = {Chung{-}Yu Wu and
Ming{-}Chuen Shiau},
title = {Efficient physical timing models for {CMOS} AND-OR-inverter and OR-AND-inverter
gates and their applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {9},
pages = {1002--1009},
year = {1990},
url = {https://doi.org/10.1109/43.59076},
doi = {10.1109/43.59076},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuS90a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Wunderlich90,
author = {Hans{-}Joachim Wunderlich},
title = {Multiple distributions for biased random test patterns},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {6},
pages = {584--593},
year = {1990},
url = {https://doi.org/10.1109/43.55187},
doi = {10.1109/43.55187},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Wunderlich90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YamamuraH90,
author = {Kiyotaka Yamamura and
Kazuo Horiuchi},
title = {A globally and quadratically convergent algorithm for solving nonlinear
resistive networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {5},
pages = {487--499},
year = {1990},
url = {https://doi.org/10.1109/43.55173},
doi = {10.1109/43.55173},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YamamuraH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YericTB90,
author = {Gregory Munson Yeric and
A. F. Tasch Jr. and
Sanjay K. Banerjee},
title = {A universal {MOSFET} mobility degradation model for circuit simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {10},
pages = {1123--1126},
year = {1990},
url = {https://doi.org/10.1109/43.62736},
doi = {10.1109/43.62736},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YericTB90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YihM90,
author = {Jih{-}Shyr Yih and
Pinaki Mazumder},
title = {A neural network design for circuit partitioning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {12},
pages = {1265--1271},
year = {1990},
url = {https://doi.org/10.1109/43.62771},
doi = {10.1109/43.62771},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YihM90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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