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@article{DBLP:journals/tcad/0001Z14,
author = {Hao Zheng and
Yingying Zhang},
title = {Local State Space Analysis Leads to Better Partial Order Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {6},
pages = {839--852},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2301671},
doi = {10.1109/TCAD.2014.2301671},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/0001Z14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AgrawalRC14,
author = {Mukesh Agrawal and
Michael Richter and
Krishnendu Chakrabarty},
title = {Test-Delivery Optimization in Manycore SOCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {7},
pages = {1067--1080},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2311394},
doi = {10.1109/TCAD.2014.2311394},
timestamp = {Thu, 09 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/AgrawalRC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AmrouchEH14,
author = {Hussam Amrouch and
Thomas Ebi and
J{\"{o}}rg Henkel},
title = {{RESI:} Register-Embedded Self-Immunity for Reliability Enhancement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {5},
pages = {677--690},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2295799},
doi = {10.1109/TCAD.2013.2295799},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AmrouchEH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AmyMM14,
author = {Matthew Amy and
Dmitri Maslov and
Michele Mosca},
title = {Polynomial-Time T-Depth Optimization of Clifford+T Circuits Via Matroid
Partitioning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {10},
pages = {1476--1489},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2341953},
doi = {10.1109/TCAD.2014.2341953},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/AmyMM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BandaliGB14,
author = {Bardia Bandali and
Emad Gad and
Miodrag Bolic},
title = {Accelerated Harmonic-Balance Analysis Using a Graphical Processing
Unit Platform},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {7},
pages = {1017--1030},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2304696},
doi = {10.1109/TCAD.2014.2304696},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BandaliGB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BanerjeeKSM14,
author = {Kunal Banerjee and
Chandan Karfa and
Dipankar Sarkar and
Chittaranjan A. Mandal},
title = {Verification of Code Motion Techniques Using Value Propagation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {8},
pages = {1180--1193},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2314392},
doi = {10.1109/TCAD.2014.2314392},
timestamp = {Mon, 08 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/BanerjeeKSM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BanerjeeSM14,
author = {Kunal Banerjee and
Dipankar Sarkar and
Chittaranjan A. Mandal},
title = {Extending the {FSMD} Framework for Validating Code Motions of Array-Handling
Programs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {2015--2019},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2354298},
doi = {10.1109/TCAD.2014.2354298},
timestamp = {Mon, 08 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/BanerjeeSM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BernardeschiCDS14,
author = {Cinzia Bernardeschi and
Luca Cassano and
Andrea Domenici and
Luca Sterpone},
title = {{ASSESS:} {A} Simulator of Soft Errors in the Configuration Memory
of SRAM-Based FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {9},
pages = {1342--1355},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2329419},
doi = {10.1109/TCAD.2014.2329419},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BernardeschiCDS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BrachtendorfMFLL14,
author = {Hans Georg Brachtendorf and
Robert C. Melville and
Peter Feldmann and
Siegmar Lampe and
Rainer Laur},
title = {Homotopy Method for Finding the Steady States of Oscillators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {6},
pages = {867--878},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2302637},
doi = {10.1109/TCAD.2014.2302637},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BrachtendorfMFLL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CalimeraLMP14,
author = {Andrea Calimera and
Mirko Loghi and
Enrico Macii and
Massimo Poncino},
title = {Dynamic Indexing: Leakage-Aging Co-Optimization for Caches},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {2},
pages = {251--264},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2287187},
doi = {10.1109/TCAD.2013.2287187},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CalimeraLMP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CaoVSCAEBF14,
author = {Yu Cao and
Jyothi Velamala and
Ketul Sutaria and
Mike Shuo{-}Wei Chen and
Jonathan Ahlbin and
Ivan Sanchez Esqueda and
Michael Bajura and
Michael Fritze},
title = {Cross-Layer Modeling and Simulation of Circuit Reliability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {1},
pages = {8--23},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2289874},
doi = {10.1109/TCAD.2013.2289874},
timestamp = {Thu, 15 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CaoVSCAEBF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangHLW14,
author = {En{-}Jui Chang and
Hsien{-}Kai Hsin and
Shu{-}Yen Lin and
An{-}Yeu Wu},
title = {Path-Congestion-Aware Adaptive Routing With a Contention Prediction
Scheme for Network-on-Chip Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {1},
pages = {113--126},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2282262},
doi = {10.1109/TCAD.2013.2282262},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChangHLW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangLCLSY14,
author = {Da{-}Wei Chang and
Ing{-}Chao Lin and
Yu{-}Shiang Chien and
Ching{-}Lun Lin and
Alvin W. Y. Su and
Chung{-}Ping Young},
title = {{CASA:} Contention-Aware Scratchpad Memory Allocation for Online Hybrid
On-Chip Memory Management},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1806--1817},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2363385},
doi = {10.1109/TCAD.2014.2363385},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangLCLSY14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangZ14,
author = {Chip{-}Hong Chang and
Li Zhang},
title = {A Blind Dynamic Fingerprinting Technique for Sequential Circuit Intellectual
Property Protection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {1},
pages = {76--89},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2282282},
doi = {10.1109/TCAD.2013.2282282},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenGLSC14,
author = {Yu{-}Guang Chen and
Hui Geng and
Kuan{-}Yu Lai and
Yiyu Shi and
Shih{-}Chieh Chang},
title = {Multibit Retention Registers for Power Gated Designs: Concept, Design,
and Deployment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {507--518},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2293881},
doi = {10.1109/TCAD.2013.2293881},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChenGLSC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenHCLD14,
author = {Weiwei Chen and
Xu Han and
Che{-}Wei Chang and
Guantao Liu and
Rainer D{\"{o}}mer},
title = {Out-of-Order Parallel Discrete Event Simulation for Transaction Level
Models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1859--1872},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2356469},
doi = {10.1109/TCAD.2014.2356469},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenHCLD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenWLL14,
author = {Yen{-}Lung Chen and
Wan{-}Rong Wu and
Chien{-}Nan Jimmy Liu and
James Chien{-}Mo Li},
title = {Simultaneous Optimization of Analog Circuits With Reliability and
Variability for Applications on Flexible Electronics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {1},
pages = {24--35},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2282757},
doi = {10.1109/TCAD.2013.2282757},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenWLL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengG14,
author = {Da Cheng and
Sandeep K. Gupta},
title = {Maximizing Yield per Area of Highly Parallel CMPs Using Hardware Redundancy},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {10},
pages = {1545--1558},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2334298},
doi = {10.1109/TCAD.2014.2334298},
timestamp = {Fri, 22 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChengG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChungKY14,
author = {Jaeyong Chung and
Yonghyun Kim and
Joon{-}Sung Yang},
title = {3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {2005--2009},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2361629},
doi = {10.1109/TCAD.2014.2361629},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChungKY14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CondratKB14,
author = {Christopher Condrat and
Priyank Kalla and
Steve Blair},
title = {Crossing-Aware Channel Routing for Integrated Optics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {6},
pages = {814--825},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2317575},
doi = {10.1109/TCAD.2014.2317575},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CondratKB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CortadellaPGM14,
author = {Jordi Cortadella and
Jordi Petit and
Sergio G{\'{o}}mez and
Francesc Moll},
title = {A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {3},
pages = {409--422},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2292514},
doi = {10.1109/TCAD.2013.2292514},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CortadellaPGM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DasguptaSM14,
author = {Pallab Dasgupta and
Mandayam K. Srivas and
Rajdeep Mukherjee},
title = {Formal Hardware/Software Co-Verification of Embedded Power Controllers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {2025--2029},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2354297},
doi = {10.1109/TCAD.2014.2354297},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DasguptaSM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DeutschC14,
author = {Sergej Deutsch and
Krishnendu Chakrabarty},
title = {Contactless Pre-Bond {TSV} Test and Diagnosis Using Ring Oscillators
and Multiple Voltage Levels},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {5},
pages = {774--785},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2298198},
doi = {10.1109/TCAD.2014.2298198},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/DeutschC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DimouBL14,
author = {Georgios D. Dimou and
Peter A. Beerel and
Andrew Lines},
title = {Performance-Driven Clustering of Asynchronous Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {2},
pages = {197--209},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2287189},
doi = {10.1109/TCAD.2013.2287189},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DimouBL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EldibW14,
author = {Hassan Eldib and
Chao Wang},
title = {An {SMT} Based Method for Optimizing Arithmetic Computations in Embedded
Software Code},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {11},
pages = {1611--1622},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2341931},
doi = {10.1109/TCAD.2014.2341931},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EldibW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FangCC14,
author = {Shao{-}Yun Fang and
Yao{-}Wen Chang and
Wei{-}Yu Chen},
title = {A Novel Layout Decomposition Algorithm for Triple Patterning Lithography},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {3},
pages = {397--408},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2288678},
doi = {10.1109/TCAD.2013.2288678},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FangCC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FinderSF14,
author = {Alexander Finder and
Andr{\'{e}} S{\"{u}}lflow and
G{\"{o}}rschwin Fey},
title = {Latency Analysis for Sequential Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {643--647},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2292501},
doi = {10.1109/TCAD.2013.2292501},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FinderSF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FlachRPJR14,
author = {Guilherme Flach and
Tiago Reimann and
Gracieli Posser and
Marcelo O. Johann and
Ricardo Reis},
title = {Effective Method for Simultaneous Gate Sizing and {\textdollar}V{\textdollar}
th Assignment Using Lagrangian Relaxation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {546--557},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2305847},
doi = {10.1109/TCAD.2014.2305847},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FlachRPJR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ForoozannejadHMBG14,
author = {Mohammad H. Foroozannejad and
Matin Hashemi and
Alireza Mahini and
Bevan M. Baas and
Soheil Ghiasi},
title = {Time-Scalable Mapping for Circuit-Switched {GALS} Chip Multiprocessor
Platforms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {5},
pages = {752--762},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2299958},
doi = {10.1109/TCAD.2014.2299958},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ForoozannejadHMBG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ForoutanSP14,
author = {Sahar Foroutan and
Abbas Sheibanyrad and
Fr{\'{e}}d{\'{e}}ric P{\'{e}}trot},
title = {Assignment of Vertical-Links to Routers in Vertically-Partially-Connected
3-D-NoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {8},
pages = {1208--1218},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2323219},
doi = {10.1109/TCAD.2014.2323219},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ForoutanSP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GangeHNS14,
author = {Graeme Gange and
Benjamin Horsfall and
Lee Naish and
Harald S{\o}ndergaard},
title = {Four-Valued Reasoning and Cyclic Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {7},
pages = {1003--1016},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2304176},
doi = {10.1109/TCAD.2014.2304176},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GangeHNS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Gonzalez-EchevarriaCRFSVL14,
author = {Reinier Gonzalez{-}Echevarria and
Rafael Castro{-}L{\'{o}}pez and
Elisenda Roca and
Francisco V. Fern{\'{a}}ndez and
Javier J. Sieiro and
Neus Vidal and
Jos{\'{e}} Mar{\'{\i}}a L{\'{o}}pez{-}Villegas},
title = {Automated Generation of the Optimal Performance Trade-Offs of Integrated
Inductors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {8},
pages = {1269--1273},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2316092},
doi = {10.1109/TCAD.2014.2316092},
timestamp = {Thu, 15 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Gonzalez-EchevarriaCRFSVL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GrissomB14,
author = {Daniel T. Grissom and
Philip Brisk},
title = {Fast Online Synthesis of Digital Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {3},
pages = {356--369},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2290582},
doi = {10.1109/TCAD.2013.2290582},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GrissomB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GrissomMB14,
author = {Daniel T. Grissom and
Jeffrey McDaniel and
Philip Brisk},
title = {A Low-Cost Field-Programmable Pin-Constrained Digital Microfluidic
Biochip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {11},
pages = {1657--1670},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2347931},
doi = {10.1109/TCAD.2014.2347931},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GrissomMB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuZL14,
author = {Chenjie Gu and
Manzil Zaheer and
Xin Li},
title = {Multiple-Population Moment Estimation: Exploiting Interpopulation
Correlation for Efficient Moment Estimation in Analog/Mixed-Signal
Validation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {7},
pages = {961--974},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2304929},
doi = {10.1109/TCAD.2014.2304929},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuZL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuoCCWCHC14,
author = {Qi Guo and
Tianshi Chen and
Yunji Chen and
Rui Wang and
Huanhuan Chen and
Weiwu Hu and
Guoliang Chen},
title = {Pre-Silicon Bug Forecast},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {3},
pages = {451--463},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2288688},
doi = {10.1109/TCAD.2013.2288688},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuoCCWCHC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HapkeRGRRHKSF14,
author = {Friedrich Hapke and
Wilfried Redemund and
Andreas Glowatz and
Janusz Rajski and
Michael Reese and
Marek Hustava and
Martin Keim and
Juergen Schloeffel and
Anja Fast},
title = {Cell-Aware Test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {9},
pages = {1396--1409},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2323216},
doi = {10.1109/TCAD.2014.2323216},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HapkeRGRRHKSF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HoLLCCLS14,
author = {Yuan{-}Kai Ho and
Hsu{-}Chieh Lee and
Webber Lee and
Yao{-}Wen Chang and
Chen{-}Feng Chang and
I{-}Jye Lin and
Chin{-}Fang Shen},
title = {Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {2},
pages = {224--236},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2285275},
doi = {10.1109/TCAD.2013.2285275},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HoLLCCLS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HolcombS14,
author = {Daniel E. Holcomb and
Sanjit A. Seshia},
title = {Compositional Performance Verification of Network-on-Chip Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {9},
pages = {1370--1383},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2331342},
doi = {10.1109/TCAD.2014.2331342},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HolcombS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HouLF14,
author = {Chih{-}Sheng Hou and
Jin{-}Fu Li and
Ting{-}Jun Fu},
title = {A {BIST} Scheme With the Ability of Diagnostic Data Compression for
RAMs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {2020--2024},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2363393},
doi = {10.1109/TCAD.2014.2363393},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HouLF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsiehHC14,
author = {Yi{-}Ling Hsieh and
Tsung{-}Yi Ho and
Krishnendu Chakrabarty},
title = {Biochip Synthesis and Dynamic Error Recovery for Sample Preparation
Using Digital Microfluidics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {2},
pages = {183--196},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2284010},
doi = {10.1109/TCAD.2013.2284010},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HsiehHC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsinCLW14,
author = {Hsien{-}Kai Hsin and
En{-}Jui Chang and
Chia{-}An Lin and
An{-}Yeu Andy Wu},
title = {Ant Colony Optimization-Based Fault-Aware Routing in Mesh-Based Network-on-Chip
Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {11},
pages = {1693--1705},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2347922},
doi = {10.1109/TCAD.2014.2347922},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HsinCLW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsuCH14,
author = {Po{-}Yang Hsu and
Hsien{-}Te Chen and
TingTing Hwang},
title = {Stacking Signal {TSV} for Thermal Dissipation in Global Routing for
3-D {IC}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {7},
pages = {1031--1042},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2307488},
doi = {10.1109/TCAD.2014.2307488},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsuCH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsuCHCLCC14,
author = {Meng{-}Kai Hsu and
Yi{-}Fang Chen and
Chau{-}Chin Huang and
Sheng Chou and
Tzu{-}Hen Lin and
Tung{-}Chieh Chen and
Yao{-}Wen Chang},
title = {NTUplace4h: {A} Novel Routability-Driven Placement Algorithm for Hierarchical
Mixed-Size Circuit Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1914--1927},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2360453},
doi = {10.1109/TCAD.2014.2360453},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsuCHCLCC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuYHC14,
author = {Kai Hu and
Feiqiao Yu and
Tsung{-}Yi Ho and
Krishnendu Chakrabarty},
title = {Testing of Flow-Based Microfluidic Biochips: Fault Modeling, Test
Generation, and Experimental Demonstration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {10},
pages = {1463--1475},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2336215},
doi = {10.1109/TCAD.2014.2336215},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuYHC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangHTC14,
author = {Li{-}Ren Huang and
Shi{-}Yu Huang and
Kun{-}Han Tsai and
Wu{-}Tung Cheng},
title = {Parametric Fault Testing and Performance Characterization of Post-Bond
Interposer Wires in 2.5-D ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {3},
pages = {476--488},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2290589},
doi = {10.1109/TCAD.2013.2290589},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangHTC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangLTC14,
author = {Shi{-}Yu Huang and
Jeo{-}Yen Lee and
Kun{-}Han Tsai and
Wu{-}Tung Cheng},
title = {Pulse-Vanishing Test for Interposers Wires in 2.5-D {IC}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {8},
pages = {1258--1268},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2316093},
doi = {10.1109/TCAD.2014.2316093},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangLTC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Jang14,
author = {Wooyoung Jang},
title = {Error-Correcting Code Aware Memory Subsystem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {11},
pages = {1706--1717},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2351494},
doi = {10.1109/TCAD.2014.2351494},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Jang14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JanickiKMMRT14,
author = {Jakub Janicki and
Mark Kassab and
Grzegorz Mrugalski and
Nilanjan Mukherjee and
Janusz Rajski and
Jerzy Tyszer},
title = {Erratum to "Test Time Reduction in {EDT} Bandwidth Management for
SoC Designs"},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {1},
pages = {167},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2292631},
doi = {10.1109/TCAD.2013.2292631},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JanickiKMMRT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JavaidSHP14,
author = {Haris Javaid and
Muhammad Shafique and
J{\"{o}}rg Henkel and
Sri Parameswaran},
title = {Energy-Efficient Adaptive Pipelined MPSoCs for Multimedia Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {5},
pages = {663--676},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2298196},
doi = {10.1109/TCAD.2014.2298196},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/JavaidSHP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JooK14,
author = {Deokjin Joo and
Taewhan Kim},
title = {A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and
Low-Power Digital Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {3},
pages = {423--436},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2288698},
doi = {10.1109/TCAD.2013.2288698},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JooK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JungLK14,
author = {Seobin Jung and
Jiho Lee and
Jaeha Kim},
title = {Variability-Aware, Discrete Optimization for Analog Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {8},
pages = {1117--1130},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2313452},
doi = {10.1109/TCAD.2014.2313452},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JungLK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JungLK14a,
author = {Seobin Jung and
Jiho Lee and
Jaeha Kim},
title = {Yield-Aware Pareto Front Extraction for Discrete Hierarchical Optimization
of Analog Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {10},
pages = {1437--1449},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2331563},
doi = {10.1109/TCAD.2014.2331563},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JungLK14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KanounMAS14,
author = {Karim Kanoun and
Nicholas Mastronarde and
David Atienza and
Mihaela van der Schaar},
title = {Online Energy-Efficient Task-Graph Scheduling for Multicore Platforms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {8},
pages = {1194--1207},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2316094},
doi = {10.1109/TCAD.2014.2316094},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KanounMAS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KarmarkarT14,
author = {Kedar Karmarkar and
Spyros Tragoudas},
title = {On-Chip Codeword Generation to Cope With Crosstalk},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {2},
pages = {237--250},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2284017},
doi = {10.1109/TCAD.2013.2284017},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KarmarkarT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimML14,
author = {Daehyun Kim and
Saibal Mukhopadhyay and
Sung Kyu Lim},
title = {TSV-Aware Interconnect Distribution Models for Prediction of Delay
and Power Consumption of 3-D Stacked ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {9},
pages = {1384--1395},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2329472},
doi = {10.1109/TCAD.2014.2329472},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimML14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KohS14,
author = {Cheng{-}Kok Koh and
Chin Ngai Sze},
title = {Guest Editorial Special Section on Contemporary and Emerging Issues
in Physical Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {493--494},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2304991},
doi = {10.1109/TCAD.2014.2304991},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KohS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KumarAV14,
author = {Jayanand Asok Kumar and
Seyed Nematollah Ahmadyan and
Shobha Vasudevan},
title = {Efficient Statistical Model Checking of Hardware Circuits With Multiple
Failure Regions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {6},
pages = {945--958},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2299957},
doi = {10.1109/TCAD.2014.2299957},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KumarAV14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LaiCAG14,
author = {Liangzhen Lai and
Vikas Chandra and
Robert C. Aitken and
Puneet Gupta},
title = {SlackProbe: {A} Flexible and Efficient In Situ Timing Slack Monitoring
Methodology},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {8},
pages = {1168--1179},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2323195},
doi = {10.1109/TCAD.2014.2323195},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LaiCAG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LaoP14,
author = {Yingjie Lao and
Keshab K. Parhi},
title = {Statistical Analysis of MUX-Based Physical Unclonable Functions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {5},
pages = {649--662},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2296525},
doi = {10.1109/TCAD.2013.2296525},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LaoP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeKCK14,
author = {Changwook Lee and
Wooheon Kang and
Donkoo Cho and
Sungho Kang},
title = {A New Fuse Architecture and a New Post-Share Redundancy Scheme for
Yield Enhancement in 3-D-Stacked Memories},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {5},
pages = {786--797},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2296538},
doi = {10.1109/TCAD.2013.2296538},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeKCK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeS14,
author = {Jaeil Lee and
Dongkun Shin},
title = {Adaptive Paired Page Prebackup Scheme for {MLC} {NAND} Flash Memory},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {7},
pages = {1110--1114},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2309857},
doi = {10.1109/TCAD.2014.2309857},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeWSCP14,
author = {Woojoo Lee and
Yanzhi Wang and
Donghwa Shin and
Naehyuck Chang and
Massoud Pedram},
title = {Optimizing the Power Delivery Network in a Smartphone Platform},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {1},
pages = {36--49},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2282287},
doi = {10.1109/TCAD.2013.2282287},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeWSCP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LenoxT14,
author = {Joseph Lenox and
Spyros Tragoudas},
title = {Adapting an Implicit Path Delay Grading Method for Parallel Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1965--1976},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2356438},
doi = {10.1109/TCAD.2014.2356438},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LenoxT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiBGP14,
author = {Cheng Li and
Mark Browning and
Paul V. Gratz and
Samuel Palermo},
title = {LumiNOC: {A} Power-Efficient, High-Performance, Photonic Network-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {6},
pages = {826--838},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2320510},
doi = {10.1109/TCAD.2014.2320510},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiBGP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiD14,
author = {Min Li and
Azadeh Davoodi},
title = {A Hybrid Approach for Fast and Accurate Trace Signal Selection for
Post-Silicon Debug},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {7},
pages = {1081--1094},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2307533},
doi = {10.1109/TCAD.2014.2307533},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiLLL14,
author = {Yi{-}Hua Li and
Wei{-}Cheng Lien and
Ing{-}Chao Lin and
Kuen{-}Jong Lee},
title = {Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based
Testing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {1},
pages = {127--138},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2282281},
doi = {10.1109/TCAD.2013.2282281},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiLLL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiZCL14,
author = {Yongfu Li and
Zhe Zhang and
Dingjuan Chua and
Yong Lian},
title = {Placement for Binary-Weighted Capacitive Array in {SAR} {ADC} Using
Multiple Weighting Methods},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {9},
pages = {1277--1287},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2323217},
doi = {10.1109/TCAD.2014.2323217},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiZCL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinHLSKFHGM14,
author = {David Lin and
Ted Hong and
Yanjing Li and
Eswaran S and
Sharad Kumar and
Farzan Fallah and
Nagib Hakim and
Donald S. Gardner and
Subhasish Mitra},
title = {Effective Post-Silicon Validation of System-on-Chips Using Quick Error
Detection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {10},
pages = {1573--1590},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2334301},
doi = {10.1109/TCAD.2014.2334301},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinHLSKFHGM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinW14,
author = {Jai{-}Ming Lin and
Ji{-}Heng Wu},
title = {{F-FM:} Fixed-Outline Floorplanning Methodology for Mixed-Size Modules
Considering Voltage-Island Constraint},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {11},
pages = {1681--1692},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2351571},
doi = {10.1109/TCAD.2014.2351571},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuCCH14,
author = {Shih{-}Ying Sean Liu and
Chung{-}Hung Chang and
Hung{-}Ming Chen and
Tsung{-}Yi Ho},
title = {{ACER:} An Agglomerative Clustering Based Electrode Addressing and
Routing Algorithm for Pin-Constrained {EWOD} Chips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {9},
pages = {1316--1327},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2329415},
doi = {10.1109/TCAD.2014.2329415},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuCCH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuL14,
author = {Wen{-}Hao Liu and
Yih{-}Lang Li},
title = {Optimizing the Antenna Area and Separators in Layer Assignment of
Multilayer Global Routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {613--626},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2293053},
doi = {10.1109/TCAD.2013.2293053},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuLCLW14,
author = {Chih{-}Hung Liu and
Chun{-}Xun Lin and
I{-}Che Chen and
D. T. Lee and
Ting{-}Chi Wang},
title = {Efficient Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction
Based on Geometric Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1928--1941},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2363390},
doi = {10.1109/TCAD.2014.2363390},
timestamp = {Tue, 14 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuLCLW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuP14,
author = {Lechang Liu and
Ramesh K. Pokharel},
title = {Post-Layout Simulation Time Reduction for Phase-Locked Loop Frequency
Synthesizer Using System Identification Techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {11},
pages = {1751--1755},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2354291},
doi = {10.1109/TCAD.2014.2354291},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuSTCW14,
author = {Zao Liu and
Sahana Swarup and
Sheldon X.{-}D. Tan and
Hai{-}Bao Chen and
Hai Wang},
title = {Compact Lateral Thermal Resistance Model of TSVs for Fast Finite-Difference
Based Thermal Analysis of 3-D Stacked ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {10},
pages = {1490--1502},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2334321},
doi = {10.1109/TCAD.2014.2334321},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuSTCW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuW0SZS14,
author = {Duo Liu and
Tianzheng Wang and
Yi Wang and
Zili Shao and
Qingfeng Zhuge and
Edwin Hsing{-}Mean Sha},
title = {Application-Specific Wear Leveling for Extending Lifetime of Phase
Change Memory in Embedded Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {10},
pages = {1450--1462},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2341922},
doi = {10.1109/TCAD.2014.2341922},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuW0SZS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuYC14,
author = {Ying Liu and
Weizheng Yuan and
Honglong Chang},
title = {A Global Maximum Error Controller-Based Method for Linearization Point
Selection in Trajectory Piecewise-Linear Model Order Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {7},
pages = {1100--1104},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2307000},
doi = {10.1109/TCAD.2014.2307000},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuYC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuZRG14,
author = {Bo Liu and
Dixian Zhao and
Patrick Reynaert and
Georges G. E. Gielen},
title = {{GASPAD:} {A} General and Efficient mm-Wave Integrated Circuit Synthesis
Method Based on Surrogate Model Assisted Evolutionary Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {2},
pages = {169--182},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2284109},
doi = {10.1109/TCAD.2013.2284109},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuZRG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuTB14,
author = {Shiting (Justin) Lu and
Russell Tessier and
Wayne P. Burleson},
title = {Dynamic On-Chip Thermal Sensor Calibration Using Performance Counters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {6},
pages = {853--866},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2302384},
doi = {10.1109/TCAD.2014.2302384},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuTB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuoCH14,
author = {Yan Luo and
Krishnendu Chakrabarty and
Tsung{-}Yi Ho},
title = {Biochemistry Synthesis on a Cyberphysical Digital Microfluidics Platform
Under Completion-Time Uncertainties in Fluidic Operations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {6},
pages = {903--916},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2303948},
doi = {10.1109/TCAD.2014.2303948},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LuoCH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaW14,
author = {Kun Ma and
Kaijie Wu},
title = {Error Detection and Recovery for {ECC:} {A} New Approach Against Side-Channel
Attacks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {627--637},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2293058},
doi = {10.1109/TCAD.2013.2293058},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MahmoodGCCD14,
author = {Zohaib Mahmood and
Stefano Grivet{-}Talocia and
Alessandro Chinea and
Giuseppe Carlo Calafiore and
Luca Daniel},
title = {Efficient Localization Methods for Passivity Enforcement of Linear
Dynamical Models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {9},
pages = {1328--1341},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2329418},
doi = {10.1109/TCAD.2014.2329418},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MahmoodGCCD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MahmoudSF14,
author = {Mohamed Mounir Mahmoud and
Norhayati Soin and
Hossam A. H. Fahmy},
title = {Design Framework to Overcome Aging Degradation of the 16 nm {VLSI}
Technology Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {5},
pages = {691--703},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2299713},
doi = {10.1109/TCAD.2014.2299713},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MahmoudSF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MakC14,
author = {Wai{-}Kei Mak and
Chris Chu},
title = {E-Beam Lithography Character and Stencil Co-Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {5},
pages = {741--751},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2296496},
doi = {10.1109/TCAD.2013.2296496},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MakC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MalburgFF14,
author = {Jan Malburg and
Alexander Finder and
G{\"{o}}rschwin Fey},
title = {A Simulation-Based Approach for Automated Feature Localization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1886--1899},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2360462},
doi = {10.1109/TCAD.2014.2360462},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MalburgFF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MangassarianLV14,
author = {Hratch Mangassarian and
Bao Le and
Andreas G. Veneris},
title = {Debugging {RTL} Using Structural Dominance},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {1},
pages = {153--166},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2278491},
doi = {10.1109/TCAD.2013.2278491},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MangassarianLV14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MitraRBCB14,
author = {Debasis Mitra and
Sudip Roy and
Sukanta Bhattacharjee and
Krishnendu Chakrabarty and
Bhargab B. Bhattacharya},
title = {On-Chip Sample Preparation for Multiple Targets Using Digital Microfluidics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {8},
pages = {1131--1144},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2323200},
doi = {10.1109/TCAD.2014.2323200},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MitraRBCB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MorrisonR14,
author = {Matthew Morrison and
Nagarajan Ranganathan},
title = {Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {7},
pages = {975--988},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2313454},
doi = {10.1109/TCAD.2014.2313454},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MorrisonR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Narayanan14,
author = {Vijaykrishnan Narayanan},
title = {Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {1},
pages = {1},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2292271},
doi = {10.1109/TCAD.2013.2292271},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Narayanan14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NikdastXWZYWWW14,
author = {Mahdi Nikdast and
Jiang Xu and
Xiaowen Wu and
Wei Zhang and
Yaoyao Ye and
Xuan Wang and
Zhehui Wang and
Zhe Wang},
title = {Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical
Networks-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {3},
pages = {437--450},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2288676},
doi = {10.1109/TCAD.2013.2288676},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/NikdastXWZYWWW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NoiaC14,
author = {Brandon Noia and
Krishnendu Chakrabarty},
title = {Retiming for Delay Recovery After DfT Insertion on Interdie Paths
in 3-D ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {3},
pages = {464--475},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2289857},
doi = {10.1109/TCAD.2013.2289857},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/NoiaC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NowrozHKR14,
author = {Abdullah Nazma Nowroz and
Kangqiao Hu and
Farinaz Koushanfar and
Sherief Reda},
title = {Novel Techniques for High-Sensitivity Hardware Trojan Detection Using
Thermal and Power Maps},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1792--1805},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2354293},
doi = {10.1109/TCAD.2014.2354293},
timestamp = {Fri, 04 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NowrozHKR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ObergMSK14,
author = {Jason Oberg and
Sarah Meiklejohn and
Timothy Sherwood and
Ryan Kastner},
title = {Leveraging Gate-Level Properties to Identify Hardware Timing Channels},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {9},
pages = {1288--1301},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2331332},
doi = {10.1109/TCAD.2014.2331332},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ObergMSK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OborilT14,
author = {Fabian Oboril and
Mehdi Baradaran Tahoori},
title = {Aging-Aware Design of Microprocessor Instruction Pipelines},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {5},
pages = {704--716},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2298333},
doi = {10.1109/TCAD.2014.2298333},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OborilT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OuCC14,
author = {Hung{-}Chih Ou and
Hsing{-}Chih Chang Chien and
Yao{-}Wen Chang},
title = {Nonuniform Multilevel Analog Routing With Matching Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1942--1954},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2363394},
doi = {10.1109/TCAD.2014.2363394},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OuCC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OzdalH14,
author = {Muhammet Mustafa Ozdal and
Renato Fernandes Hentschke},
title = {Algorithms for Maze Routing With Exact Matching Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {1},
pages = {101--112},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2279516},
doi = {10.1109/TCAD.2013.2279516},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OzdalH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PakLP14,
author = {Jiwoo Pak and
Sung Kyu Lim and
David Z. Pan},
title = {Electromigration Study for Multiscale Power/Ground Vias in TSV-Based
3-D ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1873--1885},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2360456},
doi = {10.1109/TCAD.2014.2360456},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PakLP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ParasharMS14,
author = {Karthick Nagaraj Parashar and
Daniel M{\'{e}}nard and
Olivier Sentieys},
title = {Accelerated Performance Evaluation of Fixed-Point Systems With Un-Smooth
Operations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {599--612},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2292510},
doi = {10.1109/TCAD.2013.2292510},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ParasharMS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PellegriniB14,
author = {Andrea Pellegrini and
Valeria Bertacco},
title = {Cardio: {CMP} Adaptation for Reliability Through Dynamic Introspective
Operation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {2},
pages = {265--278},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2284008},
doi = {10.1109/TCAD.2013.2284008},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PellegriniB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PengSPL14,
author = {Yarui Peng and
Taigon Song and
Dusan Petranovic and
Sung Kyu Lim},
title = {Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV
Coupling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1900--1913},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2359578},
doi = {10.1109/TCAD.2014.2359578},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PengSPL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz14,
author = {Irith Pomeranz},
title = {Unknown Output Values of Faulty Circuits and Output Response Compaction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {2},
pages = {323--327},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2284012},
doi = {10.1109/TCAD.2013.2284012},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz14a,
author = {Irith Pomeranz},
title = {Input Test Data Volume Reduction for Skewed-Load Tests by Additional
Shifting of Scan-In States},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {638--642},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2290085},
doi = {10.1109/TCAD.2013.2290085},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz14b,
author = {Irith Pomeranz},
title = {Selection of Functional Test Sequences With Overlaps},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {7},
pages = {1095--1099},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2293473},
doi = {10.1109/TCAD.2013.2293473},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz14b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz14c,
author = {Irith Pomeranz},
title = {Simultaneous Generation of Functional and Low-Power Non-Functional
Broadside Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {8},
pages = {1245--1257},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2314293},
doi = {10.1109/TCAD.2014.2314293},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz14c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz14d,
author = {Irith Pomeranz},
title = {Functional Broadside Tests for Multistep Defect Diagnosis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {9},
pages = {1429--1433},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2331559},
doi = {10.1109/TCAD.2014.2331559},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz14d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz14e,
author = {Irith Pomeranz},
title = {Static Test Compaction for Scan Circuits by Using Restoration to Modify
and Remove Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1955--1964},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2358932},
doi = {10.1109/TCAD.2014.2358932},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz14e.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz14f,
author = {Irith Pomeranz},
title = {Improving the Accuracy of Defect Diagnosis by Considering Fewer Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {2010--2014},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2358936},
doi = {10.1109/TCAD.2014.2358936},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz14f.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/QiuMM14,
author = {Xiang Qiu and
Malgorzata Marek{-}Sadowska and
Wojciech P. Maly},
title = {Characterizing VeSFET-Based ICs With CMOS-Oriented {EDA} Infrastructure},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {495--506},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2293539},
doi = {10.1109/TCAD.2013.2293539},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/QiuMM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/QiuZLFX14,
author = {Keni Qiu and
Mengying Zhao and
Qing'an Li and
Chenchen Fu and
Chun Jason Xue},
title = {Migration-Aware Loop Retiming for STT-RAM-Based Hybrid Cache in Embedded
Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {3},
pages = {329--342},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2288692},
doi = {10.1109/TCAD.2013.2288692},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/QiuZLFX14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RakaiFWB14,
author = {Logan M. Rakai and
Amin Farshidi and
David T. Westwick and
Laleh Behjat},
title = {Variation-Aware Geometric Programming Models for the Clock Network
Buffer Sizing Problem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {532--545},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2293067},
doi = {10.1109/TCAD.2013.2293067},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RakaiFWB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RamprasathV14,
author = {S. Ramprasath and
Vinita Vasudevan},
title = {Statistical Criticality Computation Using the Circuit Delay},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {5},
pages = {717--727},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2296436},
doi = {10.1109/TCAD.2013.2296436},
timestamp = {Tue, 05 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/RamprasathV14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RehmanKSH14,
author = {Semeen Rehman and
Florian Kriebel and
Muhammad Shafique and
J{\"{o}}rg Henkel},
title = {Reliability-Driven Software Transformations for Unreliable Hardware},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {11},
pages = {1597--1610},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2341894},
doi = {10.1109/TCAD.2014.2341894},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/RehmanKSH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RoyCPP14,
author = {Subhendu Roy and
Mihir R. Choudhury and
Ruchir Puri and
David Z. Pan},
title = {Towards Optimal Performance-Area Trade-Off in Adders by Synthesis
of Parallel Prefix Structures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {10},
pages = {1517--1530},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2341926},
doi = {10.1109/TCAD.2014.2341926},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RoyCPP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SarmadiKR14,
author = {Siavash Bayat Sarmadi and
Mehran Mozaffari Kermani and
Arash Reyhani{-}Masoleh},
title = {Efficient and Concurrent Reliable Realization of the Secure Cryptographic
{SHA-3} Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {7},
pages = {1105--1109},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2307002},
doi = {10.1109/TCAD.2014.2307002},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SarmadiKR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SavojMB14,
author = {Hamid Savoj and
Alan Mishchenko and
Robert K. Brayton},
title = {Sequential Equivalence Checking for Clock-Gated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {2},
pages = {305--317},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2284190},
doi = {10.1109/TCAD.2013.2284190},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SavojMB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SchoenmakerCG14,
author = {Wim Schoenmaker and
Quan Chen and
Philippe Galy},
title = {Computation of Self-Induced Magnetic Field Effects Including the Lorentz
Force for Fast-Transient Phenomena in Integrated-Circuit Devices},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {6},
pages = {893--902},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2303050},
doi = {10.1109/TCAD.2014.2303050},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SchoenmakerCG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SenNDC14,
author = {Shreyas Sen and
Vishwanath Natarajan and
Shyam Kumar Devarakond and
Abhijit Chatterjee},
title = {Process-Variation Tolerant Channel-Adaptive Virtually Zero-Margin
Low-Power Wireless Receiver Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1764--1777},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2358535},
doi = {10.1109/TCAD.2014.2358535},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SenNDC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShafiqueBH14,
author = {Muhammad Shafique and
Lars Bauer and
J{\"{o}}rg Henkel},
title = {Adaptive Energy Management for Dynamically Reconfigurable Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {1},
pages = {50--63},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2282265},
doi = {10.1109/TCAD.2013.2282265},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ShafiqueBH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShiQZX14,
author = {Liang Shi and
Keni Qiu and
Mengying Zhao and
Chun Jason Xue},
title = {Error Model Guided Joint Performance and Endurance Optimization for
Flash Memory},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {3},
pages = {343--355},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2288691},
doi = {10.1109/TCAD.2013.2288691},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShiQZX14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShiS14,
author = {Bing Shi and
Ankur Srivastava},
title = {Optimized Micro-Channel Design for Stacked 3-D-ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {1},
pages = {90--100},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2279514},
doi = {10.1109/TCAD.2013.2279514},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ShiS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShihLYLKLSW14,
author = {Hsiu{-}Chuan Shih and
Pei{-}Wen Luo and
Jen{-}Chieh Yeh and
Shu{-}Yen Lin and
Ding{-}Ming Kwai and
Shih{-}Lien Lu and
Andre Schaefer and
Cheng{-}Wen Wu},
title = {DArT: {A} Component-Based {DRAM} Area, Power, and Timing Modeling
Tool},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {9},
pages = {1356--1369},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2323203},
doi = {10.1109/TCAD.2014.2323203},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShihLYLKLSW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShintaniUTHAMS14,
author = {Michihiro Shintani and
Takumi Uezono and
Tomoyuki Takahashi and
Kazumi Hatayama and
Takashi Aikyo and
Kazuya Masu and
Takashi Sato},
title = {A Variability-Aware Adaptive Test Flow for Test Quality Improvement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {7},
pages = {1056--1066},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2305835},
doi = {10.1109/TCAD.2014.2305835},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShintaniUTHAMS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinghHCO14,
author = {Ashish Kumar Singh and
Ku He and
Constantine Caramanis and
Michael Orshansky},
title = {Modeling and Optimization Techniques for Yield-Aware {SRAM} Post-Silicon
Tuning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {8},
pages = {1159--1167},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2317571},
doi = {10.1109/TCAD.2014.2317571},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinghHCO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SongYD14,
author = {Yang Song and
Hao Yu and
Sai Manoj Pudukotai Dinakarrao},
title = {Reachability-Based Robustness Verification and Optimization of {SRAM}
Dynamic Stability Under Process Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {585--598},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2304704},
doi = {10.1109/TCAD.2014.2304704},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SongYD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SridharSA14,
author = {Arvind Sridhar and
Mohamed M. Sabry and
David Atienza},
title = {A Semi-Analytical Thermal Modeling Framework for Liquid-Cooled ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {8},
pages = {1145--1158},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2323194},
doi = {10.1109/TCAD.2014.2323194},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SridharSA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/StratigopoulosS14,
author = {Haralampos{-}G. D. Stratigopoulos and
Stephen Sunter},
title = {Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1977--1990},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2360458},
doi = {10.1109/TCAD.2014.2360458},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/StratigopoulosS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SuR14,
author = {Yehua Su and
Wenjing Rao},
title = {An Integrated Framework Toward Defect-Tolerant Logic Implementation
Onto Nanocrossbars},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {1},
pages = {64--75},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2282755},
doi = {10.1109/TCAD.2013.2282755},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SuR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TamB14,
author = {Wing Chiu Tam and
R. D. (Shawn) Blanton},
title = {Design-for-Manufacturability Assessment for Integrated Circuits Using
{RADAR}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {10},
pages = {1559--1572},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2336216},
doi = {10.1109/TCAD.2014.2336216},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TamB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TangRZBM14,
author = {Qin Tang and
Javier Rodr{\'{\i}}guez and
Amir Zjajo and
Michel Berkelaar and
Nick van der Meijs},
title = {Statistical Transistor-Level Timing Analysis Using a Direct Random
Differential Equation Solver},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {2},
pages = {210--223},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2287179},
doi = {10.1109/TCAD.2013.2287179},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TangRZBM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TangZBM14,
author = {Qin Tang and
Amir Zjajo and
Michel Berkelaar and
Nick van der Meijs},
title = {Considering Crosstalk Effects in Statistical Timing Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {2},
pages = {318--322},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2279515},
doi = {10.1109/TCAD.2013.2279515},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TangZBM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TheodorouKPG14,
author = {Georgios Theodorou and
Nektarios Kranitis and
Antonis M. Paschalis and
Dimitris Gizopoulos},
title = {Software-Based Self-Test for Small Caches in Microprocessors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1991--2004},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2363387},
doi = {10.1109/TCAD.2014.2363387},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/TheodorouKPG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TodorovMRS14,
author = {Vladimir Todorov and
Daniel Mueller{-}Gritschneder and
Helmut Reinig and
Ulf Schlichtmann},
title = {Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip
Topologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {10},
pages = {1503--1516},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2331556},
doi = {10.1109/TCAD.2014.2331556},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TodorovMRS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Topaloglu14,
author = {Rasit Onur Topaloglu},
title = {Guest Editorial Special Section on Optical Interconnects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {6},
pages = {813},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2321020},
doi = {10.1109/TCAD.2014.2321020},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Topaloglu14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/UkhovEP14,
author = {Ivan Ukhov and
Petru Eles and
Zebo Peng},
title = {Probabilistic Analysis of Power and Temperature Under Process Variation
for Electronic System Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {6},
pages = {931--944},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2301672},
doi = {10.1109/TCAD.2014.2301672},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/UkhovEP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/UmbarkarSD14,
author = {Anurag Umbarkar and
Varun Subramanian and
Alex Doboli},
title = {Linear Programming-Based Optimization for Robust Data Modeling in
a Distributed Sensing Platform},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {10},
pages = {1531--1544},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2334295},
doi = {10.1109/TCAD.2014.2334295},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/UmbarkarSD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/UrdahlSK14,
author = {Joakim Urdahl and
Dominik Stoffel and
Wolfgang Kunz},
title = {Path Predicate Abstraction for Sound System-Level Models of RT-Level
Circuit Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {2},
pages = {291--304},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2285276},
doi = {10.1109/TCAD.2013.2285276},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/UrdahlSK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VansteenkisteFBS14,
author = {Elias Vansteenkiste and
Brahim Al Farisi and
Karel Bruneel and
Dirk Stroobandt},
title = {TPaR: Place and Route Tools for the Dynamic Reconfiguration of the
FPGA's Interconnect Network},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {3},
pages = {370--383},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2291659},
doi = {10.1109/TCAD.2013.2291659},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VansteenkisteFBS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Voyiatzis14,
author = {Ioannis Voyiatzis},
title = {Aliasing Reduction in Accumulator-Based Response Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {11},
pages = {1746--1750},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2351582},
doi = {10.1109/TCAD.2014.2351582},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Voyiatzis14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangCE14,
author = {Ran Wang and
Krishnendu Chakrabarty and
Bill Eklow},
title = {Scan-Based Testing of Post-Bond Silicon Interposer Interconnects in
2.5-D ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {9},
pages = {1410--1423},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2331336},
doi = {10.1109/TCAD.2014.2331336},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WangCE14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangDWCL14,
author = {Kan Wang and
Sheqin Dong and
Huaxi Wang and
Qian Chen and
Tao Lin},
title = {Mixed-Crossing-Avoided Escape Routing of Mixed-Pattern Signals on
Staggered-Pin-Array PCBs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {571--584},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2301676},
doi = {10.1109/TCAD.2014.2301676},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangDWCL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangHSCBD14,
author = {Yi Wang and
Min Huang and
Zili Shao and
Henry C. B. Chan and
Luis Angel D. Bathen and
Nikil D. Dutt},
title = {A Reliability-Aware Address Mapping Strategy for {NAND} Flash Memory
Storage Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {11},
pages = {1623--1631},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2347929},
doi = {10.1109/TCAD.2014.2347929},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangHSCBD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangLKCP14,
author = {Yanzhi Wang and
Xue Lin and
Younghyun Kim and
Naehyuck Chang and
Massoud Pedram},
title = {Architecture and Control Algorithms for Combating Partial Shading
in Photovoltaic Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {6},
pages = {917--930},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2302383},
doi = {10.1109/TCAD.2014.2302383},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangLKCP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangZKTC14,
author = {Ran Wang and
Zhaobo Zhang and
Xrysovalantis Kavousianos and
Yiorgos Tsiatouhas and
Krishnendu Chakrabarty},
title = {Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {8},
pages = {1231--1244},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2314303},
doi = {10.1109/TCAD.2014.2314303},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WangZKTC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangZXS14,
author = {Tao Wang and
Chun Zhang and
Jinjun Xiong and
Yiyu Shi},
title = {On the Deployment of On-Chip Noise Sensors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {519--531},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2293477},
doi = {10.1109/TCAD.2013.2293477},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WangZXS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WenLLCC14,
author = {Wan{-}Yu Wen and
Jin{-}Cheng Li and
Sheng{-}Yuan Lin and
Jing{-}Yi Chen and
Shih{-}Chieh Chang},
title = {A Fuzzy-Matching Model With Grid Reduction for Lithography Hotspot
Detection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {11},
pages = {1671--1680},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2351273},
doi = {10.1109/TCAD.2014.2351273},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WenLLCC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WenZC0014,
author = {Wujie Wen and
Yaojun Zhang and
Yiran Chen and
Yu Wang and
Yuan Xie},
title = {{PS3-RAM:} {A} Fast Portable and Scalable Statistical {STT-RAM} Reliability/Energy
Analysis Method},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {11},
pages = {1644--1656},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2351581},
doi = {10.1109/TCAD.2014.2351581},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WenZC0014.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WettinKMYPGH14,
author = {Paul Wettin and
Ryan Gary Kim and
Jacob Murray and
Xinmin Yu and
Partha Pratim Pande and
Amlan Ganguly and
Deuk Hyoun Heo},
title = {Design Space Exploration for Wireless NoCs Incorporating Irregular
Network Routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {11},
pages = {1732--1745},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2351577},
doi = {10.1109/TCAD.2014.2351577},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WettinKMYPGH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WilleLD14,
author = {Robert Wille and
Aaron Lye and
Rolf Drechsler},
title = {Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1818--1831},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2356463},
doi = {10.1109/TCAD.2014.2356463},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WilleLD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuLCYHL14,
author = {Po{-}Hsun Wu and
Mark Po{-}Hung Lin and
Tung{-}Chieh Chen and
Ching{-}Feng Yeh and
Tsung{-}Yi Ho and
Bin{-}Da Liu},
title = {Exploring Feasibilities of Symmetry Islands and Monotonic Current
Paths in Slicing Trees for Analog Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {6},
pages = {879--892},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2305831},
doi = {10.1109/TCAD.2014.2305831},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WuLCYHL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuLWY14,
author = {Kai{-}Chiang Wu and
Ing{-}Chao Lin and
Yao{-}Te Wang and
Shuen{-}Shiang Yang},
title = {BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating
Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {10},
pages = {1591--1595},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2334331},
doi = {10.1109/TCAD.2014.2334331},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuLWY14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuWLH14,
author = {Cheng{-}Yin Wu and
Chi{-}An Wu and
Chien{-}Yu Lai and
Chung{-}Yang (Ric) Huang},
title = {A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based
Model Checking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1846--1858},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2363395},
doi = {10.1109/TCAD.2014.2363395},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuWLH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuYH14,
author = {Bo{-}Han Wu and
Chun{-}Ju Yang and
Chung{-}Yang Huang},
title = {A High-Throughput and Arbitrary-Distribution Pattern Generator for
the Constrained Random Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {1},
pages = {139--152},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2282776},
doi = {10.1109/TCAD.2013.2282776},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuYH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XiaoFT14,
author = {Kan Xiao and
Domenic Forte and
Mohammad Tehranipoor},
title = {A Novel Built-In Self-Authentication Technique to Prevent Inserting
Hardware Trojans},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1778--1791},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2356453},
doi = {10.1109/TCAD.2014.2356453},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/XiaoFT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangJH14,
author = {Yu{-}Ming Yang and
Iris Hui{-}Ru Jiang and
Sung{-}Ting Ho},
title = {PushPull: Short-Path Padding for Timing Error Resilient Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {558--570},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2304681},
doi = {10.1109/TCAD.2014.2304681},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangJH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangLT14,
author = {Joon{-}Sung Yang and
Jinkyu Lee and
Nur A. Touba},
title = {Utilizing {ATE} Vector Repeat With Linear Decompressor for Test Vector
Compression},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {8},
pages = {1219--1230},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2314307},
doi = {10.1109/TCAD.2014.2314307},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangLT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YaoYW14,
author = {Jian Yao and
Zuochang Ye and
Yan Wang},
title = {Importance Boundary Sampling for {SRAM} Yield Analysis With Multiple
Failure Regions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {3},
pages = {384--396},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2292504},
doi = {10.1109/TCAD.2013.2292504},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YaoYW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YaoYW14a,
author = {Jian Yao and
Zuochang Ye and
Yan Wang},
title = {Scalable Compact Modeling for On-Chip Passive Elements with Correlated
Parameter Extraction and Adaptive Boundary Compression},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {9},
pages = {1424--1428},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2323197},
doi = {10.1109/TCAD.2014.2323197},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YaoYW14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YeWYXWWNWD14,
author = {Yaoyao Ye and
Zhehui Wang and
Peng Yang and
Jiang Xu and
Xiaowen Wu and
Xuan Wang and
Mahdi Nikdast and
Zhe Wang and
Luan H. K. Duong},
title = {System-Level Modeling and Analysis of Thermal Effects in WDM-Based
Optical Networks-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {11},
pages = {1718--1731},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2351584},
doi = {10.1109/TCAD.2014.2351584},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/YeWYXWWNWD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YeX14,
author = {Rong Ye and
Qiang Xu},
title = {Learning-Based Power Management for Multicore Processors via Idle
Period Manipulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {7},
pages = {1043--1055},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2305838},
doi = {10.1109/TCAD.2014.2305838},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/YeX14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YeZCG14,
author = {Fangming Ye and
Zhaobo Zhang and
Krishnendu Chakrabarty and
Xinli Gu},
title = {Board-Level Functional Fault Diagnosis Using Multikernel Support Vector
Machines and Incremental Learning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {2},
pages = {279--290},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2287184},
doi = {10.1109/TCAD.2013.2287184},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/YeZCG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YehCHYH14,
author = {Sheng{-}Han Yeh and
Jia{-}Wen Chang and
Tsung{-}Wei Huang and
Shang{-}Tsung Yu and
Tsung{-}Yi Ho},
title = {Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained
{EWOD} Chips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {9},
pages = {1302--1315},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2331340},
doi = {10.1109/TCAD.2014.2331340},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YehCHYH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuLHHKC14,
author = {Cody Hao Yu and
Chiao{-}Ling Lung and
Yi{-}Lun Ho and
Ruei{-}Siang Hsu and
Ding{-}Ming Kwai and
Shih{-}Chieh Chang},
title = {Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput
Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {5},
pages = {763--773},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2293476},
doi = {10.1109/TCAD.2013.2293476},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuLHHKC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhanSOTN014,
author = {Jia Zhan and
Nikolay Stoimenov and
Jin Ouyang and
Lothar Thiele and
Vijaykrishnan Narayanan and
Yuan Xie},
title = {Optimizing the NoC Slack Through Voltage and Frequency Scaling in
Hard Real-Time Embedded Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {11},
pages = {1632--1643},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2347921},
doi = {10.1109/TCAD.2014.2347921},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhanSOTN014.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangEED14,
author = {Zheng Zhang and
Tarek A. El{-}Moselhy and
Ibrahim M. Elfadel and
Luca Daniel},
title = {Calculation of Generalized Polynomial-Chaos Basis Functions and Gauss
Quadrature Rules in Hierarchical Uncertainty Quantification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {5},
pages = {728--740},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2295818},
doi = {10.1109/TCAD.2013.2295818},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhangEED14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhengGYCR14,
author = {Hongbin Zheng and
Swathi T. Gurumani and
Liwei Yang and
Deming Chen and
Kyle Rupnow},
title = {High-Level Synthesis With Behavioral-Level Multicycle Path Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1832--1845},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2361661},
doi = {10.1109/TCAD.2014.2361661},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhengGYCR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhongKAZ14,
author = {Shida Zhong and
S. Saqib Khursheed and
Bashir M. Al{-}Hashimi and
Wei Zhao},
title = {Efficient Variation-Aware Delay Fault Simulation Methodology for Resistive
Open and Bridge Defects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {5},
pages = {798--810},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2295812},
doi = {10.1109/TCAD.2013.2295812},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhongKAZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhouCGC14,
author = {Rong Zhou and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {A Low Overhead Quasi-Delay-Insensitive {(QDI)} Asynchronous Data Path
Synthesis Based on Microcell-Interleaving Genetic Algorithm {(MIGA)}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {7},
pages = {989--1002},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2309859},
doi = {10.1109/TCAD.2014.2309859},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhouCGC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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