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@article{DBLP:journals/tcad/AbabeiMB06,
author = {Cristinel Ababei and
Hushrav Mogal and
Kia Bazargan},
title = {Three-dimensional place and route for FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1132--1140},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855945},
doi = {10.1109/TCAD.2005.855945},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AbabeiMB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AgarwalASB06,
author = {Kanak Agarwal and
Mridul Agarwal and
Dennis Sylvester and
David T. Blaauw},
title = {Statistical interconnect metrics for physical-design optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1273--1288},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855954},
doi = {10.1109/TCAD.2005.855954},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AgarwalASB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AgarwalSB06,
author = {Kanak Agarwal and
Dennis Sylvester and
David T. Blaauw},
title = {Modeling and analysis of crosstalk noise in coupled {RLC} interconnects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {892--901},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855961},
doi = {10.1109/TCAD.2005.855961},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AgarwalSB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AkbarpourT06,
author = {Behzad Akbarpour and
Sofi{\`{e}}ne Tahar},
title = {An approach for the formal verification of {DSP} designs using Theorem
proving},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {8},
pages = {1441--1457},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.857314},
doi = {10.1109/TCAD.2005.857314},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AkbarpourT06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Al-ArsHGA06,
author = {Zaid Al{-}Ars and
Said Hamdioui and
Ad J. van de Goor and
Sultan M. Al{-}Harbi},
title = {Influence of Bit-Line Coupling and Twisting on the Faulty Behavior
of DRAMs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2989--2996},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882492},
doi = {10.1109/TCAD.2006.882492},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Al-ArsHGA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Al-JunaidKWB06,
author = {Hessa Al{-}Junaid and
Tom J. Kazmierski and
Peter R. Wilson and
Jerzy Baranowski},
title = {Timeless Discretization of Magnetization Slope in the Modeling of
Ferromagnetic Hysteresis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2757--2764},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882476},
doi = {10.1109/TCAD.2006.882476},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Al-JunaidKWB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlmukhaizimDM06,
author = {Sobeeh Almukhaizim and
Petros Drineas and
Yiorgos Makris},
title = {Entropy-driven parity-tree selection for low-overhead concurrent error
detection in finite state machines},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {8},
pages = {1547--1554},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855933},
doi = {10.1109/TCAD.2005.855933},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlmukhaizimDM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlpertHSS06,
author = {Charles J. Alpert and
Jiang Hu and
Sachin S. Sapatnekar and
Cliff C. N. Sze},
title = {Accurate estimation of global buffer delay within a floorplan},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1140--1145},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855889},
doi = {10.1109/TCAD.2005.855889},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlpertHSS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AltmanBTW06,
author = {Michael D. Altman and
Jaydeep P. Bardhan and
Bruce Tidor and
Jacob K. White},
title = {{FFTSVD:} {A} Fast Multiscale Boundary-Element Method Solver Suitable
for Bio-MEMS and Biomolecule Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {2},
pages = {274--284},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855946},
doi = {10.1109/TCAD.2005.855946},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AltmanBTW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AndersonN06,
author = {Jason Helge Anderson and
Farid N. Najm},
title = {Active leakage power optimization for FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {423--437},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.853692},
doi = {10.1109/TCAD.2005.853692},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AndersonN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BadarogluTPWVDGM06,
author = {Mustafa Badaroglu and
Kris Tiri and
Geert Van der Plas and
Piet Wambacq and
Ingrid Verbauwhede and
St{\'{e}}phane Donnay and
Georges G. E. Gielen and
Hugo De Man},
title = {Clock-skew-optimization methodology for substrate-noise reduction
with supply-current folding},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1146--1154},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855952},
doi = {10.1109/TCAD.2005.855952},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BadarogluTPWVDGM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BanerjeeMRC06,
author = {Shibaji Banerjee and
Debdeep Mukhopadhyay and
C. V. G. Rao and
Dipanwita Roy Chowdhury},
title = {An integrated {DFT} solution for mixed-signal SOCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1368--1377},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855972},
doi = {10.1109/TCAD.2005.855972},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BanerjeeMRC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BansalPR06,
author = {Aditya Bansal and
Bipul Chandra Paul and
Kaushik Roy},
title = {An Analytical Fringe Capacitance Model for Interconnects Using Conformal
Mapping},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2765--2774},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882489},
doi = {10.1109/TCAD.2006.882489},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BansalPR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BasuDBDCMFA06,
author = {Prasenjit Basu and
Sayantan Das and
Ansuman Banerjee and
Pallab Dasgupta and
P. P. Chakrabarti and
Chunduri Rama Mohan and
Limor Fix and
Roy Armoni},
title = {Design-Intent Coverage - {A} New Paradigm for Formal Property Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {1922--1934},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.859490},
doi = {10.1109/TCAD.2005.859490},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/BasuDBDCMFA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BedekarWKSS06,
author = {Anand S. Bedekar and
Yi Wang and
S. Krishnamoorthy and
Sachin S. Siddhaye and
Shankar Sundaram},
title = {System-Level Simulation of Flow-Induced Dispersion in Lab-on-a-Chip
Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {2},
pages = {294--304},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.858354},
doi = {10.1109/TCAD.2005.858354},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BedekarWKSS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BhattacharyaJS06,
author = {Sambuddha Bhattacharya and
Nuttorn Jangkrajarng and
C.{-}J. Richard Shi},
title = {Multilevel symmetry-constraint generation for retargeting large analog
layouts},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {945--960},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855982},
doi = {10.1109/TCAD.2005.855982},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BhattacharyaJS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BilavarnGPB06,
author = {S{\'{e}}bastien Bilavarn and
Guy Gogniat and
Jean Luc Philippe and
Lilian Bossuet},
title = {Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs
for {FPGA} Implementations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {1950--1968},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.862742},
doi = {10.1109/TCAD.2005.862742},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BilavarnGPB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BlantonDD06,
author = {Ronald D. Blanton and
Kumar N. Dwarakanath and
Rao Desineni},
title = {Defect Modeling Using Fault Tuples},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2450--2464},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870836},
doi = {10.1109/TCAD.2006.870836},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BlantonDD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BodapatiN06,
author = {Srinivas Bodapati and
Farid N. Najm},
title = {High-level current macro model for logic blocks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {837--855},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855976},
doi = {10.1109/TCAD.2005.855976},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BodapatiN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Bohringer06,
author = {Karl{-}Friedrich B{\"{o}}hringer},
title = {Modeling and Controlling Parallel Tasks in Droplet-Based Microfluidic
Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {2},
pages = {334--344},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855958},
doi = {10.1109/TCAD.2005.855958},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Bohringer06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BriskDJS06,
author = {Philip Brisk and
Foad Dabiri and
Roozbeh Jafari and
Majid Sarrafzadeh},
title = {Optimal register sharing for high-level synthesis of {SSA} form programs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {772--779},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870409},
doi = {10.1109/TCAD.2006.870409},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BriskDJS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CaiPL06,
author = {Le Cai and
Nathaniel Pettis and
Yung{-}Hsiang Lu},
title = {Joint Power Management of Memory and Disk Under Performance Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2697--2711},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882587},
doi = {10.1109/TCAD.2006.882587},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CaiPL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CantinSPL06,
author = {Marc{-}Andr{\'{e}} Cantin and
Yvon Savaria and
D. Prodanos and
Pierre Lavoie},
title = {A Metric for Automatic Word-Length Determination of Hardware Datapaths},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2228--2231},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.862733},
doi = {10.1109/TCAD.2005.862733},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CantinSPL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CapobianchiLSM06,
author = {M. Capobianchi and
V. Labay and
F. Shi and
G. Mizushima},
title = {Simulating the Electrical Behavior of Integrated Circuit Devices in
the Presence of Thermal Interactions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2231--2241},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.859488},
doi = {10.1109/TCAD.2005.859488},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CapobianchiLSM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CarmonaCCG06,
author = {Josep Carmona and
Jos{\'{e}} Manuel Colom and
Jordi Cortadella and
Fernando Garc{\'{\i}}a{-}Vall{\'{e}}s},
title = {Synthesis of asynchronous controllers using integer linear programming},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1637--1651},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.859516},
doi = {10.1109/TCAD.2005.859516},
timestamp = {Thu, 09 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/CarmonaCCG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CasuM06,
author = {Mario R. Casu and
Luca Macchiarulo},
title = {Floorplanning With Wire Pipelining in Adaptive Communication Channels},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2996--3004},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882590},
doi = {10.1109/TCAD.2006.882590},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CasuM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CervenkaWAGS06,
author = {Johann Cervenka and
W. Wessner and
E. Al{-}Ani and
Tibor Grasser and
Siegfried Selberherr},
title = {Generation of Unstructured Meshes for Process and Device Simulation
by Means of Partial Differential Equations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2118--2128},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.876514},
doi = {10.1109/TCAD.2006.876514},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CervenkaWAGS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChakrabortyLM06,
author = {Kanad Chakraborty and
Alexey Lvov and
Maharaj Mukherjee},
title = {Novel algorithms for placement of rectangular covers for mask inspection
in advanced lithography and other {VLSI} design applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {79--91},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.853710},
doi = {10.1109/TCAD.2005.853710},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChakrabortyLM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChantrapornchaiSS06,
author = {Chantana Chantrapornchai and
Wanlop Surakampontorn and
Edwin Hsing{-}Mean Sha},
title = {Design Exploration With Imprecise Latency and Register Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2650--2662},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882591},
doi = {10.1109/TCAD.2006.882591},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChantrapornchaiSS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChatterjeeMBWK06,
author = {Satrajit Chatterjee and
Alan Mishchenko and
Robert K. Brayton and
Xinning Wang and
Timothy Kam},
title = {Reducing Structural Bias in Technology Mapping},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2894--2903},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882484},
doi = {10.1109/TCAD.2006.882484},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChatterjeeMBWK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenC06,
author = {Tung{-}Chieh Chen and
Yao{-}Wen Chang},
title = {Modern Floorplanning Based on B\({}^{\mbox{*}}\)-Tree and Fast Simulated
Annealing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {4},
pages = {637--650},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870076},
doi = {10.1109/TCAD.2006.870076},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenH06,
author = {Jun Chen and
Lei He},
title = {Modeling and synthesis of multiport transmission line for multichannel
communication},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1664--1676},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.858272},
doi = {10.1109/TCAD.2005.858272},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenLW06,
author = {Hung{-}Ming Chen and
I{-}Min Liu and
Martin D. F. Wong},
title = {{I/O} Clustering in Design Cost and Performance Optimization for Flip-Chip
Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2552--2556},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.873900},
doi = {10.1109/TCAD.2006.873900},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenLW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenZ06,
author = {Ruiming Chen and
Hai Zhou},
title = {Statistical timing verification for transparently latched circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1847--1855},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.857395},
doi = {10.1109/TCAD.2005.857395},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenZ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenZ06a,
author = {Ruiming Chen and
Hai Zhou},
title = {An Efficient Data Structure for Maxplus Merge in Dynamic Programming},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {3004--3009},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882479},
doi = {10.1109/TCAD.2006.882479},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenZ06a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengW06,
author = {Lei Cheng and
Martin D. F. Wong},
title = {Floorplan Design for Multimillion Gate FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2795--2805},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882481},
doi = {10.1109/TCAD.2006.882481},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChengW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoiM06,
author = {Munkang Choi and
Linda S. Milor},
title = {Impact on circuit performance of deterministic within-die variation
in nanoscale semiconductor manufacturing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1350--1367},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855963},
doi = {10.1109/TCAD.2005.855963},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChoiM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChopraV06,
author = {Kaviraj Chopra and
Sarma B. K. Vrudhula},
title = {Efficient Symbolic Algorithms for Computing the Minimum and Bounded
Leakage States},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2820--2832},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882603},
doi = {10.1109/TCAD.2006.882603},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChopraV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CirianiBD06,
author = {Valentina Ciriani and
Anna Bernasconi and
Rolf Drechsler},
title = {Testability of {SPP} Three-Level Logic Networks in Static Fault Models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2241--2248},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.862746},
doi = {10.1109/TCAD.2005.862746},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CirianiBD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongRS06,
author = {Jason Cong and
Michail Romesis and
Joseph R. Shinnerl},
title = {Fast floorplanning by look-ahead enabled recursive bipartitioning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1719--1732},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.859519},
doi = {10.1109/TCAD.2005.859519},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongRS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CortadellaKLS06,
author = {Jordi Cortadella and
Alex Kondratyev and
Luciano Lavagno and
Christos P. Sotiriou},
title = {Desynchronization: Synthesis of Asynchronous Circuits From Synchronous
Specifications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {1904--1921},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.860958},
doi = {10.1109/TCAD.2005.860958},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CortadellaKLS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CotaL06,
author = {{\'{E}}rika F. Cota and
Chunsheng Liu},
title = {Constraint-Driven Test Scheduling for NoC-Based Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2465--2478},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.881331},
doi = {10.1109/TCAD.2006.881331},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CotaL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DattaBMR06,
author = {Animesh Datta and
Swarup Bhunia and
Saibal Mukhopadhyay and
Kaushik Roy},
title = {Delay Modeling and Statistical Design of Pipelined Circuit Under Process
Variation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2427--2436},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.873886},
doi = {10.1109/TCAD.2006.873886},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DattaBMR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DavoodiKS06,
author = {Azadeh Davoodi and
Vishal Khandelwal and
Ankur Srivastava},
title = {Probabilistic Evaluation of Solutions in Variability-Driven Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {3010--3016},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882529},
doi = {10.1109/TCAD.2006.882529},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/DavoodiKS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DrinicKMP06,
author = {Milenko Drinic and
Darko Kirovski and
Seapahn Megerian and
Miodrag Potkonjak},
title = {Latency-Guided On-Chip Bus-Network Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2663--2673},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882488},
doi = {10.1109/TCAD.2006.882488},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DrinicKMP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DuanM06,
author = {Xiaochun Duan and
Kartikeya Mayaram},
title = {Frequency-Domain Simulation of Ring Oscillators With a Multiple-Probe
Method},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2833--2842},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882586},
doi = {10.1109/TCAD.2006.882586},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DuanM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DuanM06a,
author = {Xiaochun Duan and
Kartikeya Mayaram},
title = {Robust Simulation of High-Q Oscillators Using a Homotopy-Based Harmonic
Balance Method},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2843--2851},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882602},
doi = {10.1109/TCAD.2006.882602},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DuanM06a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EbendtD06,
author = {R{\"{u}}diger Ebendt and
Rolf Drechsler},
title = {Effect of improved lower bounds in dynamic {BDD} reordering},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {902--909},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.854632},
doi = {10.1109/TCAD.2005.854632},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EbendtD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EkpanyapongHL06,
author = {Mongkol Ekpanyapong and
Michael B. Healy and
Sung Kyu Lim},
title = {Profile-Driven Instruction Mapping for Dataflow Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {3017--3025},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.883927},
doi = {10.1109/TCAD.2006.883927},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EkpanyapongHL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EkpanyapongMWLL06,
author = {Mongkol Ekpanyapong and
Jacob R. Minz and
Thaisiri Watewai and
Hsien{-}Hsin S. Lee and
Sung Kyu Lim},
title = {Profile-guided microarchitectural floor planning for deep submicron
processor design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1289--1300},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855971},
doi = {10.1109/TCAD.2005.855971},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EkpanyapongMWLL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/El-MalehKS06,
author = {Aiman H. El{-}Maleh and
S. Saqib Khursheed and
Sadiq M. Sait},
title = {Efficient Static Compaction Techniques for Sequential Circuits Based
on Reverse-Order Restoration and Test Relaxation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2556--2564},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.873895},
doi = {10.1109/TCAD.2006.873895},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/El-MalehKS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EngelkePRB06,
author = {Piet Engelke and
Ilia Polian and
Michel Renovell and
Bernd Becker},
title = {Simulating Resistive-Bridging and Stuck-At Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2181--2192},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.871626},
doi = {10.1109/TCAD.2006.871626},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/EngelkePRB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FengM06,
author = {Yan Feng and
Dinesh P. Mehta},
title = {Module relocation to obtain feasible constrained floorplans},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {856--866},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855981},
doi = {10.1109/TCAD.2005.855981},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/FengM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FerzliN06,
author = {Imad A. Ferzli and
Farid N. Najm},
title = {Analysis and verification of power grids considering process-induced
leakage-current variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {126--143},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.852665},
doi = {10.1109/TCAD.2005.852665},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FerzliN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FeyD06,
author = {G{\"{o}}rschwin Fey and
Rolf Drechsler},
title = {Minimizing the number of paths in BDDs: Theory and algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {4--11},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.852662},
doi = {10.1109/TCAD.2005.852662},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FeyD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GalanisTTG06,
author = {Michalis D. Galanis and
George Theodoridis and
Spyros Tragoudas and
Constantinos E. Goutis},
title = {A high-performance data path for synthesizing {DSP} kernels},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1154--1162},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855965},
doi = {10.1109/TCAD.2005.855965},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GalanisTTG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GaoH06,
author = {Feng Gao and
John P. Hayes},
title = {Exact and Heuristic Approaches to Input Vector Control for Leakage
Power Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2564--2571},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.875711},
doi = {10.1109/TCAD.2006.875711},
timestamp = {Thu, 09 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/GaoH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GhiasiBHJS06,
author = {Soheil Ghiasi and
Elaheh Bozorgzadeh and
Po{-}Kuan Huang and
Roozbeh Jafari and
Majid Sarrafzadeh},
title = {A Unified Theory of Timing Budget Management},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2364--2375},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.873901},
doi = {10.1109/TCAD.2006.873901},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GhiasiBHJS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GhoneimaIKTD06,
author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {Formal derivation of optimal active shielding for low-power on-chip
buses},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {821--836},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855974},
doi = {10.1109/TCAD.2005.855974},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GhoneimaIKTD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GhoshBRR06,
author = {Swaroop Ghosh and
Swarup Bhunia and
Arijit Raychowdhury and
Kaushik Roy},
title = {A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In
Delay Sensor},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2934--2943},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882523},
doi = {10.1109/TCAD.2006.882523},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GhoshBRR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GoplenS06,
author = {Brent Goplen and
Sachin S. Sapatnekar},
title = {Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {4},
pages = {692--709},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870069},
doi = {10.1109/TCAD.2006.870069},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GoplenS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GriffithAG06,
author = {Eric J. Griffith and
Srinivas Akella and
Mark K. Goldberg},
title = {Performance Characterization of a Reconfigurable Planar-Array Digital
Microfluidic System},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {2},
pages = {345--357},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.859515},
doi = {10.1109/TCAD.2005.859515},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GriffithAG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuoV06,
author = {Ruifeng Guo and
Srikanth Venkataraman},
title = {An algorithmic technique for diagnosis of faulty scan chains},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1861--1868},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.858267},
doi = {10.1109/TCAD.2005.858267},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuoV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuptaAJ06,
author = {Pallav Gupta and
Abhinav Agrawal and
Niraj K. Jha},
title = {An Algorithm for Synthesis of Reversible Logic Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2317--2330},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.871622},
doi = {10.1109/TCAD.2006.871622},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuptaAJ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuptaKPSX06,
author = {Puneet Gupta and
Andrew B. Kahng and
Chul{-}Hong Park and
Kambiz Samadi and
Xu Xu},
title = {Wafer Topography-Aware Optical Proximity Correction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2747--2756},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882604},
doi = {10.1109/TCAD.2006.882604},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuptaKPSX06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuptaKSS06,
author = {Puneet Gupta and
Andrew B. Kahng and
Puneet Sharma and
Dennis Sylvester},
title = {Gate-length biasing for runtime-leakage control},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {8},
pages = {1475--1485},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.857313},
doi = {10.1109/TCAD.2005.857313},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuptaKSS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HaznedarGZKOP06,
author = {Haldun Haznedar and
Martin Gall and
Vladimir Zolotov and
Pon Sung Ku and
Chanhee Oh and
Rajendran Panda},
title = {Impact of stress-induced backflow on full-chip electromigration risk
assessment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1038--1046},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855941},
doi = {10.1109/TCAD.2005.855941},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HaznedarGZKOP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HosangadiFK06,
author = {Anup Hosangadi and
Farzan Fallah and
Ryan Kastner},
title = {Optimizing Polynomial Expressions by Algebraic Factorization and Common
Subexpression Elimination},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2012--2022},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.875712},
doi = {10.1109/TCAD.2006.875712},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HosangadiFK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HrkicLB06,
author = {Milos Hrkic and
John Lillis and
Giancarlo Beraudo},
title = {An Approach to Placement-Coupled Logic Replication},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2539--2551},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.871624},
doi = {10.1109/TCAD.2006.871624},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HrkicLB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsiehLC06,
author = {C.{-}T. Hsieh and
J.{-}C. Lin and
S.{-}C. Chang},
title = {Vectorless Estimation of Maximum Instantaneous Current for Sequential
Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2341--2352},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.873894},
doi = {10.1109/TCAD.2006.873894},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsiehLC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuM06,
author = {Yutao Hu and
Kartikeya Mayaram},
title = {Comparison of Algorithms for Frequency Domain Coupled Device and Circuit
Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2571--2578},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.871621},
doi = {10.1109/TCAD.2006.871621},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuOM06,
author = {Jingcao Hu and
{\"{U}}mit Y. Ogras and
Radu Marculescu},
title = {System-Level Buffer Allocation for Application-Specific Networks-on-Chip
Router Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2919--2933},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882474},
doi = {10.1109/TCAD.2006.882474},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HuOM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangN06,
author = {Shih{-}Hsu Huang and
Yow{-}Tyng Nieh},
title = {Synthesis of nonzero clock skew circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {961--976},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855923},
doi = {10.1109/TCAD.2005.855923},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangRRJ06,
author = {Chao Huang and
Srivaths Ravi and
Anand Raghunathan and
Niraj K. Jha},
title = {Use of Computation-Unit Integrated Memories in High-Level Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {1969--1989},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.862749},
doi = {10.1109/TCAD.2005.862749},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangRRJ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HungSYYP06,
author = {William N. N. Hung and
Xiaoyu Song and
Guowu Yang and
Jin Yang and
Marek A. Perkowski},
title = {Optimal synthesis of multiple output Boolean functions using a set
of quantum gates by symbolic reachability analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1652--1663},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.858352},
doi = {10.1109/TCAD.2005.858352},
timestamp = {Mon, 17 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HungSYYP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IranliP06,
author = {Ali Iranli and
Massoud Pedram},
title = {Cycle-Based Decomposition of Markov Chains With Applications to Low-Power
Synthesis and Sequence Compaction for Finite State Machines},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2712--2725},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882478},
doi = {10.1109/TCAD.2006.882478},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IranliP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IyerSEJ06,
author = {Subramanian K. Iyer and
Debashis Sahoo and
E. Allen Emerson and
Jawahar Jain},
title = {On partitioning and symbolic model checking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {780--788},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870410},
doi = {10.1109/TCAD.2006.870410},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IyerSEJ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JejurikarG06,
author = {Ravindra Jejurikar and
Rajesh K. Gupta},
title = {Energy-aware task scheduling with task synchronization for embedded
real-time systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1024--1037},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855964},
doi = {10.1109/TCAD.2005.855964},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JejurikarG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JessKNOV06,
author = {Jochen A. G. Jess and
Kerim Kalafala and
Srinath R. Naidu and
Ralph H. J. M. Otten and
Chandramouli Visweswariah},
title = {Statistical Timing for Parametric Yield Prediction of Digital Integrated
Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2376--2392},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.881332},
doi = {10.1109/TCAD.2006.881332},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JessKNOV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiangB06,
author = {Tao Jiang and
R. D. (Shawn) Blanton},
title = {Inductive fault analysis of surface-micromachined {MEMS}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1104--1116},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855926},
doi = {10.1109/TCAD.2005.855926},
timestamp = {Wed, 22 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/JiangB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiangB06a,
author = {Jie{-}Hong Roland Jiang and
Robert K. Brayton},
title = {Retiming and Resynthesis: {A} Complexity Perspective},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2674--2686},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882520},
doi = {10.1109/TCAD.2006.882520},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiangB06a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JimenezMZBA06,
author = {Jaime Jimenez and
Jos{\'{e}} Luis Mart{\'{\i}}n and
Aitzol Zuloaga and
Unai Bidarte and
Jagoba Arias},
title = {Comparison of two designs for the multifunction vehicle bus},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {797--805},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855925},
doi = {10.1109/TCAD.2005.855925},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JimenezMZBA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JoshiWSK06,
author = {Nikhil Joshi and
Kaijie Wu and
Jayachandran Sundararajan and
Ramesh Karri},
title = {Concurrent error detection for involutional functions with applications
in fault-tolerant cryptographic hardware design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1163--1169},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855980},
doi = {10.1109/TCAD.2005.855980},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JoshiWSK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JungEF06,
author = {Kooho Jung and
William R. Eisenstadt and
Robert M. Fox},
title = {SPICE-based mixed-mode S-parameter calculations for four-port and
three-port circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {909--913},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855924},
doi = {10.1109/TCAD.2005.855924},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JungEF06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KagarisKN06,
author = {Dimitrios Kagaris and
P. Karpodinis and
Dimitris Nikolos},
title = {On Obtaining Maximum-Length Sequences for Accumulator-Based Serial
{TPG}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2578--2586},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870860},
doi = {10.1109/TCAD.2006.870860},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KagarisKN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngMRXZ06,
author = {Andrew B. Kahng and
Ion I. Mandoiu and
Sherief Reda and
Xu Xu and
Alexander Zelikovsky},
title = {Computer-Aided Optimization of {DNA} Array Design and Manufacturing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {2},
pages = {305--320},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855940},
doi = {10.1109/TCAD.2005.855940},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KahngMRXZ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngR06,
author = {Andrew B. Kahng and
Sherief Reda},
title = {New and improved {BIST} diagnosis methods from combinatorial Group
testing theory},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {533--543},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.854635},
doi = {10.1109/TCAD.2005.854635},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KahngR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngR06a,
author = {Andrew B. Kahng and
Sherief Reda},
title = {Wirelength minimization for min-cut placements via placement feedback},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1301--1312},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855917},
doi = {10.1109/TCAD.2005.855917},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KahngR06a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngR06b,
author = {Andrew B. Kahng and
Sherief Reda},
title = {Zero-Change Netlist Transformations: {A} New Technique for Placement
Benchmarking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2806--2819},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882473},
doi = {10.1109/TCAD.2006.882473},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KahngR06b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KannanB06,
author = {PariVallal Kannan and
Dinesh Bhatia},
title = {Interconnect estimation for FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {8},
pages = {1523--1534},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.857312},
doi = {10.1109/TCAD.2005.857312},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KannanB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KenningsV06,
author = {Andrew A. Kennings and
Kristofer Vorwerk},
title = {Force-Directed Methods for Generic Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2076--2087},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.862748},
doi = {10.1109/TCAD.2005.862748},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KenningsV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimB06,
author = {Sangyun Kim and
Peter A. Beerel},
title = {Pipeline optimization for asynchronous circuits: complexity analysis
and an efficient optimal algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {389--402},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.853689},
doi = {10.1109/TCAD.2005.853689},
timestamp = {Tue, 05 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KimB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimK06,
author = {Hong{-}Sik Kim and
Sungho Kang},
title = {Increasing encoding efficiency of {LFSR} reseeding-based test compression},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {913--917},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855977},
doi = {10.1109/TCAD.2005.855977},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KimK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimKP06,
author = {Kyosun Kim and
Ramesh Karri and
Miodrag Potkonjak},
title = {Micropreemption synthesis: an enabling mechanism for multitask {VLSI}
systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {19--30},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.852668},
doi = {10.1109/TCAD.2005.852668},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimKP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KirovskiHPC06,
author = {Darko Kirovski and
Yean{-}Yow Hwang and
Miodrag Potkonjak and
Jason Cong},
title = {Protecting Combinational Logic Synthesis Solutions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2687--2696},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882490},
doi = {10.1109/TCAD.2006.882490},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KirovskiHPC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KnockaertD06,
author = {Luc Knockaert and
Tom Dhaene},
title = {Orthonormal bandlimited Kautz sequences for global system modeling
from piecewise rational models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1377--1381},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855888},
doi = {10.1109/TCAD.2005.855888},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KnockaertD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KongN06,
author = {Xiaohua Kong and
Radu Negulescu},
title = {Semihiding operators and active-edge specification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1831--1846},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.858349},
doi = {10.1109/TCAD.2005.858349},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KongN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KouroussisAN06,
author = {Dionysios Kouroussis and
Rubil Ahmadi and
Farid N. Najm},
title = {Voltage-Aware Static Timing Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2156--2169},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.860953},
doi = {10.1109/TCAD.2005.860953},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KouroussisAN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KuboT06,
author = {Yukiko Kubo and
Atsushi Takahashi},
title = {Global Routing by Iterative Improvements for Two-Layer Ball Grid Array
Packages},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {4},
pages = {725--733},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870064},
doi = {10.1109/TCAD.2006.870064},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KuboT06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KumarTCJ06,
author = {Mahilchi Milir Vaseekar Kumar and
Spyros Tragoudas and
Sreejit Chakravarty and
Rathish Jayabharathi},
title = {Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault
Model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2954--2964},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882583},
doi = {10.1109/TCAD.2006.882583},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KumarTCJ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LaiWF06,
author = {Nan{-}Cheng Lai and
Sying{-}Jyan Wang and
Y.{-}H. Fu},
title = {Low-Power {BIST} With a Smoother and Scan-Chain Reorder Under Optimal
Cluster Size},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2586--2594},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870861},
doi = {10.1109/TCAD.2006.870861},
timestamp = {Fri, 11 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LaiWF06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LasbouyguesEWMAA06,
author = {B. Lasbouygues and
Sylvain Engels and
Robin Wilson and
Philippe Maurine and
Nadine Az{\'{e}}mard and
Daniel Auvergne},
title = {Logical effort model extension to propagation delay representation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1677--1684},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.857400},
doi = {10.1109/TCAD.2005.857400},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LasbouyguesEWMAA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeGCMLC06,
author = {Dong{-}U Lee and
Altaf Abdul Gaffar and
Ray C. C. Cheung and
Oskar Mencer and
Wayne Luk and
George A. Constantinides},
title = {Accuracy-Guaranteed Bit-Width Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {1990--2000},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.873887},
doi = {10.1109/TCAD.2006.873887},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeGCMLC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeK06,
author = {Jae{-}Gon Lee and
Chong{-}Min Kyung},
title = {PrePack: Predictive Packetizing Scheme for Reducing Channel Traffic
in Transaction-Level Hardware/Software Co-Emulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {1935--1949},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.859501},
doi = {10.1109/TCAD.2005.859501},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Li06,
author = {Peng Li},
title = {Statistical Sampling-Based Parametric Analysis of Power Grids},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2852--2867},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882582},
doi = {10.1109/TCAD.2006.882582},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Li06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiFQTWCH06,
author = {Hang Li and
Jeffrey Fan and
Zhenyu Qi and
Sheldon X.{-}D. Tan and
Lifeng Wu and
Yici Cai and
Xianlong Hong},
title = {Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting
and Minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2402--2412},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870862},
doi = {10.1109/TCAD.2006.870862},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiFQTWCH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiJBR06,
author = {Junjun Li and
Sopan Joshi and
Ryan Barnes and
Elyse Rosenbaum},
title = {Compact modeling of on-chip {ESD} protection devices using Verilog-A},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1047--1063},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855948},
doi = {10.1109/TCAD.2005.855948},
timestamp = {Wed, 09 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiJBR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiPAC06,
author = {Peng Li and
Lawrence T. Pileggi and
Mehdi Asheghi and
Rajit Chandra},
title = {{IC} thermal simulation and modeling via efficient multigrid-based
approaches},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1763--1776},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.858276},
doi = {10.1109/TCAD.2005.858276},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiPAC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiS06,
author = {Zhuo Li and
Weiping Shi},
title = {An O(bn\({}^{\mbox{2}}\)) time algorithm for optimal buffer insertion
with b buffer types},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {484--489},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.854631},
doi = {10.1109/TCAD.2005.854631},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiS06a,
author = {Zhao Li and
C.{-}J. Richard Shi},
title = {{SILCA:} SPICE-accurate iterative linear-centric analysis for efficient
time-domain Simulation of {VLSI} circuits with strong parasitic couplings},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1087--1103},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855943},
doi = {10.1109/TCAD.2005.855943},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiS06a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiS06b,
author = {Zhao Li and
C.{-}J. Richard Shi},
title = {A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and
Efficient Time-Domain Simulation of Integrated Circuits With Strong
Parasitic Couplings},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2868--2881},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882483},
doi = {10.1109/TCAD.2006.882483},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiS06b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiSCLC06,
author = {Katherine Shu{-}Min Li and
Chauchin Su and
Yao{-}Wen Chang and
Chung{-}Len Lee and
Jwu E. Chen},
title = {{IEEE} Standard 1500 Compatible Interconnect Diagnosis for Delay and
Crosstalk Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2513--2525},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.881330},
doi = {10.1109/TCAD.2006.881330},
timestamp = {Tue, 07 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiSCLC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiYM06,
author = {Hong Li and
Wen{-}Yan Yin and
Junfa Mao},
title = {Comments on "Modeling of Metallic Carbon-Nanotube Interconnects for
Circuit Simulations and a Comparison With Cu Interconnects for Sealed
Technologies"},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {3042--3044},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.883920},
doi = {10.1109/TCAD.2006.883920},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiYM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiZMORC06,
author = {Hongmei Li and
Cole E. Zemke and
Giorgos Manetas and
Vladimir I. Okhmatovski and
Elyse Rosenbaum and
Andreas C. Cangellaris},
title = {An automated and efficient substrate noise analysis tool},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {454--468},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.854628},
doi = {10.1109/TCAD.2005.854628},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiZMORC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LienemannGK06,
author = {Jan Lienemann and
Andreas Greiner and
Jan G. Korvink},
title = {Modeling, Simulation, and Optimization of Electrowetting},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {2},
pages = {234--247},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855890},
doi = {10.1109/TCAD.2005.855890},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LienemannGK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinH06,
author = {Yan Lin and
Lei He},
title = {Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for {FPGA}
Power Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2023--2034},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870858},
doi = {10.1109/TCAD.2006.870858},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinLC06,
author = {Yung{-}Chieh Lin and
Feng Lu and
Kwang{-}Ting Cheng},
title = {Pseudofunctional testing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {8},
pages = {1535--1546},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.857379},
doi = {10.1109/TCAD.2005.857379},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LinLC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinZ06,
author = {Chuan Lin and
Hai Zhou},
title = {Optimal wire retiming without binary search},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1577--1588},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.858268},
doi = {10.1109/TCAD.2005.858268},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinZ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LingappanRJ06,
author = {Loganathan Lingappan and
Srivaths Ravi and
Niraj K. Jha},
title = {Satisfiability-based test generation for nonseparable {RTL} controller-datapath
circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {544--557},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.853700},
doi = {10.1109/TCAD.2005.853700},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LingappanRJ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LingappanRRJC06,
author = {Loganathan Lingappan and
Srivaths Ravi and
Anand Raghunathan and
Niraj K. Jha and
Srimat T. Chakradhar},
title = {Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and
Multilevel Compression Techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2193--2206},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.862735},
doi = {10.1109/TCAD.2005.862735},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LingappanRRJC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuLJWTY06,
author = {Pu Liu and
Hang Li and
Lingling Jin and
Wei Wu and
Sheldon X.{-}D. Tan and
Jun Yang},
title = {Fast Thermal Simulation for Runtime Temperature Tracking and Management},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2882--2893},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882594},
doi = {10.1109/TCAD.2006.882594},
timestamp = {Thu, 04 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiuLJWTY06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuM06,
author = {Qinghua Liu and
Malgorzata Marek{-}Sadowska},
title = {Semi-Individual Wire-Length Prediction With Application to Logic Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {4},
pages = {611--624},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.859487},
doi = {10.1109/TCAD.2005.859487},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuOB06,
author = {Fang Liu and
Sule Ozev and
Martin A. Brooke},
title = {Identifying the Source of {BW} Failures in High-Frequency Linear Analog
Circuits Based on S-Parameter Measurements},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2594--2605},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.871619},
doi = {10.1109/TCAD.2006.871619},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuOB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuPP06,
author = {Xun Liu and
Yuantao Peng and
Marios C. Papaefthymiou},
title = {Practical repeater insertion for low power: what repeater library
do we need?},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {917--924},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.855968},
doi = {10.1109/TCAD.2006.855968},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuPP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuK06,
author = {Ruibing Lu and
Cheng{-}Kok Koh},
title = {Performance analysis of latency-insensitive systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {469--483},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.854636},
doi = {10.1109/TCAD.2005.854636},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuzKK06,
author = {Victor De La Luz and
Mahmut T. Kandemir and
Ibrahim Kolcu},
title = {Reducing memory energy consumption of embedded applications that process
dynamically allocated data},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1855--1860},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.859521},
doi = {10.1109/TCAD.2005.859521},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuzKK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaR06,
author = {James D. Ma and
Rob A. Rutenbar},
title = {Fast Interval-Valued Statistical Modeling of Interconnect and Effective
Capacitance},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {4},
pages = {710--724},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870067},
doi = {10.1109/TCAD.2006.870067},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MaR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaffezzoniCD06,
author = {Paolo Maffezzoni and
Lorenzo Codecasa and
Dario D'Amore},
title = {Event-Driven Time-Domain Simulation of Closed-Loop Switched Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2413--2426},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882121},
doi = {10.1109/TCAD.2006.882121},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaffezzoniCD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MagargleHM06,
author = {Ryan Magargle and
James F. Hoburg and
Tamal Mukherjee},
title = {Microfluidic Injector Models Based on Artificial Neural Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {2},
pages = {378--385},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855936},
doi = {10.1109/TCAD.2005.855936},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MagargleHM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MakL06,
author = {Wei{-}Kei Mak and
C.{-}L. Lai},
title = {On Constrained Pin-Mapping for {FPGA-PCB} Codesign},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2393--2401},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.881336},
doi = {10.1109/TCAD.2006.881336},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MakL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ManohararajahBV06,
author = {Valavan Manohararajah and
Stephen Dean Brown and
Zvonko G. Vranesic},
title = {Heuristics for Area Minimization in LUT-Based {FPGA} Technology Mapping},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2331--2340},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882119},
doi = {10.1109/TCAD.2006.882119},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ManohararajahBV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MartensG06,
author = {Ewout Martens and
Georges G. E. Gielen},
title = {Analyzing continuous-time Delta-Sigma-Modulators with generic behavioral
models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {924--932},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855970},
doi = {10.1109/TCAD.2005.855970},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MartensG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Mencer06,
author = {Oskar Mencer},
title = {{ASC:} a stream compiler for computing with FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1603--1617},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.857377},
doi = {10.1109/TCAD.2005.857377},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Mencer06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MenonXT06,
author = {Premachandran R. Menon and
Weifeng Xu and
Russell Tessier},
title = {Design-specific path delay testing in lookup-table-based FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {867--877},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855955},
doi = {10.1109/TCAD.2005.855955},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MenonXT06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MinYSBP06,
author = {Pyoungwoo Min and
Hyunbean Yi and
Jaehoon Song and
Sanghyeon Baeg and
Sungju Park},
title = {Efficient Interconnect Test Patterns for Crosstalk and Static Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2605--2608},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.873899},
doi = {10.1109/TCAD.2006.873899},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MinYSBP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MinzL06,
author = {Jacob R. Minz and
Sung Kyu Lim},
title = {Block-level 3-D Global Routing With an Application to 3-D Packaging},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2248--2257},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.860952},
doi = {10.1109/TCAD.2005.860952},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MinzL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MishchenkoB06,
author = {Alan Mishchenko and
Robert K. Brayton},
title = {A theory of nondeterministic networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {977--999},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855978},
doi = {10.1109/TCAD.2005.855978},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MishchenkoB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MishchenkoZSBBC06,
author = {Alan Mishchenko and
Jin S. Zhang and
Subarnarekha Sinha and
Jerry R. Burch and
Robert K. Brayton and
Malgorzata Chrzanowska{-}Jeske},
title = {Using simulation and satisfiability to compute flexibilities in Boolean
networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {743--755},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.860955},
doi = {10.1109/TCAD.2005.860955},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MishchenkoZSBBC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Miskov-ZivanovM06,
author = {Natasa Miskov{-}Zivanov and
Diana Marculescu},
title = {Circuit Reliability Analysis Using Symbolic Techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2638--2649},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882592},
doi = {10.1109/TCAD.2006.882592},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Miskov-ZivanovM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MolinaRMH06,
author = {Mar{\'{\i}}a C. Molina and
Rafael Ruiz{-}Sautua and
Jose Manuel Mendias and
Rom{\'{a}}n Hermida},
title = {Bitwise scheduling to balance the computational cost of behavioral
specifications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {31--46},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.852663},
doi = {10.1109/TCAD.2005.852663},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MolinaRMH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MondalC06,
author = {Arijit Mondal and
P. P. Chakrabarti},
title = {Reasoning about timing behavior of digital circuits using symbolic
event propagation and temporal logic},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1793--1814},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.859508},
doi = {10.1109/TCAD.2005.859508},
timestamp = {Mon, 07 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MondalC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MukhopadhyayBR06,
author = {Saibal Mukhopadhyay and
Swarup Bhunia and
Kaushik Roy},
title = {Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS
logic circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {8},
pages = {1486--1495},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855934},
doi = {10.1109/TCAD.2005.855934},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MukhopadhyayBR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MukhopadhyayKCR06,
author = {Saibal Mukhopadhyay and
Keunwoo Kim and
Ching{-}Te Chuang and
Kaushik Roy},
title = {Modeling and Analysis of Leakage Currents in Double-Gate Technologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2052--2061},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.873892},
doi = {10.1109/TCAD.2006.873892},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MukhopadhyayKCR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NamRAVK06,
author = {Gi{-}Joon Nam and
Sherief Reda and
Charles J. Alpert and
Paul Villarrubia and
Andrew B. Kahng},
title = {A Fast Hierarchical Quadratic Placement Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {4},
pages = {678--691},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870079},
doi = {10.1109/TCAD.2006.870079},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NamRAVK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NeophytouMT06,
author = {Stelios Neophytou and
Maria K. Michael and
Spyros Tragoudas},
title = {Functions for Quality Transition-Fault Tests and Their Applications
in Test-Set Enhancement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {3026--3035},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882635},
doi = {10.1109/TCAD.2006.882635},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NeophytouMT06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NieuwoudtM06,
author = {Arthur Nieuwoudt and
Yehia Massoud},
title = {Variability-Aware Multilevel Integrated Spiral Inductor Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2613--2625},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882475},
doi = {10.1109/TCAD.2006.882475},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NieuwoudtM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OikonomakosZ06,
author = {Petros Oikonomakos and
Mark Zwolinski},
title = {An Integrated High-Level On-Line Test Synthesis Tool},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2479--2491},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882120},
doi = {10.1109/TCAD.2006.882120},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OikonomakosZ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OzdalW06,
author = {Muhammet Mustafa Ozdal and
Martin D. F. Wong},
title = {Algorithmic study of single-layer bus routing for high-speed boards},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {490--503},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.853685},
doi = {10.1109/TCAD.2005.853685},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OzdalW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OzdalW06a,
author = {Muhammet Mustafa Ozdal and
Martin D. F. Wong},
title = {Algorithms for simultaneous escape routing and Layer assignment of
dense PCBs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {8},
pages = {1510--1522},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.857376},
doi = {10.1109/TCAD.2005.857376},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OzdalW06a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OzdalW06b,
author = {Muhammet Mustafa Ozdal and
Martin D. F. Wong},
title = {A Length-Matching Routing Algorithm for High-Performance Printed Circuit
Boards},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2784--2794},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882584},
doi = {10.1109/TCAD.2006.882584},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OzdalW06b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ParkMR06,
author = {Jongsun Park and
Khurram Muhammad and
Kaushik Roy},
title = {Efficient modeling of 1/f\({}^{\mbox{alpha}}\)/ noise using multirate
process},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1247--1256},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855953},
doi = {10.1109/TCAD.2005.855953},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ParkMR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PatelBMP06,
author = {Kimish Patel and
Luca Benini and
Enrico Macii and
Massimo Poncino},
title = {Reducing Conflict Misses by Application-Specific Reconfigurable Indexing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2626--2637},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882588},
doi = {10.1109/TCAD.2006.882588},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PatelBMP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PatelMBS06,
author = {Hiren D. Patel and
Deepak Mathaikutty and
David Berner and
Sandeep K. Shukla},
title = {{CARH:} service-oriented architecture for validating system-level
designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {8},
pages = {1458--1474},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.857315},
doi = {10.1109/TCAD.2005.857315},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PatelMBS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PengL06,
author = {Yuantao Peng and
Xun Liu},
title = {An Efficient Low-Power Repeater-Insertion Scheme},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2726--2736},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882601},
doi = {10.1109/TCAD.2006.882601},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PengL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PfeifferMH06,
author = {Anton J. Pfeiffer and
Tamal Mukherjee and
Steinar Hauan},
title = {Synthesis of Multiplexed Biofluidic Microchips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {2},
pages = {321--333},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855931},
doi = {10.1109/TCAD.2005.855931},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PfeifferMH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR06,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Scan-BIST based on transition probabilities for circuits with single
and multiple scan chains},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {591--596},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.854634},
doi = {10.1109/TCAD.2005.854634},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR06a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Transparent {DFT:} a design for testability and test generation approach
for synchronous sequential circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1170--1175},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855947},
doi = {10.1109/TCAD.2005.855947},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR06a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR06b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Generation of Functional Broadside Tests for Transition Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2207--2218},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.860959},
doi = {10.1109/TCAD.2005.860959},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR06b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR06c,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Using Dummy Bridging Faults to Define Reduced Sets of Target Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2219--2227},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.860951},
doi = {10.1109/TCAD.2005.860951},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR06c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR06d,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Improved n-Detection Test Sequences Under Transparent Scan},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2492--2501},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.881334},
doi = {10.1109/TCAD.2006.881334},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR06d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PozziAI06,
author = {Laura Pozzi and
Kubilay Atasu and
Paolo Ienne},
title = {Exact and approximate algorithms for the extension of embedded processor
instruction sets},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1209--1229},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855950},
doi = {10.1109/TCAD.2005.855950},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PozziAI06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/QiYLTH06,
author = {Zhenyu Qi and
Hao Yu and
Pu Liu and
Sheldon X.{-}D. Tan and
Lei He},
title = {Wideband passive multiport model order reduction and realization of
{RLCM} circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {8},
pages = {1496--1509},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855937},
doi = {10.1109/TCAD.2005.855937},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/QiYLTH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RadeckaZ06,
author = {Knockaert Radecka and
Zeljko Zilic},
title = {Arithmetic transforms for compositions of sequential and imprecise
datapaths},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1382--1391},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855935},
doi = {10.1109/TCAD.2005.855935},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RadeckaZ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RajaramHM06,
author = {Anand Rajaram and
Jiang Hu and
Rabi N. Mahapatra},
title = {Reducing clock skew variability via crosslinks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1176--1182},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855928},
doi = {10.1109/TCAD.2005.855928},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RajaramHM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RajaramLHMG06,
author = {Anand Rajaram and
Bing Lu and
Jiang Hu and
Rabi N. Mahapatra and
Wei Guo},
title = {Analytical bound for unwanted clock skew due to wire width variation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1869--1876},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.857398},
doi = {10.1109/TCAD.2005.857398},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RajaramLHMG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RaoDBS06,
author = {Rajeev R. Rao and
Anirudh Devgan and
David T. Blaauw and
Dennis Sylvester},
title = {Analytical yield prediction considering leakage/performance correlation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1685--1695},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.858351},
doi = {10.1109/TCAD.2005.858351},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RaoDBS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RaoV06,
author = {Ravishankar Rao and
Sarma B. K. Vrudhula},
title = {Energy-Optimal Speed Control of a Generic Device},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2737--2746},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882598},
doi = {10.1109/TCAD.2006.882598},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RaoV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RaychowdhuryR06,
author = {Arijit Raychowdhury and
Kaushik Roy},
title = {Modeling of metallic carbon-nanotube interconnects for circuit simulations
and a comparison with Cu interconnects for scaled technologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {58--65},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.853702},
doi = {10.1109/TCAD.2005.853702},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RaychowdhuryR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ReshadiGD06,
author = {Mehrdad Reshadi and
Bita Gorjiara and
Nikil D. Dutt},
title = {Generic Processor Modeling for Automatically Generating Very Fast
Cycle-Accurate Simulators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2904--2918},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882597},
doi = {10.1109/TCAD.2006.882597},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ReshadiGD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RongP06,
author = {Peng Rong and
Massoud Pedram},
title = {Battery-aware power management based on Markovian decision processes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1337--1349},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855975},
doi = {10.1109/TCAD.2005.855975},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RongP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RosingerAC06,
author = {Paul M. Rosinger and
Bashir M. Al{-}Hashimi and
Krishnendu Chakrabarty},
title = {Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated
Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2502--2512},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.873898},
doi = {10.1109/TCAD.2006.873898},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/RosingerAC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RoyAPM06,
author = {Jarrod A. Roy and
Saurabh N. Adya and
David A. Papa and
Igor L. Markov},
title = {Min-cut floorplacement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1313--1326},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855969},
doi = {10.1109/TCAD.2005.855969},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RoyAPM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RoychowdhuryM06,
author = {Jaijeet S. Roychowdhury and
Robert C. Melville},
title = {Delivering global {DC} convergence for large mixed-signal circuits
via homotopy/continuation methods},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {66--78},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.852461},
doi = {10.1109/TCAD.2005.852461},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RoychowdhuryM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Rubanov06,
author = {Nikolay Rubanov},
title = {A High-Performance Subcircuit Recognition Method Based on the Nonlinear
Graph Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2353--2363},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.881335},
doi = {10.1109/TCAD.2006.881335},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Rubanov06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Sasao06,
author = {Tsutomu Sasao},
title = {Analysis and synthesis of weighted-sum functions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {789--796},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870407},
doi = {10.1109/TCAD.2006.870407},
timestamp = {Mon, 07 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Sasao06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SassoneL06,
author = {Peter G. Sassone and
Sung Kyu Lim},
title = {Traffic: a novel geometric algorithm for fast wire-optimized floorplanning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1075--1086},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855921},
doi = {10.1109/TCAD.2005.855921},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SassoneL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Saxena06,
author = {Prashant Saxena},
title = {On controlling perturbation due to repeaters during quadratic placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1733--1743},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.858273},
doi = {10.1109/TCAD.2005.858273},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Saxena06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SelvakkumaranK06,
author = {Navaratnasothie Selvakkumaran and
George Karypis},
title = {Multiobjective hypergraph-partitioning algorithms for cut and maximum
subdomain-degree minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {504--517},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.854637},
doi = {10.1109/TCAD.2005.854637},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SelvakkumaranK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SeoKL06,
author = {Jaewon Seo and
Taewhan Kim and
Joonwon Lee},
title = {Optimal intratask dynamic voltage-scaling technique and its practical
extensions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {47--57},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.853703},
doi = {10.1109/TCAD.2005.853703},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SeoKL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShangPJ06,
author = {Li Shang and
Li{-}Shiuan Peh and
Niraj K. Jha},
title = {PowerHerd: a distributed scheme for dynamically satisfying peak-power
constraints in interconnection networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {92--110},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.852438},
doi = {10.1109/TCAD.2005.852438},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShangPJ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SharmaEH06,
author = {Akshay Sharma and
Carl Ebeling and
Scott Hauck},
title = {PipeRoute: a pipelining-aware router for reconfigurable architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {518--532},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.853691},
doi = {10.1109/TCAD.2005.853691},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SharmaEH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShelarSS06,
author = {Rupesh S. Shelar and
Prashant Saxena and
Sachin S. Sapatnekar},
title = {Technology Mapping Algorithm Targeting Routing Congestion Under Delay
Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {4},
pages = {625--636},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870078},
doi = {10.1109/TCAD.2006.870078},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShelarSS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShendeBM06,
author = {Vivek V. Shende and
Stephen S. Bullock and
Igor L. Markov},
title = {Synthesis of quantum-logic circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1000--1010},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855930},
doi = {10.1109/TCAD.2005.855930},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShendeBM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShiHS06,
author = {Guoyong Shi and
Bo Hu and
C.{-}J. Richard Shi},
title = {On symbolic model order reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1257--1272},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855887},
doi = {10.1109/TCAD.2005.855887},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShiHS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShiTS06,
author = {C.{-}J. Richard Shi and
Michael W. Tian and
Guoyong Shi},
title = {Efficient {DC} fault simulation of nonlinear analog circuits: one-step
relaxation and adaptive simulation continuation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1392--1400},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855884},
doi = {10.1109/TCAD.2005.855884},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShiTS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShinK06,
author = {Dongkun Shin and
Jihong Kim},
title = {Dynamic voltage scaling of mixed task sets in priority-driven systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {438--453},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.853706},
doi = {10.1109/TCAD.2005.853706},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShinK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SilveiraP06,
author = {Lu{\'{\i}}s Miguel Silveira and
Joel R. Phillips},
title = {Resampling Plans for Sample Point Selection in Multipoint Model-Order
Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2775--2783},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882477},
doi = {10.1109/TCAD.2006.882477},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SilveiraP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinghS06,
author = {Jaskirat Singh and
Sachin S. Sapatnekar},
title = {Partition-Based Algorithm for Power Grid Design Using Locality},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {4},
pages = {664--677},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870071},
doi = {10.1109/TCAD.2006.870071},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinghS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinhaZ06,
author = {Debjit Sinha and
Hai Zhou},
title = {Gate-size optimization under timing constraints for coupling-noise
reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1064--1074},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855932},
doi = {10.1109/TCAD.2005.855932},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinhaZ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinhaZ06a,
author = {Debjit Sinha and
Hai Zhou},
title = {Statistical Timing Analysis With Coupling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2965--2975},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882482},
doi = {10.1109/TCAD.2006.882482},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinhaZ06a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SongNBG06,
author = {Hui{-}Yuan Song and
Kundan Nepal and
R. Iris Bahar and
Joel Grodstein},
title = {Timing analysis for full-custom circuits using symbolic {DC} formulations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1815--1830},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.859510},
doi = {10.1109/TCAD.2005.859510},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SongNBG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/StratigopoulosM06,
author = {Haralampos{-}G. D. Stratigopoulos and
Yiorgos Makris},
title = {Concurrent detection of erroneous responses in linear analog circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {878--891},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855962},
doi = {10.1109/TCAD.2005.855962},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/StratigopoulosM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SuC06,
author = {Fei Su and
Krishnendu Chakrabarty},
title = {Defect Tolerance Based on Graceful Degradation and Dynamic Reconfiguration
for Digital Microfluidics-Based Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2944--2953},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882480},
doi = {10.1109/TCAD.2006.882480},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SuC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SuCF06,
author = {Fei Su and
Krishnendu Chakrabarty and
Richard B. Fair},
title = {Microfluidics-Based Biochips: Technology Issues, Implementation Platforms,
and Design-Automation Challenges},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {2},
pages = {211--223},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855956},
doi = {10.1109/TCAD.2005.855956},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SuCF06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SunRRJ06,
author = {Fei Sun and
Srivaths Ravi and
Anand Raghunathan and
Niraj K. Jha},
title = {Application-specific heterogeneous multiprocessor synthesis using
extensible processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1589--1602},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.858269},
doi = {10.1109/TCAD.2005.858269},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SunRRJ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SyalH06,
author = {Manan Syal and
Michael S. Hsiao},
title = {New techniques for untestable fault identification in sequential circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1117--1131},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855967},
doi = {10.1109/TCAD.2005.855967},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SyalH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TangD06,
author = {Hua Tang and
Alex Doboli},
title = {High-level synthesis of {\(\Delta\)}{\(\Sigma\)} Modulator topologies
optimized for complexity, sensitivity, and power consumption},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {597--607},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.854633},
doi = {10.1109/TCAD.2005.854633},
timestamp = {Tue, 27 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TangD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TangTW06,
author = {Xiaoping Tang and
Ruiqi Tian and
Martin D. F. Wong},
title = {Minimizing wire length in floorplanning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1744--1753},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.858266},
doi = {10.1109/TCAD.2005.858266},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TangTW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TangZD06,
author = {Hua Tang and
Hui Zhang and
Alex Doboli},
title = {Refinement-based synthesis of continuous-time analog filters through
successive domain pruning, plateau search, and adaptive sampling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {8},
pages = {1421--1440},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.857378},
doi = {10.1109/TCAD.2005.857378},
timestamp = {Mon, 27 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TangZD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TaskinK06,
author = {Baris Taskin and
Ivan S. Kourtev},
title = {Delay Insertion Method in Clock Skew Scheduling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {4},
pages = {651--663},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870072},
doi = {10.1109/TCAD.2006.870072},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TaskinK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TiriV06,
author = {Kris Tiri and
Ingrid Verbauwhede},
title = {A digital design flow for secure integrated circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1197--1208},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855939},
doi = {10.1109/TCAD.2005.855939},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TiriV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TuCJ06,
author = {Shang{-}Wei Tu and
Yao{-}Wen Chang and
Jing{-}Yang Jou},
title = {{RLC} Coupling-Aware Simulation and On-Chip Bus Encoding for Delay
Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2258--2264},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.860956},
doi = {10.1109/TCAD.2005.860956},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TuCJ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TuunaIT06,
author = {Sampo Tuuna and
Jouni Isoaho and
Hannu Tenhunen},
title = {Analytical model for crosstalk and intersymbol interference in point-to-point
buses},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1400--1410},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855973},
doi = {10.1109/TCAD.2005.855973},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TuunaIT06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/UmansVS06,
author = {Christopher Umans and
Tiziano Villa and
Alberto L. Sangiovanni{-}Vincentelli},
title = {Complexity of two-level logic minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1230--1246},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855944},
doi = {10.1109/TCAD.2005.855944},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/UmansVS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VasilyevRW06,
author = {Dmitry Vasilyev and
Michal Rewienski and
Jacob K. White},
title = {Macromodel Generation for BioMEMS Components Using a Stabilized Balanced
Truncation Plus Trajectory Piecewise-Linear Approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {2},
pages = {285--293},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.857389},
doi = {10.1109/TCAD.2005.857389},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VasilyevRW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VenkataramaniBCG06,
author = {Girish Venkataramani and
Tobias Bjerregaard and
Tiberiu Chelcea and
Seth Copen Goldstein},
title = {Hardware compilation of application-specific memory-access interconnect},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {756--771},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870411},
doi = {10.1109/TCAD.2006.870411},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VenkataramaniBCG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VermaWM06,
author = {Manish Verma and
Lars Wehmeyer and
Peter Marwedel},
title = {Cache-Aware Scratchpad-Allocation Algorithms for Energy-Constrained
Embedded Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2035--2051},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.859523},
doi = {10.1109/TCAD.2005.859523},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VermaWM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VisweswariahRKWNBPVH06,
author = {Chandramouli Visweswariah and
K. Ravindran and
Kerim Kalafala and
Steven G. Walker and
S. Narayan and
Daniel K. Beece and
Jeff Piaget and
Natesan Venkateswaran and
Jeffrey G. Hemmett},
title = {First-Order Incremental Block-Based Statistical Timing Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2170--2180},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.862751},
doi = {10.1109/TCAD.2005.862751},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VisweswariahRKWNBPVH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VrudhulaWG06,
author = {Sarma B. K. Vrudhula and
Janet Meiling Wang and
Praveen Ghanta},
title = {Hermite Polynomial Based Interconnect Analysis in the Presence of
Process Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2001--2011},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.862734},
doi = {10.1109/TCAD.2005.862734},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VrudhulaWG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Vygen06,
author = {Jens Vygen},
title = {Slack in static timing analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1876--1885},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.858348},
doi = {10.1109/TCAD.2005.858348},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Vygen06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangC06,
author = {Seongmoon Wang and
Srimat T. Chakradhar},
title = {A scalable scan-path test point insertion technique to enhance delay
fault coverage for standard scan designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {8},
pages = {1555--1564},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855929},
doi = {10.1109/TCAD.2005.855929},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangCTJ06,
author = {Hao Gang Wang and
Chi Hou Chan and
Leung Tsang and
Vikram Jandhyala},
title = {On sampling algorithms in multilevel {QR} factorization method for
magnetoquasistatic analysis of integrated circuits over multilayered
lossy substrates},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1777--1792},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.859534},
doi = {10.1109/TCAD.2005.859534},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangCTJ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangG06,
author = {Seongmoon Wang and
Sandeep K. Gupta},
title = {{LT-RTPG:} a new test-per-scan {BIST} {TPG} for low switching activity},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {8},
pages = {1565--1574},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855927},
doi = {10.1109/TCAD.2005.855927},
timestamp = {Fri, 22 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangKYAW06,
author = {Xin Wang and
Joe Kanapka and
Wenjing Ye and
Narayan R. Aluru and
Jacob White},
title = {Algorithms in FastStokes and Its Application to Micromachined Device
Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {2},
pages = {248--257},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855938},
doi = {10.1109/TCAD.2005.855938},
timestamp = {Sat, 29 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangKYAW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangLJHS06,
author = {Chao Wang and
Bing Li and
HoonSang Jin and
Gary D. Hachtel and
Fabio Somenzi},
title = {Improving Ariadne's Bundle by Following Multiple Threads in Abstraction
Refinement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2297--2316},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.873897},
doi = {10.1109/TCAD.2006.873897},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangLJHS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangLM06,
author = {Yi Wang and
Qiao Lin and
Tamal Mukherjee},
title = {Composable Behavioral Models and Schematic-Based Simulation of Electrokinetic
Lab-on-a-Chip Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {2},
pages = {258--273},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855942},
doi = {10.1109/TCAD.2005.855942},
timestamp = {Thu, 23 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangLM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangLYVM06,
author = {Janet Meiling Wang and
Jun Li and
Satish K. Yanamanamanda and
Lakshmi Kalpana Vakati and
Kishore Kumar Muchherla},
title = {Modeling the Driver Load in the Presence of Process Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2264--2275},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.862739},
doi = {10.1109/TCAD.2005.862739},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangLYVM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangMTR06,
author = {Zhiyuan Wang and
Malgorzata Marek{-}Sadowska and
Kun{-}Han Tsai and
Janusz Rajski},
title = {Analysis and methodology for multiple-fault diagnosis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {558--575},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.854624},
doi = {10.1109/TCAD.2005.854624},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangMTR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangO06,
author = {Wei{-}Shen Wang and
Michael Orshansky},
title = {Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations:
Theory and Implementation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2976--2988},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882585},
doi = {10.1109/TCAD.2006.882585},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangO06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangSABKB06,
author = {Gang Wang and
Satish Sivaswamy and
Cristinel Ababei and
Kia Bazargan and
Ryan Kastner and
Elaheh Bozorgzadeh},
title = {Statistical Analysis and Design of {HARP} FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2088--2102},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.859485},
doi = {10.1109/TCAD.2005.859485},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangSABKB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangYW06,
author = {Xiren Wang and
Wenjian Yu and
Zeyi Wang},
title = {Efficient Direct Boundary Element Method for Resistance Extraction
of Substrate With Arbitrary Doping Profile},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {3035--3042},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882487},
doi = {10.1109/TCAD.2006.882487},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangYW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WessnerCHHS06,
author = {W. Wessner and
Johann Cervenka and
Clemens Heitzinger and
Andreas H{\"{o}}ssinger and
Siegfried Selberherr},
title = {Anisotropic Mesh Refinement for the Simulation of Three-Dimensional
Semiconductor Manufacturing Processes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2129--2139},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.862750},
doi = {10.1109/TCAD.2005.862750},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WessnerCHHS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WongBKN06,
author = {Ngai Wong and
Venkataramanan Balakrishnan and
Cheng{-}Kok Koh and
Tung{-}Sang Ng},
title = {Two Algorithms for Fast and Accurate Passivity-Preserving Model Order
Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2062--2075},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.873893},
doi = {10.1109/TCAD.2006.873893},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WongBKN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WongDKSP06,
author = {Jennifer L. Wong and
Azadeh Davoodi and
Vishal Khandelwal and
Ankur Srivastava and
Miodrag Potkonjak},
title = {A statistical methodology for wire-length prediction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1327--1336},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855885},
doi = {10.1109/TCAD.2005.855885},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WongDKSP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuH06,
author = {Qingwei Wu and
Michael S. Hsiao},
title = {State Variable Extraction and Partitioning to Reduce Problem Complexity
for {ATPG} and Design Validation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2275--2282},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.859512},
doi = {10.1109/TCAD.2005.859512},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuHM06,
author = {Di Wu and
Jiang Hu and
Rabi N. Mahapatra},
title = {Antenna Avoidance in Layer Assignment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {4},
pages = {734--738},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.870061},
doi = {10.1109/TCAD.2006.870061},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuHM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuK06,
author = {Kaijie Wu and
Ramesh Karri},
title = {Algorithm-level recomputing with shifted operands-a register transfer
level concurrent error detection technique},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {413--422},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.853694},
doi = {10.1109/TCAD.2005.853694},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WuK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuZN06,
author = {Bin Wu and
Jianwen Zhu and
Farid N. Najm},
title = {Dynamic-range estimation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1618--1636},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.859507},
doi = {10.1109/TCAD.2005.859507},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuZN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XiangCW06,
author = {Hua Xiang and
Kai{-}Yuan Chao and
Martin D. F. Wong},
title = {An {ECO} routing algorithm for eliminating coupling-capacitance violations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1754--1762},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.857396},
doi = {10.1109/TCAD.2005.857396},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XiangCW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuFM06,
author = {Chenggang Xu and
Terri S. Fiez and
Kartikeya Mayaram},
title = {An error control method for application of the discrete cosine transform
to extraction of substrate parasitics in ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {932--938},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855959},
doi = {10.1109/TCAD.2005.855959},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XuFM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuN06,
author = {Qiang Xu and
Nicola Nicolici},
title = {Multifrequency {TAM} design for hierarchical SOCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {181--196},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.852440},
doi = {10.1109/TCAD.2005.852440},
timestamp = {Thu, 30 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XuN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YanSS06,
author = {Shu Yan and
Vivek Sarin and
Weiping Shi},
title = {Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2282--2286},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.862747},
doi = {10.1109/TCAD.2005.862747},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YanSS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangP06,
author = {Shih{-}Yu Yang and
Christos A. Papachristou},
title = {A method for detecting interconnect {DSM} defects in systems on chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {197--204},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.853707},
doi = {10.1109/TCAD.2005.853707},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangWK06,
author = {Bo Yang and
Kaijie Wu and
Ramesh Karri},
title = {Secure Scan: {A} Design-for-Test Architecture for Crypto Chips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2287--2293},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.862745},
doi = {10.1109/TCAD.2005.862745},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangWK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangWWI06,
author = {Josh Yang and
Baosheng Wang and
Yuejian Wu and
Andr{\'{e}} Ivanov},
title = {Fast detection of data retention faults and other {SRAM} cell open
defects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {167--180},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.852680},
doi = {10.1109/TCAD.2005.852680},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangWWI06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YiH06,
author = {Joonhwan Yi and
John P. Hayes},
title = {High-level delay test generation for modular circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {576--590},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.853697},
doi = {10.1109/TCAD.2005.853697},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YiH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YiW06,
author = {Ying Yi and
Roger F. Woods},
title = {Hierarchical synthesis of complex {DSP} functions using {IRIS}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {806--820},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855957},
doi = {10.1109/TCAD.2005.855957},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YiW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YoonBD06,
author = {Sungroh Yoon and
Luca Benini and
Giovanni De Micheli},
title = {A Pattern-Mining Method for High-Throughput Lab-on-a-Chip Data Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {2},
pages = {358--377},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855960},
doi = {10.1109/TCAD.2005.855960},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YoonBD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuZW06,
author = {Wenjian Yu and
Mengsheng Zhang and
Zeyi Wang},
title = {Efficient 3-D extraction of interconnect capacitance considering floating
metal fills with boundary element method},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {12--18},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.853690},
doi = {10.1109/TCAD.2005.853690},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuZW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Zeng06,
author = {Jun Zeng},
title = {Modeling and Simulation of Electrified Droplets and Its Application
to Computer-Aided Design of Digital Microfluidics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {2},
pages = {224--233},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.857387},
doi = {10.1109/TCAD.2005.857387},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Zeng06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZengHAC06,
author = {Xiangyin Zeng and
Jiangqi He and
M. N. Abdulla and
Qing{-}Lun Chen},
title = {Understanding and closed-form-formula determination of frequency-dependent
bonding-pad characterization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1696--1704},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.858263},
doi = {10.1109/TCAD.2005.858263},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZengHAC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZengRG06,
author = {Annie (Yujuan) Zeng and
Kenneth Rose and
Ronald J. Gutmann},
title = {Memory performance prediction for high-performance microprocessors
at deep submicrometer technologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {9},
pages = {1705--1718},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.858346},
doi = {10.1109/TCAD.2005.858346},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZengRG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangC06,
author = {Ying Zhang and
Krishnendu Chakrabarty},
title = {A unified approach for fault tolerance and dynamic power management
in fixed-priority real-time embedded systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {111--125},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.852657},
doi = {10.1109/TCAD.2005.852657},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhangC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangCHC06,
author = {Lizheng Zhang and
Weijen Chen and
Yuhen Hu and
Charlie Chung{-}Ping Chen},
title = {Statistical static timing analysis with conditional linear {MAX/MIN}
approximation and extended canonical timing model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1183--1191},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855979},
doi = {10.1109/TCAD.2005.855979},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhangCHC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangCHGC06,
author = {Lizheng Zhang and
Weijen Chen and
Yuhen Hu and
John A. Gubner and
Charlie Chung{-}Ping Chen},
title = {Correlation-Preserved Statistical Timing With a Quadratic Form of
Gaussian Variables},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2437--2449},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.873885},
doi = {10.1109/TCAD.2006.873885},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhangCHGC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangCMB06,
author = {Jin S. Zhang and
Malgorzata Chrzanowska{-}Jeske and
Alan Mishchenko and
Jerry R. Burch},
title = {Linear cofactor relationships in Boolean functions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1011--1023},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855951},
doi = {10.1109/TCAD.2005.855951},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhangCMB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangGH06,
author = {Liang Zhang and
Indradeep Ghosh and
Michael S. Hsiao},
title = {A Framework for Automatic Design Validation of {RTL} Circuits Using
{ATPG} and Observability-Enhanced Tag Coverage},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2526--2538},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.881333},
doi = {10.1109/TCAD.2006.881333},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhangGH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangRJK06,
author = {Lihong Zhang and
Rabin Raut and
Yingtao Jiang and
Ulrich Kleine},
title = {Placement Algorithm in Analog-Layout Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {1889--1903},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.860957},
doi = {10.1109/TCAD.2005.860957},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhangRJK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangS06,
author = {Ming Zhang and
Naresh R. Shanbhag},
title = {Soft-Error-Rate-Analysis {(SERA)} Methodology},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2140--2155},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.862738},
doi = {10.1109/TCAD.2005.862738},
timestamp = {Wed, 25 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhangS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoFZSP06,
author = {Min Zhao and
Yuhong Fu and
Vladimir Zolotov and
Savithri Sundareswaran and
Rajendran Panda},
title = {Optimal placement of power-supply pads and pins},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {144--154},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.852459},
doi = {10.1109/TCAD.2005.852459},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoFZSP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoUM06,
author = {Dan Zhao and
Shambhu J. Upadhyaya and
Martin Margala},
title = {Design of a wireless test control network with radio-on-chip technology
for nanometer system-on-a-chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {7},
pages = {1411--1418},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855919},
doi = {10.1109/TCAD.2005.855919},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoUM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhengMWLY06,
author = {Hao Zheng and
Chris J. Myers and
David Walter and
Scott Little and
Tomohiro Yoneda},
title = {Verification of timed circuits with failure-directed abstractions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {403--412},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.854638},
doi = {10.1109/TCAD.2005.854638},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhengMWLY06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhongRRJ06,
author = {Lin Zhong and
Srivaths Ravi and
Anand Raghunathan and
Niraj K. Jha},
title = {RTL-Aware Cycle-Accurate Functional Power Estimation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2103--2117},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.859504},
doi = {10.1109/TCAD.2005.859504},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhongRRJ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhouM06,
author = {Quming Zhou and
Kartik Mohanram},
title = {Gate sizing to radiation harden combinational logic},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {155--166},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.853696},
doi = {10.1109/TCAD.2005.853696},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhouM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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