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@article{DBLP:journals/sigarch/AggarwalBZ07,
  author       = {Aneesh Aggarwal and
                  Pradip Bose and
                  Mohamed Zahran},
  title        = {Introduction to the special issue on the 2006 reconfigurable and adaptive
                  architecture workshop},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {3},
  pages        = {1},
  year         = {2007},
  url          = {https://doi.org/10.1145/1294313.1294317},
  doi          = {10.1145/1294313.1294317},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/AggarwalBZ07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/BardineFGPS07,
  author       = {Alessandro Bardine and
                  Pierfrancesco Foglia and
                  Giacomo Gabrielli and
                  Cosimo Antonio Prete and
                  Per Stenstr{\"{o}}m},
  title        = {Improving power efficiency of {D-NUCA} caches},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {4},
  pages        = {53--58},
  year         = {2007},
  url          = {https://doi.org/10.1145/1327312.1327321},
  doi          = {10.1145/1327312.1327321},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/BardineFGPS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/BartoliniFP07,
  author       = {Sandro Bartolini and
                  Pierfrancesco Foglia and
                  Cosimo Antonio Prete},
  title        = {MEmory performance: DEaling with applications, systems and architecture},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {4},
  pages        = {4--5},
  year         = {2007},
  url          = {https://doi.org/10.1145/1327312.1327314},
  doi          = {10.1145/1327312.1327314},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/BartoliniFP07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/BellasCDL07,
  author       = {Nikolaos Bellas and
                  Sek M. Chai and
                  Malcolm Dwyer and
                  Dan Linzmeier},
  title        = {Mapping streaming architectures on reconfigurable platforms},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {3},
  pages        = {2--8},
  year         = {2007},
  url          = {https://doi.org/10.1145/1294313.1294318},
  doi          = {10.1145/1294313.1294318},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/BellasCDL07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/DerisB07,
  author       = {Kaveh Jokar Deris and
                  Amirali Baniasadi},
  title        = {Investigating cache energy and latency break-even points in high performance
                  processors},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {4},
  pages        = {13--20},
  year         = {2007},
  url          = {https://doi.org/10.1145/1327312.1327316},
  doi          = {10.1145/1327312.1327316},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/DerisB07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/DybdahlSN07,
  author       = {Haakon Dybdahl and
                  Per Stenstr{\"{o}}m and
                  Lasse Natvig},
  title        = {An LRU-based replacement algorithm augmented with frequency of access
                  in shared chip-multiprocessor caches},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {4},
  pages        = {45--52},
  year         = {2007},
  url          = {https://doi.org/10.1145/1327312.1327320},
  doi          = {10.1145/1327312.1327320},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/DybdahlSN07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/FerriMBBH07,
  author       = {Cesare Ferri and
                  Tali Moreshet and
                  R. Iris Bahar and
                  Luca Benini and
                  Maurice Herlihy},
  title        = {A hardware/software framework for supporting transactional memory
                  in a MPSoC environment},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {47--54},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241611},
  doi          = {10.1145/1241601.1241611},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/FerriMBBH07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Gove07,
  author       = {Darryl Gove},
  title        = {{CPU2006} working set size},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {90--96},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241619},
  doi          = {10.1145/1241601.1241619},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Gove07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/GoveS07,
  author       = {Darryl Gove and
                  Lawrence Spracklen},
  title        = {Evaluating the correspondence between training and reference workloads
                  in {SPEC} {CPU2006}},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {122--129},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241624},
  doi          = {10.1145/1241601.1241624},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/GoveS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/GuoKZIINSK07,
  author       = {Fei Guo and
                  Hari Kannan and
                  Li Zhao and
                  Ramesh Illikkal and
                  Ravi R. Iyer and
                  Don Newell and
                  Yan Solihin and
                  Christos Kozyrakis},
  title        = {From chaos to QoS: case studies in {CMP} resource management},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {21--30},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241608},
  doi          = {10.1145/1241601.1241608},
  timestamp    = {Mon, 15 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/GuoKZIINSK07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Henning07,
  author       = {John L. Henning},
  title        = {Guest editor's introduction},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {63--64},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241614},
  doi          = {10.1145/1241601.1241614},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Henning07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Henning07a,
  author       = {John L. Henning},
  title        = {{SPEC} {CPU} suite growth: an historical perspective},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {65--68},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241615},
  doi          = {10.1145/1241601.1241615},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Henning07a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Henning07b,
  author       = {John L. Henning},
  title        = {{SPEC} {CPU2006} memory footprint},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {84--89},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241618},
  doi          = {10.1145/1241601.1241618},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Henning07b.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Henning07c,
  author       = {John L. Henning},
  title        = {Performance counters and development of {SPEC} {CPU2006}},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {118--121},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241623},
  doi          = {10.1145/1241601.1241623},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Henning07c.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/IrieSGS07,
  author       = {Hidetsugu Irie and
                  Ken Sugimoto and
                  Masahiro Goshima and
                  Shuichi Sakai},
  title        = {Preventing timing errors on register writes: mechanisms of detections
                  and recoveries},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {5},
  pages        = {25--31},
  year         = {2007},
  url          = {https://doi.org/10.1145/1360464.1360473},
  doi          = {10.1145/1360464.1360473},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/IrieSGS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/KiseSN07,
  author       = {Kenji Kise and
                  Toshinori Sato and
                  Hironori Nakajo},
  title        = {Introduction},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {5},
  pages        = {1--2},
  year         = {2007},
  url          = {https://doi.org/10.1145/1360464.1360469},
  doi          = {10.1145/1360464.1360469},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/KiseSN07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/KondoSN07,
  author       = {Masaaki Kondo and
                  Hiroshi Sasaki and
                  Hiroshi Nakamura},
  title        = {Improving fairness, throughput and energy-efficiency on a chip multiprocessor
                  through {DVFS}},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {31--38},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241609},
  doi          = {10.1145/1241601.1241609},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/KondoSN07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/KornC07,
  author       = {Wendy Korn and
                  Moon S. Chang},
  title        = {{SPEC} {CPU2006} sensitivity to memory page sizes},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {97--101},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241620},
  doi          = {10.1145/1241601.1241620},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/KornC07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/LabrecqueYS07,
  author       = {Martin Labrecque and
                  Peter Yiannacouras and
                  J. Gregory Steffan},
  title        = {Custom code generation for soft processors},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {3},
  pages        = {9--19},
  year         = {2007},
  url          = {https://doi.org/10.1145/1294313.1294319},
  doi          = {10.1145/1294313.1294319},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/LabrecqueYS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/LakshmikanthanN07,
  author       = {Preetham Lakshmikanthan and
                  Adrian Nunez},
  title        = {{VCLEARIT:} a {VLSI} {CMOS} circuit leakage reduction technique for
                  nanoscale technologies},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {5},
  pages        = {10--16},
  year         = {2007},
  url          = {https://doi.org/10.1145/1360464.1360471},
  doi          = {10.1145/1360464.1360471},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/LakshmikanthanN07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/LortonW07,
  author       = {K. Patrick Lorton and
                  David S. Wise},
  title        = {Analyzing block locality in Morton-order and Morton-hybrid matrices},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {4},
  pages        = {6--12},
  year         = {2007},
  url          = {https://doi.org/10.1145/1327312.1327315},
  doi          = {10.1145/1327312.1327315},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/LortonW07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/MahesriWP07,
  author       = {Aqeel Mahesri and
                  Nicholas J. Wang and
                  Sanjay J. Patel},
  title        = {Hardware support for software controlled multithreading},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {3--12},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241606},
  doi          = {10.1145/1241601.1241606},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/MahesriWP07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/MalitaST07,
  author       = {Mihaela Malita and
                  Gheorghe Stefan and
                  Dominique Thi{\'{e}}baut},
  title        = {Not multi-, but many-core: designing integral parallel architectures
                  for embedded computation},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {5},
  pages        = {32--38},
  year         = {2007},
  url          = {https://doi.org/10.1145/1360464.1360474},
  doi          = {10.1145/1360464.1360474},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/MalitaST07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/MiyoshiS07,
  author       = {Takefumi Miyoshi and
                  Nobuhiko Sugino},
  title        = {Fine-grain compensation method with consideration of trade-offs between
                  computation and data transfer for power consumption},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {5},
  pages        = {39--44},
  year         = {2007},
  url          = {https://doi.org/10.1145/1360464.1360475},
  doi          = {10.1145/1360464.1360475},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/MiyoshiS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Najaf-abadiR07,
  author       = {Hashem Hashemi Najaf{-}abadi and
                  Eric Rotenberg},
  title        = {Architectural \emph{contesting}: exposing and exploiting temperamental
                  behavior},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {3},
  pages        = {28--35},
  year         = {2007},
  url          = {https://doi.org/10.1145/1294313.1294321},
  doi          = {10.1145/1294313.1294321},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Najaf-abadiR07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/PhansalkarJJ07,
  author       = {Aashish Phansalkar and
                  Ajay Joshi and
                  Lizy K. John},
  title        = {Subsetting the {SPEC} {CPU2006} benchmark suite},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {69--76},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241616},
  doi          = {10.1145/1241601.1241616},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/PhansalkarJJ07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/RamirezPSV07,
  author       = {Tanaus{\'{u}} Ram{\'{\i}}rez and
                  Alex Pajuelo and
                  Oliverio J. Santana and
                  Mateo Valero},
  title        = {Energy saving through a simple load control mechanism},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {4},
  pages        = {29--36},
  year         = {2007},
  url          = {https://doi.org/10.1145/1327312.1327318},
  doi          = {10.1145/1327312.1327318},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/RamirezPSV07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/RamosBIV07,
  author       = {Luis M. Ramos and
                  Jos{\'{e}} Luis Briz and
                  Pablo E. Ib{\'{a}}{\~{n}}ez and
                  V{\'{\i}}ctor Vi{\~{n}}als},
  title        = {Data prefetching in a cache hierarchy with high bandwidth and capacity},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {4},
  pages        = {37--44},
  year         = {2007},
  url          = {https://doi.org/10.1145/1327312.1327319},
  doi          = {10.1145/1327312.1327319},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/RamosBIV07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/RomanescuBOS07,
  author       = {Bogdan F. Romanescu and
                  Michael E. Bauer and
                  Sule Ozev and
                  Daniel J. Sorin},
  title        = {VariaSim: simulating circuits and systems in the presence of process
                  variability},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {5},
  pages        = {45--48},
  year         = {2007},
  url          = {https://doi.org/10.1145/1360464.1360465},
  doi          = {10.1145/1360464.1360465},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/RomanescuBOS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/RulVB07,
  author       = {Sean Rul and
                  Hans Vandierendonck and
                  Koen De Bosschere},
  title        = {Function level parallelism driven by data dependencies},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {55--62},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241612},
  doi          = {10.1145/1241601.1241612},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/RulVB07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/ShiSPXY07,
  author       = {Xudong Shi and
                  Feiqi Su and
                  Jih{-}Kwon Peir and
                  Ye Xia and
                  Zhen Yang},
  title        = {{CMP} cache performance projection: accessibility vs. capacity},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {13--20},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241607},
  doi          = {10.1145/1241601.1241607},
  timestamp    = {Wed, 22 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/sigarch/ShiSPXY07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Sibai07,
  author       = {Fadi N. Sibai},
  title        = {Performance analysis and workload characterization of the 3DMark05
                  benchmark on modern parallel computer platforms},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {3},
  pages        = {44--52},
  year         = {2007},
  url          = {https://doi.org/10.1145/1294313.1294315},
  doi          = {10.1145/1294313.1294315},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Sibai07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Spradling07,
  author       = {Cloyce D. Spradling},
  title        = {{SPEC} {CPU2006} benchmark tools},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {130--134},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241625},
  doi          = {10.1145/1241601.1241625},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Spradling07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/SridharSB07,
  author       = {Swaroop Sridhar and
                  Jonathan S. Shapiro and
                  Prashanth P. Bungale},
  title        = {HDTrans: a low-overhead dynamic translator},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {135--140},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241602},
  doi          = {10.1145/1241601.1241602},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/SridharSB07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Suri07,
  author       = {Tameesh Suri},
  title        = {Improving instruction level parallelism through reconfigurable units
                  in superscalar processors},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {3},
  pages        = {20--27},
  year         = {2007},
  url          = {https://doi.org/10.1145/1294313.1294320},
  doi          = {10.1145/1294313.1294320},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Suri07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/TanakaK07,
  author       = {Kiyofumi Tanaka and
                  Takahiro Kawahara},
  title        = {Leakage energy reduction in cache memory by data compression},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {5},
  pages        = {17--24},
  year         = {2007},
  url          = {https://doi.org/10.1145/1360464.1360472},
  doi          = {10.1145/1360464.1360472},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/TanakaK07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Thorson07,
  author       = {Mark Thorson},
  title        = {Internet nuggets},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {149--154},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241627},
  doi          = {10.1145/1241601.1241627},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Thorson07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Thorson07a,
  author       = {Mark Thorson},
  title        = {Internet nuggets},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {3},
  pages        = {53--55},
  year         = {2007},
  url          = {https://doi.org/10.1145/1294313.1294323},
  doi          = {10.1145/1294313.1294323},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Thorson07a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Thorson07b,
  author       = {Mark Thorson},
  title        = {Internet nuggets},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {4},
  pages        = {59--62},
  year         = {2007},
  url          = {https://doi.org/10.1145/1327312.1327323},
  doi          = {10.1145/1327312.1327323},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Thorson07b.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Thorson07c,
  author       = {Mark Thorson},
  title        = {Internet nuggets},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {5},
  pages        = {71--73},
  year         = {2007},
  url          = {https://doi.org/10.1145/1360464.1360477},
  doi          = {10.1145/1360464.1360477},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Thorson07c.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/TsengLLL07,
  author       = {Kuo{-}Kun Tseng and
                  Ying{-}Dar Lin and
                  Tsern{-}Huei Lee and
                  Yuan{-}Cheng Lai},
  title        = {Deterministic high-speed root-hashing automaton matching coprocessor
                  for embedded network processor},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {3},
  pages        = {36--43},
  year         = {2007},
  url          = {https://doi.org/10.1145/1294313.1294314},
  doi          = {10.1145/1294313.1294314},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/TsengLLL07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/TullsenKJ07,
  author       = {Dean M. Tullsen and
                  Rakesh Kumar and
                  Norman P. Jouppi},
  title        = {Introduction to the special issue on the 2006 workshop on design,
                  analysis, and simulation of chip multiprocessors: (dasCMP'06)},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {2},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241605},
  doi          = {10.1145/1241601.1241605},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/TullsenKJ07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/VenkateswaranSMSGECRVBS07,
  author       = {Nagarajan Venkateswaran and
                  Deepak Srinivasan and
                  Madhavan Manivannan and
                  T. P. Ramnath Sai Sagar and
                  Shyamsundar Gopalakrishnan and
                  Vinoth Krishnan Elangovan and
                  Karthik Chandrasekar and
                  Prem Kumar Ramesh and
                  Viswanath Venkatesan and
                  Arvindakshan Babu and
                  Sudharshan},
  title        = {Future generation supercomputers {I:} a paradigm for node architecture},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {5},
  pages        = {49--60},
  year         = {2007},
  url          = {https://doi.org/10.1145/1360464.1360466},
  doi          = {10.1145/1360464.1360466},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/VenkateswaranSMSGECRVBS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/VenkateswaranSMSGEMRGKS07,
  author       = {Nagarajan Venkateswaran and
                  Deepak Srinivasan and
                  Madhavan Manivannan and
                  T. P. Ramnath Sai Sagar and
                  Shyamsundar Gopalakrishnan and
                  Vinoth Krishnan Elangovan and
                  Arvind M and
                  Prem Kumar Ramesh and
                  Karthik Ganesan and
                  Viswanath Krishnamurthy and
                  Sivaramakrishnan},
  title        = {Future generation supercomputers {II:} a paradigm for cluster architecture},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {5},
  pages        = {61--70},
  year         = {2007},
  url          = {https://doi.org/10.1145/1360464.1360467},
  doi          = {10.1145/1360464.1360467},
  timestamp    = {Thu, 10 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/sigarch/VenkateswaranSMSGEMRGKS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/WaliullahS07,
  author       = {M. M. Waliullah and
                  Per Stenstr{\"{o}}m},
  title        = {Starvation-free commit arbitration policies for transactional memory
                  systems},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {39--46},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241610},
  doi          = {10.1145/1241601.1241610},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/WaliullahS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/WeickerH07,
  author       = {Reinhold Weicker and
                  John L. Henning},
  title        = {Subroutine profiling results for the {CPU2006} benchmarks},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {102--111},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241621},
  doi          = {10.1145/1241601.1241621},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/WeickerH07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Wong07,
  author       = {Michael Wong},
  title        = {{C++} benchmarks in {SPEC} {CPU2006}},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {77--83},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241617},
  doi          = {10.1145/1241601.1241617},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Wong07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/YanZ07,
  author       = {Jun Yan and
                  Wei Zhang},
  title        = {Hybrid multi-core architecture for boosting single-threaded performance},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {141--148},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241603},
  doi          = {10.1145/1241601.1241603},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/YanZ07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/YanZ07a,
  author       = {Jun Yan and
                  Wei Zhang},
  title        = {Evaluating instruction cache vulnerability to transient errors},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {4},
  pages        = {21--28},
  year         = {2007},
  url          = {https://doi.org/10.1145/1327312.1327317},
  doi          = {10.1145/1327312.1327317},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/YanZ07a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/YaoMST07,
  author       = {Jun Yao and
                  Shinobu Miwa and
                  Hajime Shimada and
                  Shinji Tomita},
  title        = {Optimal pipeline depth with pipeline stage unification adoption},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {5},
  pages        = {3--9},
  year         = {2007},
  url          = {https://doi.org/10.1145/1360464.1360470},
  doi          = {10.1145/1360464.1360470},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/YaoMST07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/YeRK07,
  author       = {Dong Ye and
                  Joydeep Ray and
                  David R. Kaeli},
  title        = {Characterization of file {I/O} activity for {SPEC} {CPU2006}},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {35},
  number       = {1},
  pages        = {112--117},
  year         = {2007},
  url          = {https://doi.org/10.1145/1241601.1241622},
  doi          = {10.1145/1241601.1241622},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/YeRK07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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