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Publication search results
found 51 matches
- 2007
- Aneesh Aggarwal, Pradip Bose, Mohamed Zahran:
Introduction to the special issue on the 2006 reconfigurable and adaptive architecture workshop. SIGARCH Comput. Archit. News 35(3): 1 (2007) - Alessandro Bardine, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström:
Improving power efficiency of D-NUCA caches. SIGARCH Comput. Archit. News 35(4): 53-58 (2007) - Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete:
MEmory performance: DEaling with applications, systems and architecture. SIGARCH Comput. Archit. News 35(4): 4-5 (2007) - Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier:
Mapping streaming architectures on reconfigurable platforms. SIGARCH Comput. Archit. News 35(3): 2-8 (2007) - Kaveh Jokar Deris, Amirali Baniasadi:
Investigating cache energy and latency break-even points in high performance processors. SIGARCH Comput. Archit. News 35(4): 13-20 (2007) - Haakon Dybdahl, Per Stenström, Lasse Natvig:
An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches. SIGARCH Comput. Archit. News 35(4): 45-52 (2007) - Cesare Ferri, Tali Moreshet, R. Iris Bahar, Luca Benini, Maurice Herlihy:
A hardware/software framework for supporting transactional memory in a MPSoC environment. SIGARCH Comput. Archit. News 35(1): 47-54 (2007) - Darryl Gove:
CPU2006 working set size. SIGARCH Comput. Archit. News 35(1): 90-96 (2007) - Darryl Gove, Lawrence Spracklen:
Evaluating the correspondence between training and reference workloads in SPEC CPU2006. SIGARCH Comput. Archit. News 35(1): 122-129 (2007) - Fei Guo, Hari Kannan, Li Zhao, Ramesh Illikkal, Ravi R. Iyer, Don Newell, Yan Solihin, Christos Kozyrakis:
From chaos to QoS: case studies in CMP resource management. SIGARCH Comput. Archit. News 35(1): 21-30 (2007) - John L. Henning:
Guest editor's introduction. SIGARCH Comput. Archit. News 35(1): 63-64 (2007) - John L. Henning:
SPEC CPU suite growth: an historical perspective. SIGARCH Comput. Archit. News 35(1): 65-68 (2007) - John L. Henning:
SPEC CPU2006 memory footprint. SIGARCH Comput. Archit. News 35(1): 84-89 (2007) - John L. Henning:
Performance counters and development of SPEC CPU2006. SIGARCH Comput. Archit. News 35(1): 118-121 (2007) - Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima, Shuichi Sakai:
Preventing timing errors on register writes: mechanisms of detections and recoveries. SIGARCH Comput. Archit. News 35(5): 25-31 (2007) - Kenji Kise, Toshinori Sato, Hironori Nakajo:
Introduction. SIGARCH Comput. Archit. News 35(5): 1-2 (2007) - Masaaki Kondo, Hiroshi Sasaki, Hiroshi Nakamura:
Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS. SIGARCH Comput. Archit. News 35(1): 31-38 (2007) - Wendy Korn, Moon S. Chang:
SPEC CPU2006 sensitivity to memory page sizes. SIGARCH Comput. Archit. News 35(1): 97-101 (2007) - Martin Labrecque, Peter Yiannacouras, J. Gregory Steffan:
Custom code generation for soft processors. SIGARCH Comput. Archit. News 35(3): 9-19 (2007) - Preetham Lakshmikanthan, Adrian Nunez:
VCLEARIT: a VLSI CMOS circuit leakage reduction technique for nanoscale technologies. SIGARCH Comput. Archit. News 35(5): 10-16 (2007) - K. Patrick Lorton, David S. Wise:
Analyzing block locality in Morton-order and Morton-hybrid matrices. SIGARCH Comput. Archit. News 35(4): 6-12 (2007) - Aqeel Mahesri, Nicholas J. Wang, Sanjay J. Patel:
Hardware support for software controlled multithreading. SIGARCH Comput. Archit. News 35(1): 3-12 (2007) - Mihaela Malita, Gheorghe Stefan, Dominique Thiébaut:
Not multi-, but many-core: designing integral parallel architectures for embedded computation. SIGARCH Comput. Archit. News 35(5): 32-38 (2007) - Takefumi Miyoshi, Nobuhiko Sugino:
Fine-grain compensation method with consideration of trade-offs between computation and data transfer for power consumption. SIGARCH Comput. Archit. News 35(5): 39-44 (2007) - Hashem Hashemi Najaf-abadi, Eric Rotenberg:
Architectural contesting: exposing and exploiting temperamental behavior. SIGARCH Comput. Archit. News 35(3): 28-35 (2007) - Aashish Phansalkar, Ajay Joshi, Lizy K. John:
Subsetting the SPEC CPU2006 benchmark suite. SIGARCH Comput. Archit. News 35(1): 69-76 (2007) - Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero:
Energy saving through a simple load control mechanism. SIGARCH Comput. Archit. News 35(4): 29-36 (2007) - Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals:
Data prefetching in a cache hierarchy with high bandwidth and capacity. SIGARCH Comput. Archit. News 35(4): 37-44 (2007) - Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin:
VariaSim: simulating circuits and systems in the presence of process variability. SIGARCH Comput. Archit. News 35(5): 45-48 (2007) - Sean Rul, Hans Vandierendonck, Koen De Bosschere:
Function level parallelism driven by data dependencies. SIGARCH Comput. Archit. News 35(1): 55-62 (2007)
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