"Logic Synthesis with NAND (or NOR) Gates in Multi-levels."

Saburo Muroga (1999)

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DOI: 10.1201/9781420049671.CH31

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type: Reference Work

metadata version: 2017-07-12

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Saburo Muroga:
Logic Synthesis with NAND (or NOR) Gates in Multi-levels. The VLSI Handbook 1999

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