"A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold ..."

Chua-Chin Wang et al. (2008)

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DOI: 10.1109/TVLSI.2008.917561

access: closed

type: Journal Article

metadata version: 2020-03-11

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Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng:
A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic. IEEE Trans. Very Large Scale Integr. Syst. 16(5): 594-598 (2008)

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