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"Multilevel hypergraph partitioning: applications in VLSI domain."

George Karypis et al. (1999)

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DOI: 10.1109/92.748202

access: closed

type: Journal Article

metadata version: 2021-11-08

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  - journals/tvlsi/KarypisAKS99
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  - https://dblp.org/rec/journals/tvlsi/KarypisAKS99
George Karypis, Rajat Aggarwal, Vipin Kumar, Shashi Shekhar:
Multilevel hypergraph partitioning: applications in VLSI domain. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 69-79 (1999)

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