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ORCIDRajat Aggarwal
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2010 – 2019
- 2017
[c13]Stephen Yang, Chandra Mulpuri, Sainath Reddy, Meghraj Kalase, Srinivasan Dasasathyan, Mehrdad E. Dehkordi, Marvin Tom, Rajat Aggarwal:
Clock-Aware FPGA Placement Contest. ISPD 2017: 159-164- 2016
- [c12]Rajat Aggarwal, Amrisha Vohra, Anoop M. Namboodiri:
Panoramic Stereo Videos with a Single Camera. CVPR 2016: 3755-3763 - [c11]Xing Liang, Rajat Aggarwal, Alhaji Cherif
, Abba B. Gumel, Giuseppe Mascaro, Ross Maciejewski:
Visualizing Malaria Spread Under Climate Variability. EnvirVis@EuroVis 2016: 29-33 - [c10]Rajat Aggarwal, Anoop M. Namboodiri:
Detection and segmentation of mirror-like surfaces using structured illumination. ICVGIP 2016: 66:1-66:8 - [c9]Sabya Das, Rajat Aggarwal, Zhiyong Wang:
An Interactive Physical Synthesis Methodology for High-Frequency FPGA Designs. ISPD 2016: 117-122 - [c8]Stephen Yang, Aman Gayasen, Chandra Mulpuri, Sainath Reddy, Rajat Aggarwal:
Routability-Driven FPGA Placement Contest. ISPD 2016: 139-143 - 2015
- [c7]Rajat Aggarwal, Sirnam Swetha, Anoop M. Namboodiri, Jayanthi Sivaswamy, C. V. Jawahar:
Online handwriting recognition using depth sensors. ICDAR 2015: 1061-1065 - 2014
- [c6]Rajat Aggarwal:
FPGA place & route challenges. ISPD 2014: 45-46
2000 – 2009
- 2009
- [j2]Jarrod A. Roy, Aaron N. Ng, Rajat Aggarwal, Venky Ramachandran, Igor L. Markov:
Solving modern mixed-size placement instances. Integr. 42(2): 262-275 (2009) - 2008
- [c5]Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal:
Architecture-specific packing for virtex-5 FPGAs. FPGA 2008: 5-13 - 2006
- [c4]Panneerselvam Kolandaivel, Rajat Aggarwal:
A Novel Earthquake Mitigation Information expert System: EMIS. CCECE 2006: 337-340 - [c3]Aaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky Ramachandran:
Solving hard instances of floorplacement. ISPD 2006: 170-177
1990 – 1999
- 1999
- [j1]George Karypis, Rajat Aggarwal, Vipin Kumar, Shashi Shekhar:
Multilevel hypergraph partitioning: applications in VLSI domain. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 69-79 (1999) - 1997
- [c2]George Karypis, Rajat Aggarwal, Vipin Kumar, Shashi Shekhar:
Multilevel Hypergraph Partitioning: Application in VLSI Domain. DAC 1997: 526-529 - [c1]Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita:
Speeding up technology-independent timing optimization by network partitioning. ICCAD 1997: 83-90
Coauthor Index
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