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"An Efficient FPGA Architecture with Turn-Restricted Switch Boxes."

Fatemeh Serajeh-hassani et al. (2024)

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DOI: 10.1145/3643809

access: closed

type: Journal Article

metadata version: 2024-07-04

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  - https://dblp.org/rec/journals/todaes/SerajehhassaniSRPWS24
Fatemeh Serajeh-hassani, Mohammad Sadrosadati, Nezam Rohbani, Sebastian Pointner, Robert Wille, Hamid Sarbazi-Azad:
An Efficient FPGA Architecture with Turn-Restricted Switch Boxes. ACM Trans. Design Autom. Electr. Syst. 29(3): 42:1-42:18 (2024)

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