"A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum ..."

Chung-Chao Cheng et al. (2014)

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DOI: 10.1109/TCSI.2014.2312479

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type: Journal Article

metadata version: 2024-05-07

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Chung-Chao Cheng, Jeng-Da Yang, Huang-Chang Lee, Chia-Hsiang Yang, Yeong-Luh Ueng:
A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9): 2738-2746 (2014)

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