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Jeng-Da Yang

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2010 – 2019

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2014
[j2]
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  - journals/tcas/ChengYLYU14
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  - https://dblp.org/rec/journals/tcas/ChengYLYU14
Chung-Chao Cheng, Jeng-Da Yang, Huang-Chang Lee, Chia-Hsiang Yang, Yeong-Luh Ueng:
A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9): 2738-2746 (2014)
2013
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Yeong-Luh Ueng, Bo-Jhang Yang, Chung-Jay Yang, Huang-Chang Lee, Jeng-Da Yang:
An Efficient Multi-Standard LDPC Decoder Design Using Hardware-Friendly Shuffled Decoding. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(3): 743-756 (2013)

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