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"Formal Probabilistic Timing Verification in RTL."

Jayanand Asok Kumar, Shobha Vasudevan (2013)

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DOI: 10.1109/TCAD.2012.2232706

access: closed

type: Journal Article

metadata version: 2020-09-24

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Jayanand Asok Kumar, Shobha Vasudevan:
Formal Probabilistic Timing Verification in RTL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 788-801 (2013)

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