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ORCIDJayanand Asok Kumar
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2010 – 2019
- 2014
[j3]Jayanand Asok Kumar, Seyed Nematollah Ahmadyan, Shobha Vasudevan:
Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(6): 945-958 (2014)- 2013
- [j2]Jayanand Asok Kumar, Shobha Vasudevan:
Formal Probabilistic Timing Verification in RTL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 788-801 (2013) - [c8]Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan:
Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm. DATE 2013: 21-26 - 2012
- [b1]Jayanand Asok Kumar:
Statistical guarantees of performance for RTL designs. University of Illinois Urbana-Champaign, USA, 2012 - [j1]Jayanand Asok Kumar, Shobha Vasudevan:
Formal Performance Analysis for Faulty MIMO Hardware. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1914-1918 (2012) - [c7]Jayanand Asok Kumar, Shobha Vasudevan:
Verifying dynamic power management schemes using statistical model checking. ASP-DAC 2012: 579-584 - [c6]Jayanand Asok Kumar, Kenneth M. Butler, Heesoo Kim, Shobha Vasudevan:
Early prediction of NBTI effects using RTL source code analysis. DAC 2012: 808-813 - [c5]Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan:
Goal-oriented stimulus generation for analog circuits. DAC 2012: 1018-1023 - 2011
- [c4]Jayanand Asok Kumar, Lingyi Liu, Shobha Vasudevan:
Scaling probabilistic timing verification of hardware using abstractions in design source code. FMCAD 2011: 196-205 - [c3]Jayanand Asok Kumar, Shobha Vasudevan:
Variation-Conscious Formal Timing Verification in RTL. VLSI Design 2011: 58-63 - 2010
- [c2]Jayanand Asok Kumar, Shobha Vasudevan:
Statistical guarantees of performance for MIMO designs. DSN 2010: 467-476 - [c1]Jayanand Asok Kumar, Shobha Vasudevan:
Automatic Compositional Reasoning for Probabilistic Model Checking of Hardware Designs. QEST 2010: 143-152
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