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"Automatic Verification of Arithmetic Circuits in RTL Using Stepwise ..."

Shobha Vasudevan et al. (2007)

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DOI: 10.1109/TC.2007.1073

access: closed

type: Journal Article

metadata version: 2022-06-13

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  - https://dblp.org/rec/journals/tc/VasudevanVSA07
Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham:
Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. IEEE Trans. Computers 56(10): 1401-1414 (2007)

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