"Solder joints layout design and reliability enhancements of wafer level ..."

Chang-Chun Lee et al. (2007)

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DOI: 10.1016/J.MICROREL.2006.09.004

access: closed

type: Journal Article

metadata version: 2024-10-06

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Chang-Chun Lee, Chien-Chen Lee, Hsiao-Tung Ku, Shu-Ming Chang, Kuo-Ning Chiang:
Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology. Microelectron. Reliab. 47(2-3): 196-204 (2007)

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