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"Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable ..."
Sung Kim et al. (2022)
- Sung Kim
, Morteza Fayazi
, Alhad Daftardar
, Kuan-Yu Chen
, Jielun Tan, Subhankar Pal
, Tutu Ajayi
, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti
, David T. Blaauw
, Ronald G. Dreslinski, Hun-Seok Kim
:
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory. IEEE J. Solid State Circuits 57(4): 986-998 (2022)
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