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ORCIDMorteza Fayazi
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2020 – today
- 2025
[j8]Kuan-Yu Chen
, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw:
DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET. IEEE J. Solid State Circuits 60(2): 672-684 (2025)- 2024
- [j7]Kuan-Yu Chen, Thomas Mason Nelson, Alireza Khadem, Morteza Fayazi, Sanjay Sri Vallabh Singapuram, Ronald G. Dreslinski, Nishil Talati, Hun-Seok Kim, David T. Blaauw:
Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication. ACM Trans. Reconfigurable Technol. Syst. 17(4): 61:1-61:32 (2024) - 2023
- [j6]Morteza Fayazi, Morteza Tavakoli Taba, Ehsan Afshari, Ronald G. Dreslinski:
AnGeL: Fully-Automated Analog Circuit Generator Using a Neural Network Assisted Semi-Supervised Learning Approach. IEEE Trans. Circuits Syst. I Regul. Pap. 70(11): 4516-4529 (2023) - [c6]Morteza Tavakoli Taba, S. M. Hossein Naghavi, Morteza Fayazi, Ali Sadeghi, Andreia Cathelin, Ehsan Afshari:
A Compact CMOS 363 GHz Autodyne FMCW Radar with 57 GHz Bandwidth for Dental Imaging. CICC 2023: 1-2 - [c5]Morteza Fayazi, Morteza Tavakoli Taba, Amirata Tabatabavakili, Ehsan Afshari, Ronald G. Dreslinski:
FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method. ICCAD 2023: 1-8 - [i5]Morteza Fayazi, Morteza Tavakoli Taba, Amirata Tabatabavakili, Ehsan Afshari, Ronald G. Dreslinski:
FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method. CoRR abs/2308.02050 (2023) - [i4]Serafina Kamp, Morteza Fayazi, Zineb Benameur-El Youbi, Shuyan Yu, Ronald G. Dreslinski:
Open Information Extraction: A Review of Baseline Techniques, Approaches, and Applications. CoRR abs/2310.11644 (2023) - 2022
- [j5]Zach Colter, Morteza Fayazi, Zineb Benameur-El Youbi, Serafina Kamp, Shuyan Yu, Ronald G. Dreslinski:
Tablext: A combined neural network and heuristic based table extractor. Array 15: 100220 (2022) - [j4]Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim:
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory. IEEE J. Solid State Circuits 57(4): 986-998 (2022) - [j3]Morteza Fayazi, Zachary Colter, Zineb Benameur-El Youbi, Javad Bagherzadeh, Tutu Ajayi, Ronald G. Dreslinski:
FASCINET: A Fully Automated Single-Board Computer Generator Using Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5435-5448 (2022) - [c4]Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw:
A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET. VLSI Technology and Circuits 2022: 202-203 - 2021
- [j2]Morteza Fayazi, Zachary Colter, Ehsan Afshari, Ronald G. Dreslinski:
Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A Review. IEEE Trans. Circuits Syst. I Regul. Pap. 68(6): 2418-2431 (2021) - [c3]Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim:
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. VLSI Circuits 2021: 1-2 - [i3]Zach Colter, Morteza Fayazi, Zineb Benameur-El Youbi, Serafina Kamp, Shuyan Yu, Ronald G. Dreslinski:
Tablext: A Combined Neural Network And Heuristic Based Table Extractor. CoRR abs/2104.11287 (2021) - [i2]Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim:
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. CoRR abs/2109.03024 (2021) - 2020
- [c2]Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David T. Blaauw, Ronald Dreslinski Jr., Benton H. Calhoun, David D. Wentzloff:
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation. VLSI-SoC (Selected Papers) 2020: 65-85 - [c1]Tutu Ajayi, Sumanth Kamineni, Yaswanth K. Cherivirala, Morteza Fayazi, Kyumin Kwon, Mehdi Saligane, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David T. Blaauw, Ronald G. Dreslinski, Benton H. Calhoun, David D. Wentzloff:
An Open-source Framework for Autonomous SoC Design with Analog Block Generation. VLSI-SOC 2020: 141-146
2010 – 2019
- 2019
- [i1]Morteza Fayazi, Ali Fotowat, Zahra Kavehvash:
A Simplified Approach to Two-Port Analysis in Feedback. CoRR abs/1908.10274 (2019) - 2017
- [j1]Morteza Fayazi, Jafar Hasani:
Structural relations between brain-behavioral systems, social anxiety, depression and internet addiction: With regard to revised Reinforcement Sensitivity Theory (r-RST). Comput. Hum. Behav. 72: 441-448 (2017)
Coauthor Index
aka: Ronald Dreslinski Jr.
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last updated on 2025-03-10 21:56 CET by the dblp team
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