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ORCID"An inter-FPGA communication bus with error detection and dynamic clock ..."
Lucas T. Melo et al. (2015)
- Lucas T. Melo, S. H. C. Santana, Abel G. Silva-Filho, Manoel Eusébio de Lima, Victor Wanderley Costa de Medeiros, Marcelo L. M. Marinho
:
An inter-FPGA communication bus with error detection and dynamic clock phase adjustment. J. Braz. Comput. Soc. 21(1): 12:1-12:11 (2015)
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