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Victor Wanderley Costa de Medeiros
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2020 – today
- 2022
- [j6]Diego de Freitas Bezerra, Victor Wanderley Costa de Medeiros, Glauco Estácio Gonçalves:
Discrete controller synthesis applied to smart greenhouse. Sustain. Comput. Informatics Syst. 35: 100679 (2022) - 2021
- [j5]Diego de Freitas Bezerra, Victor Wanderley Costa de Medeiros, Glauco Estácio Gonçalves:
Towards a control-as-a-service architecture for smart environments. Simul. Model. Pract. Theory 107: 102194 (2021)
2010 – 2019
- 2019
- [j4]José Clodoalves da Silva Júnior, Victor Wanderley Costa de Medeiros, Cícero Garrozi, Abelardo Montenegro, Glauco Estácio Gonçalves:
Random forest techniques for spatial interpolation of evapotranspiration data from Brazilian's Northeast. Comput. Electron. Agric. 166 (2019) - 2017
- [j3]Juccelino Rodrigues Alves Barros, Gustavo Rau de Almeida Callou, Glauco Estácio Gonçalves, Victor Wanderley Costa de Medeiros, Carlos Henrique M. Castelletti:
Análise de desempenho de Banco de Dados Relacionais e Não Relacionais em dados genômicos. RITA 24(2): 11-27 (2017) - 2016
- [c8]Antonyus P. A. Ferreira, Joao G. M. Silva, Jefferson R. L. Anjos, Luiz H. A. Figueiroa, Edna Natividade da Silva Barros, Manoel Eusébio de Lima, Victor Wanderley Costa de Medeiros:
A hardware accelerator for the alignment of multiple DNA sequences in forensic identification. ASAP 2016: 186-190 - [c7]Antonyus Pyetro do Amaral Ferreira, Joao G. M. Silva, Jefferson R. L. Anjos, Luiz H. A. Figueiroa, Edna Natividade da Silva Barros, Manoel Eusébio de Lima, Victor Wanderley Costa de Medeiros:
A hardware accelerator for the alignment of multiple DNA sequences. SBCCI 2016: 1-6 - 2015
- [j2]Lucas T. Melo, S. H. C. Santana, Abel G. Silva-Filho, Manoel Eusébio de Lima, Victor Wanderley Costa de Medeiros, Marcelo L. M. Marinho:
An inter-FPGA communication bus with error detection and dynamic clock phase adjustment. J. Braz. Comput. Soc. 21(1): 12:1-12:11 (2015) - [c6]Geraldo Gomes da C. Júnior, Roberta Macêdo M. Gouveia, Victor Wanderley Costa de Medeiros:
Development of an educational application using HCD toolkit and open data on the recife culture. IHC 2015: 41:1-41:10 - 2012
- [j1]Victor Wanderley Costa de Medeiros, Rodrigo Camarotti Ferreira da Rocha, Antonyus Pyetro do Amaral Ferreira, João Paulo Fernandes Barbosa, Abel Guilhermino Silva-Filho, Manoel Eusébio de Lima, Thomas Grosser, Wolfgang Rosenstiel:
FPGA-based architecture to speed-up scientific computation in seismic applications. Int. J. High Perform. Syst. Archit. 4(2): 65-77 (2012) - [c5]Gilliano Ginno Silva de Menezes, Abel G. Silva-Filho, Viviane Lucy Santos de Souza, Victor Wanderley Costa de Medeiros, Manoel Eusébio de Lima, Rodrigo Gandra, Ricardo Bragança:
Energy Estimation Tool FPGA-based Approach for Petroleum Industry. ICPP Workshops 2012: 600-601 - 2011
- [c4]Victor Wanderley Costa de Medeiros, Rodrigo Camarotti Ferreira da Rocha, Antonyus Pyetro do Amaral Ferreira, Bruno Holanda Tavares Charamba Dutra, Abner Corrêa Barros, João Cleber Bezerra Liborio Correia, João Paulo Fernandes Barbosa, Severino José de Barros-Junior, Gilliano Ginno Silva de Menezes, Abel Guilhermino Silva-Filho, Manoel Eusébio de Lima:
Poster: high performance FPGA-based implementation of the seismic modeling of the RTM algorithm. SC Companion 2011: 41-42
2000 – 2009
- 2009
- [c3]Viviane Lucy Santos de Souza, Victor Wanderley Costa de Medeiros, Manoel Eusébio de Lima:
Architecture for dense matrix multiplication on a high-performance reconfigurable system. SBCCI 2009 - 2008
- [c2]Paulo Sérgio Brandão do Nascimento, Victor Wanderley Costa de Medeiros, Viviane Lucy Santos de Souza, Abner Corrêa Barros, Manoel Eusébio de Lima:
A Temporal Partitioning Methodology for Reconfigurable High Performance Computers. ReConFig 2008: 307-312 - [c1]Abner Corrêa Barros, Victor Wanderley Costa de Medeiros, Viviane Lucy Santos de Souza, Paulo Sérgio Brandão do Nascimento, Ângelo Mazer, João Paulo Fernandes Barbosa, Bruno P. Neves, Ismael Santos, Manoel Eusébio de Lima:
Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA. SBCCI 2008: 40-45
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