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ORCID"Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and ..."
Toshiki Kanamoto et al. (2006)
- Toshiki Kanamoto
, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto:
Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3560-3568 (2006)
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