"ASIP acceleration for virtual-to-physical address translation on ..."

Roberto Ammendola et al. (2015)

> Home

Details and statistics

DOI: 10.1016/J.FUTURE.2014.12.012

access: closed

type: Journal Article

metadata version: 2020-02-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/fgcs/AmmendolaBFGGCL15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/fgcs/AmmendolaBFGGCL15
Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Werner Geurts, Gert Goossens, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini:
ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces. Future Gener. Comput. Syst. 53: 109-118 (2015)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.