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"Sequential equivalence checking between system level and RTL descriptions."

Shobha Vasudevan et al. (2008)

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DOI: 10.1007/S10617-008-9033-Z

access: closed

type: Journal Article

metadata version: 2020-10-02

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  - journals/dafes/VasudevanVAT08
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  - https://dblp.org/rec/journals/dafes/VasudevanVAT08
Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham, Jiajin Tu:
Sequential equivalence checking between system level and RTL descriptions. Des. Autom. Embed. Syst. 12(4): 377-396 (2008)

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