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"A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by ..."

Koji Nii et al. (2010)

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DOI: 10.1109/ISSCC.2010.5433817

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Yuuichi Hirano, Toshiaki Iwamatsu, Yuji Kihara:
A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias. ISSCC 2010: 356-357

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