"Minimizing gate capacitances with transistor sizing."

Artur Wróblewski et al. (2001)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2001.922203

access: closed

type: Conference or Workshop Paper

metadata version: 2018-06-28

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/WroblewskiSSN01
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/WroblewskiSSN01
Artur Wróblewski, Otto Schumacher, Christian V. Schimpfle, Josef A. Nossek:
Minimizing gate capacitances with transistor sizing. ISCAS (4) 2001: 186-189

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.