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"Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series."

Krzysztof S. Berezowski, Sarma B. K. Vrudhula (2005)

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DOI: 10.1109/DSD.2005.21

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
  - conf/dsd/BerezowskiV05
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  persistent URL:
  - https://dblp.org/rec/conf/dsd/BerezowskiV05
Krzysztof S. Berezowski, Sarma B. K. Vrudhula:
Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series. DSD 2005: 139-143

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