Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide ..."

Yoshiaki Osada et al. (2023)

> Home

Details and statistics

DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185289

access: closed

type: Conference or Workshop Paper

metadata version: 2023-07-28

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsit/OsadaNNLWLFLC23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsit/OsadaNNLWLFLC23
Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications. VLSI Technology and Circuits 2023: 1-2

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.