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"A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for ..."

Kuan-Yu Chen et al. (2022)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830330

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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  - conf/vlsit/ChenYSTFHFYMDKB22
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  - https://dblp.org/rec/conf/vlsit/ChenYSTFHFYMDKB22
Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw:
A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET. VLSI Technology and Circuits 2022: 202-203

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