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"A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating ..."

Yumito Aoyagi et al. (2023)

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DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185429

access: closed

type: Conference or Workshop Paper

metadata version: 2023-07-28

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  - https://dblp.org/rec/conf/vlsit/AoyagiYTIONNWHC23
Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking. VLSI Technology and Circuits 2023: 1-2

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