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"A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, ..."

Chao-Chieh Li et al. (2016)

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DOI: 10.1109/VLSIC.2016.7573551

access: closed

type: Conference or Workshop Paper

metadata version: 2021-03-10

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  - conf/vlsic/LiTYLCHLLKHCXS16
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Chao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Kenny Hsieh, Mark Chen, Augusto Ronchini Ximenes, Robert Bogdan Staszewski:
A 0.034mm², 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. VLSI Circuits 2016: 1-2

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