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2020 – today
- 2020
[j3]Mu-Shan Lin
, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Ching-Fang Chen, Wen-Hung Huang, Chi-Wei Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee:
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing. IEEE J. Solid State Circuits 55(4): 956-966 (2020)- [j2]Chao-Chieh Li, Min-Shueh Yuan, Yu-Tso Lin, Chia-Chun Liao, Chih-Hsien Chang, Robert Bogdan Staszewski:
A 0.2-V Three-Winding Transformer-Based DCO in 16-nm FinFET CMOS. IEEE Trans. Circuits Syst. 67-II(12): 2878-2882 (2020)
2010 – 2019
- 2019
- [c5]Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Tom Chen, Wen-Hung Huang, Jack Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee:
A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing. VLSI Circuits 2019: 28- - 2018
- [j1]Chao-Chieh Li, Min-Shueh Yuan, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, Robert Bogdan Staszewski:
All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply. IEEE J. Solid State Circuits 53(12): 3660-3671 (2018) - [c4]Min-Shueh Yuan, Chao-Chieh Li, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, Robert Bogdan Staszewski:
A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference. ISSCC 2018: 448-450 - 2017
- [c3]Chao-Chieh Li, Min-Shueh Yuan, Chih-Hsien Chang, Yu-Tso Lin, Chia-Chun Liao, Kenny Hsieh, Mark Chen, Robert Bogdan Staszewski:
19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications. ISSCC 2017: 332-333 - 2016
- [c2]Chao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Kenny Hsieh, Mark Chen, Augusto Ximenes, Robert Bogdan Staszewski:
A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. VLSI Circuits 2016: 1-2 - 2015
- [c1]Tsung-Hsien Tsai, Min-Shueh Yuan, Chih-Hsien Chang, Chia-Chun Liao, Chao-Chieh Li, Robert Bogdan Staszewski:
14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S. ISSCC 2015: 1-3
Coauthor Index
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