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"A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated ..."

Didem Turker et al. (2018)

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DOI: 10.1109/ISSCC.2018.8310342

access: closed

type: Conference or Workshop Paper

metadata version: 2021-04-26

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Didem Turker, Ade Bekele, Parag Upadhyaya, Bob Verbruggen, Ying Cao, Shaojun Ma, Christophe Erdmann, Brendan Farley, Yohan Frans, Ken Chang:
A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs. ISSCC 2018: 378-380

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