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"A reconfigurable distributed all-digital clock generator core with SSC and ..."

Y. William Li et al. (2012)

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DOI: 10.1109/ISSCC.2012.6176934

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Y. William Li, Carlos Ornelas, Hyung Seok Kim, Hasnain Lakdawala, Ashoke Ravi, Krishnamurthy Soumyanath:
A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS. ISSCC 2012: 70-72

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