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"Logic-based row redundancy technique designed in 7nm FinFET technology for ..."

Vivek Nautiyal et al. (2018)

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DOI: 10.1109/ISQED.2018.8357300

access: closed

type: Conference or Workshop Paper

metadata version: 2018-05-15

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  - conf/isqed/NautiyalNBDDSSK18
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Vivek Nautiyal, Nishant Nukala, Fakhruddin Ali Bohra, Sagar Dwivedi, Jitendra Dasani, Satinderjit Singh, Gaurav Singla, Martin Kinkade:
Logic-based row redundancy technique designed in 7nm FinFET technology for embedded SRAMs. ISQED 2018: 274-279

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