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"A power optimization method considering glitch reduction by gate sizing."

Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru (1998)

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DOI: 10.1145/280756.280907

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  dblp key:
  - conf/islped/HashimotoOT98
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Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru:
A power optimization method considering glitch reduction by gate sizing. ISLPED 1998: 221-226

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