Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Systolic VLSI realization of a novel iterative division algorithm over ..."

Chien-Hsing Wu et al. (2001)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2001.922162

access: closed

type: Conference or Workshop Paper

metadata version: 2018-08-16

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/WuWSH01
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/WuWSH01
Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang:
Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. ISCAS (4) 2001: 33-36

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.