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"A 12-bit, 270MS/s pipelined ADC with SHA-eliminating front end."

Xuan Wang et al. (2012)

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DOI: 10.1109/ISCAS.2012.6272160

access: closed

type: Conference or Workshop Paper

metadata version: 2020-08-27

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  dblp key:
  - conf/iscas/WangYZWLWW12
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  - https://dblp.org/rec/conf/iscas/WangYZWLWW12
Xuan Wang, Changyi Yang, Xiaoxiao Zhao, Chao Wu, Fule Li, Zhihua Wang, Bin Wu:
A 12-bit, 270MS/s pipelined ADC with SHA-eliminating front end. ISCAS 2012: 798-801

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