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"A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter."

Chi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee (2007)

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DOI: 10.1109/ISCAS.2007.378359

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  dblp key:
  - conf/iscas/LuWL07
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  - https://dblp.org/rec/conf/iscas/LuWL07
Chi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee:
A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter. ISCAS 2007: 1955-1958

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