"A jitter suppression technique for a 2.48832 Gb/s clock and data recovery ..."

Kiyoshi Ishii, Keiji Kishine, Haruhiko Ichino (2000)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2000.857414

access: closed

type: Conference or Workshop Paper

metadata version: 2017-10-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/IshiiKI00
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/IshiiKI00
Kiyoshi Ishii, Keiji Kishine, Haruhiko Ichino:
A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit. ISCAS 2000: 261-264

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.