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"Low power digital design in FPGAs: a study of pipeline architectures ..."

Andrés D. García, Wayne P. Burleson, Jean-Luc Danger (2000)

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DOI: 10.1109/ISCAS.2000.857496

access: closed

type: Conference or Workshop Paper

metadata version: 2021-02-27

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Andrés D. García, Wayne P. Burleson, Jean-Luc Danger:
Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. ISCAS 2000: 561-564

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