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"An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to ..."

José Ángel Díaz-Madrid et al. (2017)

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DOI: 10.1109/ISCAS.2017.8050484

access: closed

type: Conference or Workshop Paper

metadata version: 2017-10-07

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José Ángel Díaz-Madrid, Ginés Doménech-Asensi, José-Alejandro López Alcantud, M. Oberst:
An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation. ISCAS 2017: 1-4

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