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"Logic gates dynamic modeling by means of an ultra-compact MOS model."

Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo (2012)

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DOI: 10.1109/ISCAS.2012.6272018

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  - conf/iscas/ConsoliGP12
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Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo:
Logic gates dynamic modeling by means of an ultra-compact MOS model. ISCAS 2012: 3250-3253

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