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"Clock-aware ultrascale FPGA placement with machine learning routability ..."
Chak-Wa Pui et al. (2017)
- Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu:
Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). ICCAD 2017: 929-936
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