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"Timing and Power Optimization by Gate Sizing Considering False Paths."

Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru (1996)

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DOI: 10.1109/GLSV.1996.497612

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/glvlsi/ChenOT96
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  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/ChenOT96
Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru:
Timing and Power Optimization by Gate Sizing Considering False Paths. Great Lakes Symposium on VLSI 1996: 154-

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